JPS6332960A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6332960A JPS6332960A JP61176500A JP17650086A JPS6332960A JP S6332960 A JPS6332960 A JP S6332960A JP 61176500 A JP61176500 A JP 61176500A JP 17650086 A JP17650086 A JP 17650086A JP S6332960 A JPS6332960 A JP S6332960A
- Authority
- JP
- Japan
- Prior art keywords
- well
- impurity
- resistance
- effect transistor
- reduce
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 230000005669 field effect Effects 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000000295 complement effect Effects 0.000 claims description 2
- 239000012535 impurity Substances 0.000 abstract description 15
- 238000009792 diffusion process Methods 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 235000014443 Pyrus communis Nutrition 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体基板上に形成されるウエルの構造に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a well formed on a semiconductor substrate.
第４図は、相補型電界効果トランジスタによって構成さ
れた、従来の半導体装置である。こ界効果トランジスタ
を形成する不純物拡散領域＋５１ 、 ＋７１、ゲーＮ
８）Ｉｃよって構成され入力端子（頂と出力端子（９）
を持つ〇
この構造の中には、端子ＶＣＣと端子ＧＮＤの間に等価
的なサイリスタが形成されている。この構造において、
ウエルミ位が変動すると、端子ＶＣＣと端子ＧＮＤ間に
存在する寄生サイリスタがターンオンし、端子ｖＣＣと
端子ＧＮＤ間に異常電流が流れ続ける。これを防ぐため
に、従来までウエルミ位固定用拡散領域を設け、ウエル
ミ位の安定化を計っていた。FIG. 4 shows a conventional semiconductor device composed of complementary field effect transistors. Impurity diffusion regions +51, +71, gate N forming this field effect transistor
8) Ic consists of input terminal (top and output terminal (9)
In this structure, an equivalent thyristor is formed between the terminal VCC and the terminal GND. In this structure,
When the well potential changes, a parasitic thyristor existing between the terminal VCC and the terminal GND is turned on, and an abnormal current continues to flow between the terminal VCC and the terminal GND. In order to prevent this, conventionally a diffusion region for fixing the well position has been provided to stabilize the well position.
次に従来の技術について説明する。第４図のウエル（３
１の不純物濃度は、そのウエル（３１上に形成しようと
するトランジスタの特性によって決まっていた。Next, conventional technology will be explained. Well (3) in Figure 4
The impurity concentration of 1 was determined depending on the characteristics of the transistor to be formed on the well (31).
従来の構造では、ウエル（３１の不純物濃度が一定であ
るため、ウエル（３１上に形成する電界効果トランジス
タの特性にウエル（３；の不純物濃度が制約を受け、ウ
エル（３１の抵抗を充分小さくすることができなかった
。In the conventional structure, since the impurity concentration of the well (31) is constant, the impurity concentration of the well (3) is limited by the characteristics of the field effect transistor formed on the well (31). I couldn't.
この発明は上記のような問題点を解消するためになされ
たもので、ウエル（３）の抵抗を充分小さくすることが
できると共に、その上に形成される電界効果トランジス
タの特性には全く願書を与えない半導体装置を得ること
を目的とする。This invention was made to solve the above-mentioned problems, and it is possible to sufficiently reduce the resistance of the well (3), and the characteristics of the field effect transistor formed thereon do not meet the requirements of the application. The purpose is to obtain a semiconductor device that does not cause any damage.
この発明は、ウエル（３）の不純物濃度を、シリコン基
板１１）表面と、内部で変えることにより、ウエル（３
１を２層構造としたものである。In this invention, by changing the impurity concentration of the well (3) on the surface and inside the silicon substrate 11), the impurity concentration of the well (3) is changed.
1 has a two-layer structure.
この発明によるウエル構造の２層化は、上層のウエル濃
度と、下層の濃度を変える事を可能とする。The two-layer well structure according to the present invention makes it possible to change the well concentration of the upper layer and the concentration of the lower layer.
以下、この発明の一実施例を図に従って説明する。第１
図は、この発明の一実施例による半導体装置の断面構造
図である。シリコン基板Ｉｌ＋、高濃度不純物のウエル
（２）、ウエル（３：、ウエルミ位固定用拡散領域１４
＋、 ｉｌ＋及び、電界効果トランジスタを形成する不
純物・頭載＋５１ 、１７１ 、ゲート（８）、出力端
子（９）、入力端子ｔｌｏ＋より構成されている。ここ
で、ウエルｆ２１ ｉｊ 、その抵抗を小さくするため
、不純物濃度を高くしている。この中の不純物の梨は、
ウエル（３１と同一ならば何でも良い。また、ウエル（
２）とウエルｆ３１は２回以上複数回の拡散により形成
されるものである。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present invention. Silicon substrate Il+, high concentration impurity well (2), well (3:, well position fixing diffusion region 14)
+, il+, impurity/overhead +51, 171 forming a field effect transistor, a gate (8), an output terminal (9), and an input terminal tlo+. Here, in order to reduce the resistance of the well f21 ij, the impurity concentration is increased. The impure pear in this is
Well (anything is fine as long as it is the same as 31. Also, well (
2) and the well f31 are formed by diffusion twice or more times.
この発明により上記実施例かられかるように、ウエル（
２１の抵抗を充分小さくすることができ、筐た、電界効
果トランジスタの特性は、ウエル（３）によって決まる
ため、ウエル（２１の影響ｒ／ｉ受けない。従って従来
のトランジスタ特性を得ることができると共に、ウエル
の抵抗を充分小さくすることができ、ウエルミ位を安定
できる。According to the present invention, as can be seen from the above embodiments, the well (
The resistance of the field effect transistor can be made sufficiently small, and since the characteristics of the field effect transistor are determined by the well (3), they are not affected by the well (21).Therefore, conventional transistor characteristics can be obtained. At the same time, the resistance of the well can be made sufficiently small, and the well position can be stabilized.
第２図と第３図に応用例を示す。第２図は、第１図で、
ウエル（２）とウエルミ位固定用拡散領域（４，６）が
離れていたものである。これによシ、さらにウエル抵抗
を小さくすることができ、ウエルミ位の安定が計れる。Application examples are shown in Figures 2 and 3. Figure 2 is Figure 1,
The well (2) and the well position fixing diffusion regions (4, 6) are separated from each other. In addition, the well resistance can be further reduced and the well position can be stabilized.
第３図は、ツインウエル構造のものであるが、これでは
、それぞれのウエルを２層構造とすることにより、第１
図と同様の効果を達成することができる。Figure 3 shows a twin-well structure, but by making each well a two-layer structure, the first
An effect similar to that shown in the figure can be achieved.
以上のように、この発明によれば、ウエルを２層構造に
したので、ウエルミ位の安定化が計れ、ラッチアップ防
止に効果がある。As described above, according to the present invention, since the well has a two-layer structure, the well level can be stabilized and latch-up can be prevented.
第１図は、発明の一実施例の断面構造図である。第２図
と第８図はこの発明の他の実施例を示す断面図、第４図
は従来の装置の断面図を示す。
ＩＩ＋はシリコン基板、（２）はウエル、（３１は下層
のウエル、（４１はウエルミ位固定用拡散領域、１５１
は不純物拡散領域、（６）はウエルミ位固定用拡散領域
、（７）は不純物拡散領域、（８）はゲー） 、＋９１
は出力端子、（ｌＯｌは入力端子である。
なお、図中、同一符号は同一、父は相当部分を示す。FIG. 1 is a cross-sectional structural diagram of an embodiment of the invention. 2 and 8 are cross-sectional views showing other embodiments of the present invention, and FIG. 4 is a cross-sectional view of a conventional device. II+ is a silicon substrate, (2) is a well, (31 is a lower layer well, (41 is a diffusion region for fixing the well position, 151
is an impurity diffusion region, (6) is a diffusion region for fixing the well position, (7) is an impurity diffusion region, (8) is a gate), +91
is an output terminal, and (lOl is an input terminal. In the figure, the same reference numerals are the same, and the father indicates the corresponding part.
Claims (1)
において、それらのトランジスタの下に形成されるウエ
ルを２層構造とし、下層のウエルの抵抗を低くしたこと
を特徴とする半導体装置。1. A semiconductor device comprising complementary field effect transistors formed on a semiconductor substrate, in which wells formed under the transistors have a two-layer structure, and the resistance of the lower well is reduced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61176500A JPS6332960A (en) | 1986-07-25 | 1986-07-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61176500A JPS6332960A (en) | 1986-07-25 | 1986-07-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6332960A true JPS6332960A (en) | 1988-02-12 |
Family
ID=16014733
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61176500A Pending JPS6332960A (en) | 1986-07-25 | 1986-07-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6332960A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03257961A (en) * | 1990-03-08 | 1991-11-18 | Matsushita Electron Corp | Semiconductor device |
| JPH0786424A (en) * | 1993-06-29 | 1995-03-31 | Nec Corp | Semiconductor device and its manufacture |
-
1986
- 1986-07-25 JP JP61176500A patent/JPS6332960A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03257961A (en) * | 1990-03-08 | 1991-11-18 | Matsushita Electron Corp | Semiconductor device |
| JPH0786424A (en) * | 1993-06-29 | 1995-03-31 | Nec Corp | Semiconductor device and its manufacture |
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