JP2570447B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2570447B2 JP2570447B2 JP1342838A JP34283889A JP2570447B2 JP 2570447 B2 JP2570447 B2 JP 2570447B2 JP 1342838 A JP1342838 A JP 1342838A JP 34283889 A JP34283889 A JP 34283889A JP 2570447 B2 JP2570447 B2 JP 2570447B2
- Authority
- JP
- Japan
- Prior art keywords
- width
- element isolation
- region
- semiconductor device
- isolation region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000002955 isolation Methods 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000005192 partition Methods 0.000 claims 1
- 238000000638 solvent extraction Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に半導体基板表面に設
けられた活性領域間の分離を行う素子分離領域の構造に
関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of an element isolation region for separating active regions provided on a surface of a semiconductor substrate.
従来、この種の半導体装置は、Philips Tech.Rev.−3
1 271（1970）や1971 IEDM No.21−3,No.5−７で紹介さ
れた公知技術であるLOCOS法か又はその最良プロセス技
術により第6,7図に示す様に半導体基板１表面にチャン
ネルストッパー２を設け、その上に厚いフィールド酸化
膜３を形成して素子分離領域としており、特別な配慮は
何も行われていなかった。Conventionally, this type of semiconductor device has been manufactured by Philips Tech. Rev.-3
1271 (1970) or 1971 IEDM No.21-3, No.5-7 A channel stopper 2 is provided, and a thick field oxide film 3 is formed thereon to serve as an element isolation region, and no special consideration is given.
近年、素子の微細化が進みそれにつれて素子分離領域
の幅も小さくなってきているが、上述した従来の半導体
装置では第５図に示す様に素子分離領域の幅（N+拡散層
間隔）が小さくなるにつれ寄性MOSトランジスタのしき
い値電圧が急激に低下するため素子分離領域幅をある一
定の値（第５図の例では１μｍ）以下にすると素子分離
領域の耐圧不良となる可能性が大きくなり素子の歩留り
や信頼性を低下させる原因となるため素子分離領域幅を
縮小できず素子の微細化，高集積化ができないという欠
点がある。Recently, it has become smaller width of the isolation region is advanced as it miniaturization of elements, in the conventional semiconductor device described above the width of the element isolation region as shown in FIG. 5 (N + diffusion layer interval) As the threshold voltage of the MOS transistor decreases sharply as it becomes smaller, if the width of the element isolation region is set to a certain value (1 μm in the example of FIG. 5) or less, the breakdown voltage of the element isolation region may become defective. Since the size of the device becomes large and causes a reduction in the yield and reliability of the device, there is a disadvantage that the width of the device isolation region cannot be reduced and the device cannot be miniaturized and highly integrated.
本発明の半導体装置は、半導体基板に第１および第２
の素子領域を区画するために選択酸化法によって形成さ
れた素子分離酸化膜を設け、前記素子分離酸化膜は、第
１の幅を有する第１の部分と前記第１の幅よりも広い第
２の幅を有する第２の部分をもって前記第１および第２
の素子領域を区画している半導体装置において、前記素
子分離酸化膜の前記第１の部分を限定的に覆うように導
電層を配置し、前記導電層は前記第１の素子領域に形成
された不純物領域に接続されている配線層に接続されて
定電位を受けるという特徴を有する。According to the semiconductor device of the present invention, first and second
An element isolation oxide film formed by a selective oxidation method in order to define an element region, wherein the element isolation oxide film has a first portion having a first width and a second portion wider than the first width. The first and second portions having a second portion having a width of
In the semiconductor device defining the element region, a conductive layer is disposed so as to limitly cover the first portion of the element isolation oxide film, and the conductive layer is formed in the first element region. It is characterized in that it is connected to a wiring layer connected to the impurity region and receives a constant potential.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の平面図、第２図は第１図
のＡ−Ａ′に沿った断面を表す断面図である。第１図に
おいて隣り合う素子領域６間の素子分離領域幅が他の場
所より小さく非常に近接している領域Ａ−Ａ′に沿った
線上に存在するがこの領域上部には定電位源に接続され
た第２の多結晶シリコン電極８が配置されている。この
様にすればこの素子分離領域幅（N+拡散層間隔）が第５
図のグラフに示された寄性MOSトランジスタのしきい値
電圧が低下するような第５図のグラフ上でN+拡散層間隔
が0.6μｍを使った場合でも、上記に定電位源に接続さ
れた第２の結晶シリコン電極が配置されており、通常半
導体装置に供給される電圧は接地電位か又は5Vであり寄
性MOSトランジスタのしきい値電圧はこの時8V程度ある
ためこの寄性MOSトランジスタは供給された電圧が20％
以上変動した場合でも（5V±20％）導通する事がなく各
々の素子領域間の耐圧不良とはならないので、素子分離
領域幅を小さくでき素子の集積度を向上できる。ここで
素子分離領域上に配置された電極に接続される定電位源
としては接地電位である事が望ましいが寄性MOSトラン
ジスタのしきい値電圧よりも低ければ供給電圧レベルで
あっても問題とはならない。FIG. 1 is a plan view of one embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a cross section along AA 'of FIG. In FIG. 1, the width of the element isolation region between adjacent element regions 6 is smaller than that of other places and exists on a line along the very close region AA '. The arranged second polycrystalline silicon electrode 8 is arranged. In this case, the width of the element isolation region (N + diffusion layer interval) becomes the fifth.
Even when the N + diffusion layer interval is 0.6 μm in the graph of FIG. 5 in which the threshold voltage of the parasitic MOS transistor shown in the graph of FIG. A second crystal silicon electrode is disposed, and the voltage normally supplied to the semiconductor device is the ground potential or 5 V, and the threshold voltage of the parasitic MOS transistor is about 8 V at this time. Is the supplied voltage 20%
Even in the case of the above fluctuation, there is no conduction (5 V ± 20%), and there is no breakdown voltage between the respective element regions. Therefore, the width of the element isolation region can be reduced and the degree of integration of the elements can be improved. Here, it is desirable that the constant potential source connected to the electrode arranged on the element isolation region is a ground potential, but if the source voltage is lower than the threshold voltage of the parasitic MOS transistor, there is a problem even if it is at the supply voltage level. Not be.
第３図は本発明の第２の実施例を示す平面図、第４図
はそのＡ−Ａ′に沿った断面を示す断面図である。本実
施例では近接した素子領域を分離する領域上にはゲート
電極と同じ層の第１多結晶シリコン層電極が配置された
構造となっているのでこの電極下には高不純物濃度拡散
層を作るための不純物が導入されないため第１の実施例
に比べて素子分離領域の幅をさらに小さくできる。FIG. 3 is a plan view showing a second embodiment of the present invention, and FIG. 4 is a cross-sectional view showing a cross section along the line AA '. In this embodiment, since the first polycrystalline silicon layer electrode of the same layer as the gate electrode is arranged on the region separating the adjacent device regions, a high impurity concentration diffusion layer is formed under this electrode. Is not introduced, the width of the element isolation region can be further reduced as compared with the first embodiment.
以上説明したように本発明は、半導体基板上に近接し
て設けられた素子領域間の素子分離領域上には定電位源
に接続され素子分離領域を覆い素子領域上にまで延在す
る電極を配置することにより、寄性MOSトランジスタの
しきい値電圧が低下する様な素子分離領域幅を使用した
としても各素子間の耐圧不良を引き起こす事がなく集積
度の高い半導体装置を提供できる効果がある。As described above, according to the present invention, an electrode that is connected to a constant potential source, covers an element isolation region, and extends to an element region is provided on an element isolation region between element regions provided close to a semiconductor substrate. By arranging, even if an element isolation region width that reduces the threshold voltage of a parasitic MOS transistor is used, it is possible to provide a highly integrated semiconductor device without causing a breakdown voltage failure between elements. is there.
第１図は本発明の第１の実施例を示す平面図、第２図は
第１図のＡ−Ａ′線に沿った断面図、第３図は本発明の
第２の実施例を示す平面図、第４図は第３図のＡ−Ａ′
線断面図、第５図は素子分離幅（N+拡散層間隔）と寄性
MOSトランジスタのしきい値電圧との関係を示すグラ
フ、第６図は従来例の平面図、第７図は第６図のＡ−
Ａ′線断面図である。 図において、１……Ｐ型半導体基板、２……チャンネル
ストッパー、３……フィールド酸化膜、４……ゲート酸
化膜、５……第１多結晶シリコン電極、６……N+拡散
層、７……層間絶縁膜、８……第２多結晶シリコン電
極、10……コンタクト孔、11……アルミニウム配線。FIG. 1 is a plan view showing a first embodiment of the present invention, FIG. 2 is a sectional view taken along line AA 'of FIG. 1, and FIG. 3 shows a second embodiment of the present invention. FIG. 4 is a plan view, and FIG.
Fig. 5 shows the element isolation width (N + diffusion layer interval) and characteristic.
FIG. 6 is a graph showing the relationship with the threshold voltage of a MOS transistor, FIG. 6 is a plan view of a conventional example, and FIG.
It is A 'line sectional drawing. In the figure, 1 ... P-type semiconductor substrate, 2 ... Channel stopper, 3 ... Field oxide film, 4 ... Gate oxide film, 5 ... First polycrystalline silicon electrode, 6 ... N + diffusion layer, 7 ... Interlayer insulating film, 8 second polycrystalline silicon electrode, 10 contact hole, 11 aluminum wiring.
Claims (1)
区画するために選択酸化法によって形成された素子分離
酸化膜を設け、前記素子分離酸化膜は、第１の幅を有す
る第１の部分と前記第１の幅よりも広い第２の幅を有す
る第２の部分をもって前記第１および第２の素子領域を
区画している半導体装置において、前記素子分離酸化膜
の前記第１の部分を限定的に覆うように導電層を配置
し、前記導電層は前記第１の素子領域に形成された不純
物領域に接続されている配線層に接続されて定電位を受
けることを特徴とする半導体装置。An element isolation oxide film formed by a selective oxidation method for partitioning a first and a second element region on a semiconductor substrate, wherein the element isolation oxide film has a first width having a first width. And a second portion having a second width wider than the first width to partition the first and second element regions, wherein the first and second element regions are separated from each other. A conductive layer is disposed so as to partially cover the portion, and the conductive layer is connected to a wiring layer connected to an impurity region formed in the first element region and receives a constant potential. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1342838A JP2570447B2 (en) | 1989-12-29 | 1989-12-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1342838A JP2570447B2 (en) | 1989-12-29 | 1989-12-29 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03203352A JPH03203352A (en) | 1991-09-05 |
| JP2570447B2 true JP2570447B2 (en) | 1997-01-08 |
Family
ID=18356886
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1342838A Expired - Fee Related JP2570447B2 (en) | 1989-12-29 | 1989-12-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2570447B2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6023504B2 (en) * | 1980-01-24 | 1985-06-07 | 富士通株式会社 | semiconductor memory device |
| JPS5736842A (en) * | 1980-08-15 | 1982-02-27 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS61283170A (en) * | 1985-06-10 | 1986-12-13 | Nec Corp | Mos integrated circuit device |
-
1989
- 1989-12-29 JP JP1342838A patent/JP2570447B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03203352A (en) | 1991-09-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |