JPS61283170A - Mos integrated circuit device - Google Patents

Abstract

PURPOSE:To more stably operate an MOS integrated circuit device by enclosing the periphery of an N-channel type MOSFET with the gate of a polycrystalline silicon of the first layer, grounding the polycrystalline silicon of the first layer, and using a polycrystalline silicon of the second or the following layers for the gate of the MOSFET, thereby reducing a variation due to a radioactive ray. CONSTITUTION:A polycrystalline silicon 2 of the first layer surrounds a portion to become a MOS transistor. A polycrystalline silicon 3 of the second layer is used as the gate of the MOSFET in the circuit. The silicon 2 is grounded, always regarded as the gate of the MOSFET of nonconductive state, not formed with the MOSFET as a circuit, but used as a gate for separating between diffused layers. The periphery of the MOSFET is formed in a gate structure, and the reduction in the thickness of an oxide film 5 decreases the rate of generating electron-hole pairs in case of emitting radioactive rays. Further, the polycrystalline silicon of the first layer is grounded to eliminate an electric field to suppress the increase in the hole density near the boundary between an SiO2 and an Si.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS integrated circuit device, and particularly to a MOS integrated circuit device with excellent radiation resistance.

[Conventional technology]

Conventionally, in this type of MOS integrated circuit device, as shown in Fig. 2(a)
, As shown in (b), the parts other than the MOSFET are
A thick oxide film 15 called a LOCOS occupies the region, and this LOCOS separates two adjacent N+ diffusion layers 13, and power supply lines, signal lines, etc. can be freely arranged on this LOCOS. There is. In addition, FIGS. 2(a) and (b) show the conventional MO
Mask pattern and B-B' of an example of S integrated circuit device
A line cross-sectional view is shown, and in the figure, 12 is polycrystalline silicon;
14 is a thin oxide film, and 11 is a field mask pattern.

[Problem that the invention seeks to solve]

According to the conventional structure described above, if the power supply or signal line runs on the LOCOS, the wiring is connected to the MOSFET.
When the potential of the wiring exceeds the threshold W pressure (VT2) of that part, that is, the field part, an inversion layer is formed under the thick oxide film, and the two diffusion layers that should be separated are separated. It will be electrically connected.

This VT2 value is designed to be sufficiently larger than the voltage range normally used in the circuit, but if it is affected by radiation due to being mounted on an artificial satellite, The hole density near the boundary with silicon increases and V T, 2
value decreases, and two N+ diffusion layers sandwiching a thick oxide film may be electrically connected by the inversion layer at a potential lower than the power supply voltage.

The present invention eliminates the above-mentioned conventional drawbacks, and provides a MOS that can operate stably, with a small increase in the hole density near the boundary with silicon in the oxide film even under the influence of radiation.
The purpose is to provide integrated circuits.

[Means for solving problems]

The MOS integrated circuit device according to the present invention is an N-channel type M
A first layer of polycrystalline silicon that surrounds the MOSFET is formed on a thin oxide film that includes the source and drain regions of the OSFET, and the potential of the first layer of polycrystalline silicon is the lowest among the MOS integrated circuit devices. In addition, the gate of the MOSFET is configured by using polycrystalline silicon in the second and subsequent layers.

Note that it is effective to increase the effects of the present invention by making the first layer of polycrystalline silicon entirely or partially on a thin oxide film.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) and 1(b) are a mask pattern and a cross-sectional view taken along the line A- in one embodiment of the present invention. Figure 1(a), (
In b), 1 is the field mask pattern;
The inner side is a thin oxide film region 5, and the outer side is a thick oxide film region 6.0, 2 is the first layer of polycrystalline silicon, which surrounds the part that will become a MOS transistor, and 3 is a second layer of polycrystalline silicon. The first layer of polycrystalline silicon 2 is used as the gate of the MOSFET, 4 is the source and drain region of the MOSFET, and the first layer of polycrystalline silicon 2 is grounded.

The second layer of polycrystalline silicon 3 is used as the gate of the MOSFET in the circuit, but the first layer of polycrystalline silicon 2
can be considered as the gate of a MOSFET that is grounded and always in a non-conducting state, and this is a MOSFET as a circuit.
It is not used to form a T, but is used as a gate for isolation between diffusion layers.

Creating a gate structure around the MOSFET and reducing the oxide film thickness can reduce the rate of generation of electron-hole pairs when irradiated with radiation. By grounding, no electric field is applied, and an increase in hole density near the boundary between 5i02 and Si can be suppressed.

〔Effect of the invention〕

As explained above, the present invention is an N-channel MOSFET.
The ET is surrounded by a first layer of polycrystalline silicon gate, the first layer of polycrystalline silicon is grounded, and the MOSF
By using polycrystalline silicon in the second and subsequent layers for the gate of the ET, fluctuations due to radiation are small and stable operation can be achieved.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are a mask pattern and a cross-sectional view taken along line A-A' of an embodiment of the present invention, and FIGS. 2(a) and (b) are
) is a mask pattern and a sectional view taken along line B-8' of an example of a conventional MOS integrated circuit device. 1...Field mask pattern, 2...
...First layer of polycrystalline silicon, 3...Second layer of polycrystalline silicon, 4...Diffusion layer (source, drain/), 5...Thin Oxide film, 6...
Thick oxide film, 11... Field mask pattern, 12... Polycrystalline silicon, 13...
・Diffusion layer, 14... Thin oxide film, 15...
・Thick oxide film. ,ノ・＼ Agent Patent Attorney Susumu Uchihara I I・＼１く−
”′−′ ＼5.＋

Claims (2)

[Claims] (1) In a MOS integrated circuit device including an N-channel MOSFET, the N-channel MOSFET is surrounded by a first polycrystalline silicon layer, and the potential of the first polycrystalline silicon layer is set to the integrated circuit. The MOSFET is set at the lowest potential in the device, and the gate of the MOSFET is made of polycrystalline silicon from the second layer onward.
S integrated circuit device. (2) The MO according to claim (1), wherein the first layer of polycrystalline silicon is entirely or partially on a thin oxide film.
S integrated circuit device.