JP2701853B2 - MIS type semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an MIS (metal insulator semic) constituting an IC.
The present invention relates to a structure for preventing leakage current between elements of an onductor type semiconductor device. 2. Description of the Related Art Conventionally, MOS (metal ox) which is one of MIS type transistors is used.
An MOS type IC having an ide semiconductor type transistor (hereinafter abbreviated as “MOST”) is configured as shown in FIG. Sources 22 and 23 and drains 24 and 25 are formed by forming a P conductivity type diffusion region on an N type silicon semiconductor substrate 21. Gate electrodes 28 and 29 are formed above the P-channel portion via gate oxide films 26 and 27. Further, source electrodes 30 and 31 are provided on the sources 22 and 23, respectively.
The drains 24 and 25 are provided with drain electrodes 32 and 33, respectively. The source 22, the drain 24 and the gate electrode 28 constitute a first MOST1, and the source 23, the drain 25 and the gate electrode 29 constitute a second MOST2. The P-type diffusion layer 34 forms a resistor R, and 35 is one electrode of the resistor R. Incidentally, 36 is an insulating oxide film, and 37 is a protective film. MOST 1 functions as an analog switch, and a signal is input from a source 22 and a signal is output from a drain 24. In such a MOS semiconductor device, a parasitic transistor is formed between the diffusion layer between the elements and the substrate surface, and signal current leaks between the elements. For example, between the source 22 of MOST1 and the diffusion layer 34 forming the resistor R, or
A parasitic transistor is formed between the drain 24 of the MOST2 and the source 23 of the MOST2, and the signal voltage input to the source 22 of the MOST1 causes the diffusion layer 34 constituting the resistor R from the source 22 or the drain 22 to be input from the source 22. According to the output signal voltage, a leakage current flows from the drain 24 to the source 23 of the MOST2 via the surface of the semiconductor substrate 21. This leakage current causes a malfunction of the circuit and a decrease in the operation speed. In order to prevent the leakage current between the elements, diffusion layers 40, 41, 42, and 43 of a conductivity type opposite to the source 22, 23 or the drain 24, 25 of the MOST are formed on the substrate surface between the MOSTs. Yes,
The threshold voltage of the parasitic transistor is increased to prevent a leakage current from flowing between the elements on the substrate surface. In addition to the configuration shown in FIG. 3, a method of forming a thick insulating layer on the surface of the substrate between MOSTs, similarly increasing the threshold voltage of the parasitic transistor, and isolating elements from each other has been adopted. However, when a signal exceeding the power supply voltage is input to the source 22 or the drain 24 of the MOST1 or the source 23 or the drain 25 of the MOST2, the structure of the semiconductor substrate 21 is reduced to the inside of the substrate. Due to the formed parasitic transistor, it was not possible to prevent leakage current between elements flowing inside the substrate 21. Such a leakage current has a problem that it has an adverse effect on high-precision and high-speed circuit operation and increases current consumption. The present invention has been made to solve the above problems, and an object of the present invention is to prevent leakage current between elements in a MOS semiconductor device. Means for Solving the Problems According to an aspect of the invention for solving the above problems, there is provided a semiconductor device having a plurality of source and drain regions formed on a semiconductor substrate and having a conductivity type opposite to the conductivity type of the substrate. An MIS element, a shielding diffusion layer formed between the adjacent elements in the plurality of MIS elements, having the same conductivity type as the source region and the drain region, and being diffused deeper than the source region and the drain region; And an electrode for applying a voltage to the shield diffusion layer, the electrode being connected to a power supply, and the shield diffusion layer allows one of the electrodes to be disposed between the adjacent elements. The operation of a parasitic bipolar transistor formed from the source region or the drain region of the device and the source region or the drain region of the other device and the substrate is suppressed. Characterized in that it. The shielding diffusion layer having the above structure is disposed between the elements and is connected to a power supply, and thus serves as one electrode of the parasitic transistor against leakage current due to the parasitic transistor effect. That is, since a parasitic transistor is formed by the diffusion layer of one element, the shielding diffusion layer, and the semiconductor substrate, formation of a parasitic transistor between elements is prevented. Therefore, the leakage current of one element is absorbed by the shielding diffusion layer or released from the shielding diffusion layer, so that the leakage current is equivalently shielded from other elements, and Is prevented from flowing into the diffusion layer. Further, since the shielding diffusion layer is diffused deeper than the diffusion layer forming the element in the semiconductor substrate, it effectively shields not only a leakage current flowing on the surface of the semiconductor substrate but also a leakage current flowing inside the semiconductor. be able to. EXAMPLES Hereinafter, the present invention will be described based on specific examples. FIG. 1 is a sectional view showing a configuration of a MOS type semiconductor device according to a specific embodiment of the present invention, and FIG. 2 is a circuit diagram corresponding to the semiconductor device. Parts having the same functions as in FIG. 3 are denoted by the same reference numerals. That is, reference numeral 21 denotes an N-type silicon semiconductor substrate, on which a P-type diffusion region is formed on the substrate 21 to form sources 22, 23 and drains 24, 25, and a gate is provided above the P-channel portion. Gate electrodes 28, 29 are formed via oxide films 26, 27. Source electrodes 22 and 23 are provided with source electrodes 30 and 31, and drains 24 and 25 are provided with drain electrodes 32 and 33. MOST1 includes a source 22, a drain 24, and a gate electrode 28, and MOST2 includes a source 23, a drain 25,
And a gate electrode 29. The resistor R is formed by a P-type diffusion layer 34, and 35 is one electrode of the resistor R. Incidentally, 36 is an insulating oxide film, and 37 is a protective film. In the above configuration, the source 22 of MOST1 and the resistor R
A P-type shielding diffusion layer 50 having the same conductivity type as the source 22 is formed between the diffusion layer 34 and the diffusion layer 34, and the same as the drain 24 between the drain 24 of MOST1 and the source 23 of MOST2. And a P-type shield diffusion layer 51 of the conductive type of FIG. Then, the shield diffusion layer 51 and the shield diffusion layer 50 through the diffusion layer 52 and the P ⁺ conductivity type diffusion layer 53 of P ⁺ conductivity type, the electrode 54 and the electrode 55 are connected. The electrodes 54 and 55 are connected to the power supply voltage E. MOST1 functions as an analog switch, and source 2
A signal is input from 2 and a signal is output from the drain 24. Now, when a signal exceeding the range of the power supply voltage E is input to the source electrode 30 of the MOST1, a parasitic transistor based on the N-type semiconductor substrate 21 is formed. On the other hand, a leakage current tends to flow. However, the P-type shield diffusion layer 50 exists in the path of the leakage current,
Since the depth of the shield diffusion layer 50 is larger than the depth of the source 22, the leakage current flows into the P-type shield diffusion layer 50,
Is absorbed by the power supply. Therefore, the leakage current flowing out of the source 22 is prevented from flowing into the diffusion layer 34 of the resistor R, which is another element. Next, when a signal exceeding the power supply voltage E is input to the drain electrode 32 of MOST1, a leakage current tries to flow from the drain 24 to the source 23 of the adjacent MOST2 for the same reason as described above. However, the P-type shield diffusion layer 51 exists in the path of the leakage current, and the depth of the shield diffusion layer 51 is different from that of the drain 24.
, The leakage current flows into the P-type shield diffusion layer 51 and is absorbed by the power supply via the electrode 55. Therefore, the leakage current flowing out of the drain 24 is prevented from flowing into the source 23 of the MOST2 as another element. An analog-to-digital converter IC having the configuration of the above embodiment was prepared, and no reduction in conversion accuracy was observed when the input signal was 1 V higher or lower than the range of the power supply voltage E. In the case of the analog-to-digital conversion IC having the conventional configuration, the output value fluctuates by 1%, and the conversion accuracy is reduced. Accordingly, the conversion accuracy of the analog-to-digital conversion IC using the MOS semiconductor device of the configuration of the present invention is improved as compared with the analog-to-digital conversion IC of the conventional configuration. In the above embodiment, the P-type shield diffusion layer 50 and the shield diffusion layer 51 are partially arranged between the diffusion layers constituting the element, but surround the entire periphery of one element, for example, MOST1. Forming in a shape further eliminates the effect of leakage current on other elements. Further, although the shield diffusion layer 50 and the shield diffusion layer 51 are connected to the positive power supply voltage E, similar effects can be obtained by connecting to the ground or a negative power supply voltage. Although the semiconductor substrate 21 is of the N type, it may be of the P type. In this case, the source or drain diffusion layers constituting MOST1 and MOST2 are N-type, and the shielding diffusion layers are also N-type. Further, in this embodiment, the conventional reverse conductivity type diffusion region for preventing the leakage current flowing through the substrate surface is not formed, but the substrate surface between the source 22 of the MOST1 and the shielding diffusion layer 50, the MOST1 Substrate surface between the drain 24 and the shield diffusion layer 51, the substrate surface between the shield diffusion layer 50 and the diffusion layer 34 constituting the resistor R, and the substrate surface between the shield diffusion layer 51 and the source 23 of the MOST2. In addition, a diffusion region of N ⁺ conductivity type may be formed. In the above embodiment, the first diffusion layer to which the input signal is connected is the source 22 of the MOST1, but the diffusion layer to which the input signal is input is not limited to the diffusion layer forming the transistor. A diffusion layer forming a resistor or a diode may be used. For example, there is a case where an input signal is input via a protection resistor or a protection diode. In the above embodiment, the MOS transistor is described. However, the present invention can also be used for a general insulated gate transistor, that is, an MIS transistor. The present invention has a configuration in which a shielded diffusion layer of the same conductivity type as the diffusion layer of each element is formed between the elements, and a deeper shield diffusion layer is formed than the diffusion layer, and the shield diffusion layer is connected to a power supply. A parasitic transistor is constituted by the diffusion layer of each element, the above-mentioned shield diffusion layer and the substrate, and a leakage current flows between the diffusion layer of each element and the shield diffusion layer and is reduced to the power supply. Therefore, the leakage current is prevented from flowing between the elements, so that the malfunction of the semiconductor device is prevented, and the operation speed and processing accuracy are improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing a configuration of a MOS type semiconductor device according to a specific embodiment of the present invention, FIG. 2 is a circuit diagram corresponding to the semiconductor device, FIG. FIG. 1 is a cross-sectional view showing a configuration of a conventional MOS semiconductor device. MOST1, MOST2 MOS transistor 21 Semiconductor substrate 22, 23 Source 24, 25 Drain 28, 29 Gate electrodes 26 27 Gate oxide film 36 Insulating oxide film , 37 ... protective film, 40, 41, 42, 43 ... diffusion layer, 30, 31 ... source electrode, 32, 33 ... drain electrode, 50, 51 ... shielding diffusion layer, 5
4,55 …… electrode

Claims (1)

(57) [Claims] A plurality of MIS elements formed on a semiconductor substrate and having a source region and a drain region having a conductivity type opposite to the conductivity type of the substrate, formed between the adjacent elements in the plurality of MIS elements, the source region and A shielding diffusion layer having the same conductivity type as the drain region and being diffused more deeply than the source region and the drain region; and a shielding diffusion layer disposed on the shielding diffusion layer for applying a voltage to the shielding diffusion layer. Having an electrode, and connecting the electrode to a power supply, and by the shielding diffusion layer, between the adjacent devices, the source region or the drain region of one device and the source region or the drain region of the other device. An MIS-type semiconductor device characterized by suppressing operation of a parasitic bipolar transistor formed from a substrate.