JP3352828B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to SOI (Silicon-On-Ins)
Ulator) relates to semiconductor equipment fabricated on a substrate, in particular,
Even when used in a circuit with inputs from both the source / drain regions, it is possible to suppress the substrate floating effect without complicating the circuit configuration.
About the MISFET); -Effect Transistor.

[0002]

2. Description of the Related Art FIG. 6 shows a structure of a MISFET (SOIMISFET) manufactured on an SOI substrate by a conventional technique. As shown, a buried insulating film 1 formed on a substrate 100 is formed.
01, an island-shaped active region is formed, and source and drain 102, 103, and a channel region 104 are formed in the active region.
A gate insulating film 105 is formed on the channel region 104, and a gate electrode 106 is formed thereon. This SOIMISFET according to the prior art is used as an element for controlling a current between a source and a drain by a voltage applied to a gate electrode. For the source and the drain, the source contact and the drain contact 107 are formed by the insulating film 108, respectively.
It is formed inside and is supplied with a voltage from the outside. However, the channel region 104 has no contact and is in an electrically floating state. Therefore, in the element operating state, when carriers are generated due to impact ionization or the like generated near the boundary between the channel region and the drain, the carriers are accumulated in the channel region 104 in a floating state. The accumulated carriers change the potential of the channel region 104, which may change the threshold voltage V _TH , which is called a substrate floating effect.

FIG. 7 shows the configuration of another example of a conventional SOIMISFET. In the figure, parts corresponding to those in FIG. 6 are denoted by the same reference numerals, and detailed description is omitted. As shown in the figure, the source and drain 1
The body contact region 110 is formed by extending the active region in directions other than 02 and 103, and a body contact 111 for supplying a voltage to the channel region 104 is formed on the body contact region 110. This SOIMISFET is used as an element capable of suppressing a substrate floating effect by supplying a voltage to the body contact 111 from the outside.

FIG. 8 shows a configuration of still another example of the SOIMISFET according to the prior art. Also in this case, as in the case of the above example, the same reference numerals are given to the portions corresponding to FIG. 6, and the detailed description is omitted. In this example, as shown in the figure,
A body contact region 120 is formed in a direction from a part of the channel region 104 toward the source 102, and a body contact 121 for making the potential of the channel region 104 coincide with the source potential is formed on the body contact region 120. Connect with contacts. In this SOIMISFET, since the potential of the channel region 104 is fixed at the source potential, the substrate floating effect can be suppressed without a wiring for supplying a voltage from the outside.

[0005]

[Problems to be Solved by the Invention] SOIMISFET of FIG.
In the case where is used, since the threshold voltage changes due to the substrate floating effect, there is a problem in circuit design. If this problem is to be solved by using the SOIMISFET having the configuration shown in FIG. 7, wiring for supplying a voltage to the body contact is required. Expansion of the area is unavoidable, and its restrictions are great. In the case where a solution is to be achieved by using the SOIMISFET having the configuration shown in FIG. 8, since the region where the body contact is electrically connected must always be used as the source, the relationship between the source and drain alternates.
There is a problem that it cannot be used for a circuit having inputs from both sides. As described above, a method for suppressing the substrate floating effect without sacrificing the degree of freedom in circuit configuration has not been found so far.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and to use a circuit having an input from both a source / drain region without complicating the circuit configuration. Another object of the present invention is to provide a SOIMISFET capable of suppressing a substrate floating effect.

[0007]

In order to solve the above-mentioned problems, a semiconductor device according to the present invention is a metal-insulator-semiconductor field-effect transistor manufactured on an SOI substrate, and comprises an active device.
Channel region, source and drain formed in the region
And a gate electrode formed on the channel region, and
Contact with the serial channel region and formed in the active region which is not in contact with the source and drain, a first region of the same conductivity type as the channel region, in contact with the channel region,
A second conductive layer formed in the active region not in contact with the source and the drain, and having the same conductivity type as the source and the drain;
And a region, and the first region and the second region
The semiconductor device is characterized in that it is electrically connected to each other by a metal contact and has a potential fixing effect on the channel region.

The first region is a lower layer and the second region is a lower layer.
The upper and lower two-layer structure in which the region is an upper layer is connected to the channel region.

[0009]

[0010]

[0011]

[0012]

In the SOIMISFET of the present invention, the active
Region, source and drain formed in conductive region
A gate electrode formed on the channel region;
In contact with the channel region and formed in the active region which is not in contact with the source and drain, a first region of the same conductivity type as the channel region, in contact with the channel region, and into contact with the source and drain A second region having the same conductivity type as the source and the drain, the second region being formed in a non-active region , the first region and the second region having the same conductivity type as the source and the drain.
Has a configuration electrically connected to each other by a metal contact . Here, the channel region and the first region are of the same conductivity type and have substantially the same potential. As a result, the potential of the channel region is equal to the potential of the first region which is electrically connected to the first region. It is configured to be controllable by the potential of the second region. That is, the second region can be regarded as an effective body contact. On the other hand, since the second region is in contact with the channel region, when a certain voltage is input to the gate electrode to make the SOIMISFET operate,
The second region is electrically connected to the source and the drain with a certain connection resistance through the surface of the channel region in the ON state. That is, the structure is such that the effective potential of the body contact is fixed at a constant potential determined by the ratio of the connection resistance. Therefore, by using the SOIMISFET having such a structure, the potential of the channel region is fixed, so that the substrate floating effect can be suppressed. Further, even if the source and the drain are reversed, the SOIMISFET having the same effect is obtained. This can be realized without the need for an external body contact wiring.

[0013]

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the SOIMISFET of the present invention will be specifically described below with reference to embodiments.

[0015]

FIG. 1 shows an N-type SOIMISFE according to an embodiment of the present invention.
FIG. 2 is a diagram showing a schematic configuration of T, (b) is a plan view, (a) is a line of (b)
It is sectional drawing in DD. 1, the same reference numerals are given to portions corresponding to FIG. 6, and detailed description is omitted.
As shown in the figure, a T-type gate electrode 12 is formed on a silicon active region 11, and a source 14 and a drain 15, which are N-type layers, are formed on both sides of the electrode 12. Further, a P-type first region 16 and an N-type second region 17 are formed at positions different from the source 14 and the drain 15 with the gate electrode interposed therebetween. Also, the P-type region 16
The N-type region 17 is mutually connected by a metal contact 18. The metal contact 18 may or may not be connected to an electrode other than the illustrated region.

N-type SOIMISFET having such a structure
When a positive voltage is input to the gate electrode 12 to make the gate electrode 12 operative, the N-type region 17 and the source and drain 14, 1
5 through the surface of the channel region 13 which is in the ON state by the N-type MISFET.
7 is electrically connected to the source and the drains 14 and 15 with a constant connection resistance. Where 14, 15
May be the source, the higher potential side is the drain,
The lower potential side is the source.

Hereinafter, the N-type SOIMISFET of the present invention will be described.
As a result, the configuration in which the potential of the channel region 13 is substantially fixed to the source potential only in the ON state will be described with reference to the equivalent circuit diagram of FIG. As shown in FIG. 2, a drain voltage _Vdd is applied between the source / drain of the N-type SOI MISFET T1, and the parasitic MISFETs T2 and T3 (T2 is connected between the drain and the N-type region 17) are connected in series. Parasitic MISFET, T3 is the parasitic between the N-type region 17 and the source.
MISFET) is connected in parallel to T1. T1, T2, and T3 have gate electrodes all at a common potential. Here, comparing the body contacts of T1, T2, and T3, T2 is on its own low voltage side,
T3 has its own high voltage side connected as a body contact. As is clear from the general properties of the MISFET, this structure causes the ON resistance to be lower at T3 than at T2, and as a result, the potential of the N-type region 17 is almost equal to the source potential (ground potential) of T1. . That is, the channel region 13
Has a structure in which the potential of the source is fixed to be substantially the same as the potential on the low voltage side (source potential) of 14 and 15 via the N-type region 17. The potential fluctuation in the region 13 is suppressed.

When the N-type SOIMISFET having such a structure is used, the floating effect of the substrate is suppressed and the region serving as the source (as in the case of the structure in which the body contact is connected to the source described above with reference to FIG. 8). (Low voltage side) is automatically selected and the effective body contact is electrically connected, so even if the source and drain are reversed, the same suppression effect on the substrate floating effect is obtained from the external body contact wiring. This can be realized without using.

Such a structure can be easily formed by a conventional technique such as impurity ion implantation and contact formation. In the above, N-type SOIMIS
Although the case of the FET has been described, the present invention can be applied to a P-type SOIMISFET by changing the polarity.
The positional relationship between the P-type region 16 and the N-type region 17 is free as long as each is in contact with the channel region. For example, the positions may be reversed in FIG. When viewed from above, it is not necessary that the N-type region surrounds the P-type region, and a plurality of stripes may be arranged when viewed from above.

[0020]

FIG. 3 shows an N-type SOIMIS according to another embodiment of the present invention.
FIG. 2 is a diagram showing a schematic configuration of an FET, in which (b) is a plan view and (a) is a cross-sectional view taken along line EE of (b). 3, parts corresponding to those in FIGS. 1 and 6 are denoted by the same reference numerals, and detailed description is omitted. In this case, a source 14 and a drain 15 as N-type layers are formed on the left and right sides of the gate electrode 12. Further, with the gate electrode 12 interposed therebetween, the source 14 and the drain 15
An active region having a P-type region 20 in the lower region and an N-type region 21 in the upper region is formed at a position different from the active region. The P-type region 20 and the N-type region 21
Interconnected by In addition, metal contact
22 may or may not be connected to an electrode other than the illustrated region.

N-type SOIMISFET having such a configuration
As in the first embodiment, the effect of suppressing the floating effect of the substrate can be obtained, and the use of the N-type region / P-type region having the upper and lower two-layer structure minimizes the increase in the element area. Can be suppressed. In the above,
Although the example of the N-type SOIMISFET has been described, the present invention can be applied to the P-type SOIMISFET by changing the polarity.

[0022]

Third Embodiment FIG. 4 is a diagram for explaining an example of <br/> manufacturing procedure of how the MISFET according to the present invention, (a) ~ (d) are cross-sectional views,
(e) shows a plan view of (d). The manufacturing procedure will be described. First, as shown in (a), a channel region 13 and a gate electrode 12 are formed by a known method. Next, the first region 20 is formed at the position shown in FIG. 1B, and the source and drain regions 14 and 15 are formed by using a method such as impurity ion implantation.

Next, an upper film 23 containing impurities necessary for forming the conductivity type of the second region 21 is formed, and solid-phase diffusion is performed by a method such as heat treatment as shown in FIG. Second
Region 21 is formed. At this time, the same solid-phase diffusion also occurs on the source and drain regions 14, but there is no effect since the conduction type of this region is the same as the conduction type of the impurity to be solid-phase diffused. When the upper film 23 is an insulating film, it may be used as it is as an insulating film for forming a contact hole, or may be removed after forming the second region. Also, the second
Region 21 may be formed by using an impurity ion implantation method or the like. Next, a metal contact 22 is formed in a hole which penetrates through the second region 21 and reaches the first region 20 to obtain a structure as shown in FIGS. By using the manufacturing method configured as described above, a structure having a first region below and a second region above can be formed in all the active regions except the channel region and the source / drain.

[0024]

Embodiment 4 FIG. 5 shows a method of manufacturing a MISFET according to the present invention.
7A to 7C are cross-sectional views for explaining another example of the procedure, and FIG. 9D is a plan view of FIG. The manufacturing procedure will be described. First, as shown in FIG. 3A, the channel region 13 and the gate electrode 12 are formed by a known method. Next, (b)
In addition to forming the second region 17 at the position shown in FIG. 7, the source and drain regions 14 and 15 are formed by using a method such as impurity implantation. Second region 17 and source / drain region
Since 14 and 15 have the same conductivity type, they can be formed simultaneously. Next, a metal contact 18 is formed,
(c) and (d) are obtained. Regions other than the channel region, the source, the drain, and the second region 17 automatically function as the first region 30, so that the step of forming the first region is unnecessary.

[0025]

As described above , according to the present invention,
For example, it is possible to solve the problem of the prior art and suppress the substrate floating effect without complicating the circuit configuration even when the circuit is used in a circuit having inputs from both the source / drain regions. SOIMISFET that can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of an N-type SOIMISFET of one embodiment of the present invention.

FIG. 2 is a circuit diagram showing an equivalent circuit of an N-type SOIMISFET according to one embodiment of the present invention.

FIG. 3 is a diagram showing a schematic configuration of an N-type SOIMISFET of another embodiment of the present invention.

Diagram for explaining an example <br/> steps of MISFET manufacturing method according to the invention, FIG.

[5] Other procedures MISFET manufacturing method according to the present invention
The figure for explaining an example .

FIG. 6 is a diagram showing a schematic configuration of an example of a conventional SOIMISFET.

FIG. 7 is a diagram showing a schematic configuration of another example of a SOIMISFET according to the related art.

FIG. 8 is a diagram showing a schematic configuration of still another example of a SOIMISFET according to the related art.

[Explanation of symbols]

11 ... silicon active layer, 12 ... gate electrode, 13 ... channel region, 14 ... source, 15 ... drain, 16 ... first region, 17 ...
2nd area, 18 ... metal contact, 20 ... 1st area, 21
... second region, 22 ... metal contact, 23 ... upper layer film, 30 ...
1st region, 100 ... silicon substrate, 101 ... buried oxide film, 102 ... source, 103 ... drain, 104 ... channel region, 105 ... gate oxide film, 106 ... gate electrode, 107 ... source / drain contact, 108 ... Interlayer insulating film.

Claims (2)

(57) [Claims] 1. A metal insulator semiconductor manufactured on an SOI substrate.
Body field effect transistorAnd Formed in the active area
A channel region, a source and a drain, A gate electrode formed on the channel region; the above Bordering the channel area, andthe aboveSource and Dray
Formed in an active region not in contact with the channel region,
A first region having the same conductivity type as the first region, the first region being in contact with the channel region;
Formed in an active region not in contact with
A second region of the same conductivity type as the rainHas,  The first area and the second areaIs a metal contact
ThanElectrically interconnected to the channel region
It is configured to have a potential fixing action
Semiconductor device. 2. The second region, wherein the first region is a lower layer.
2. The semiconductor device according to claim 1, wherein an upper and lower two-layer structure having the upper layer is connected to the channel region.