JPS61105868A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61105868A
JPS61105868A JP22750784A JP22750784A JPS61105868A JP S61105868 A JPS61105868 A JP S61105868A JP 22750784 A JP22750784 A JP 22750784A JP 22750784 A JP22750784 A JP 22750784A JP S61105868 A JPS61105868 A JP S61105868A
Authority
JP
Japan
Prior art keywords
diffusion layers
drain
phosphorus
diffusion layer
distribution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22750784A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP22750784A priority Critical patent/JPS61105868A/en
Publication of JPS61105868A publication Critical patent/JPS61105868A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To moderate the distribution of electric field in drain part restraining hot electrons from being generated by a method wherein drain diffusion layers in a MOS type FET are formed of two layered structure composed of diluted and concentrated phosphorus diffusion layers. CONSTITUTION:A field oxide film 12, a gate oxide film 13 and a gate electrode 14 are formed on the surface of Si substrate 11 and then source and drain diffusion layers are formed of two layered diffusion layers composed of diluted phosphorus diffusion layers 15, 17 and concentrated phosphorus diffusion layers 16, 18. In such a two layered structure of at least drain diffusion layers composed of diluted and concentrated phosphorus diffusion layers, the distribution of phosphorus diffusion concentration may be moderated since the diffusion coefficient of phosphorus exceeds to that of silicon in the distribution of impurity concentration from the concentrated diffusion layers to the diluted diffusion layers. Therefore the distribution of electric field on the drain part especially on the surface of drain diffusion layers may be moderated to restrain hot electrons from being generated in the drain part.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＭＯ３型ＮＥＴの拡散層の構成に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to the structure of a diffusion layer of an MO3 type NET.

〔従来の技術〕[Conventional technology]

従来、ＭＯ８型ＦＥＴの拡散層構造は、第１図に示す如
く、Ｐ型Ｓｉ基板１の表面にはフィールド酸化膜２．ゲ
ート酸化膜５．ゲート電極４が形成されると共に、ソー
ス及びドレイン拡散領域として、りん（Ｐ）拡散による
低濃度ｎ″″″領域７、その表面に硅素（ＡＥＩ　）拡
散による高濃度？Ｌ−１領域６．８が形成されるのが通
例であった。Conventionally, the diffusion layer structure of an MO8 type FET has a field oxide film 2.2 on the surface of a P-type Si substrate 1, as shown in FIG. Gate oxide film 5. A gate electrode 4 is formed, and a low concentration n'''' region 7 formed by phosphorus (P) diffusion is formed as a source and drain diffusion region, and a high concentration ?L-1 region 6.8 formed by silicon (AEI) diffusion is formed on its surface. was usually formed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、上記従来技術によると有毒な硅素を用いなけれ
ばならないという問題点と、硅素拡散層はなだらかな濃
度分布を得ることが難かしく、その為に、拡散層内の電
界分布もなだらかにならず、２層拡散の目的とするドレ
イン部での電界分布をなだらかにし、ホット・エレクト
ロンの発生をおさえるという事が充分に行えないという
問題点がある。However, according to the above-mentioned conventional technology, there is a problem that toxic silicon must be used, and it is difficult to obtain a smooth concentration distribution in the silicon diffusion layer, and therefore, the electric field distribution in the diffusion layer is also not smooth. However, there is a problem in that it is not possible to sufficiently suppress the generation of hot electrons by smoothing the electric field distribution in the drain region, which is the purpose of double-layer diffusion.

〔問題点を解決するための手段〕[Means for solving problems]

上記、従来技術の問題点を解決するための本発明の基本
的な構成は、半導体装置に於て、ＭＯ８型ＦＥＴの少く
ともドレイン拡散層が薄いりん拡散層と濃いりん拡散層
の２層構造にて形成されて成ることを特徴とする。The basic structure of the present invention for solving the above problems of the prior art is that in a semiconductor device, at least the drain diffusion layer of an MO8 type FET has a two-layer structure of a thin phosphorus diffusion layer and a thick phosphorus diffusion layer. It is characterized by being formed by.

〔作用〕[Effect]

本発明の如く、ＭＯ８型ＦＥＴの少くともドレイン拡散
層を薄いりん拡散層と濃いりん拡散層との２層構造とな
すことにより、少くともドレイン拡散層における電界分
布を濃いりん拡散層から薄いりん拡散層にかけて、なだ
らかな電界分布を得ることができる作用がある。As in the present invention, by forming at least the drain diffusion layer of the MO8 type FET into a two-layer structure consisting of a thin phosphorus diffusion layer and a thick phosphorus diffusion layer, the electric field distribution in at least the drain diffusion layer is changed from the thick phosphorus diffusion layer to the thin phosphorus diffusion layer. There is an effect that a gentle electric field distribution can be obtained across the diffusion layer.

〔実施例〕〔Example〕

以下、実施例により本発明を詳述する。第１図は、本発
明の一実施例を示すＭＯ３型ＦＥＴの断面図である。す
なわち、Ｓ１基板１１の表面には、フィールド酸化膜１
２．ゲート酸化膜１３．ゲート電極１４が形成されると
共に、ソース及びドレインの拡散層は薄いりん拡散層１
５．１７と濃いりん拡散層１６゜１８の２層拡散層によ
り形成されて成る。Hereinafter, the present invention will be explained in detail with reference to Examples. FIG. 1 is a sectional view of an MO3 type FET showing one embodiment of the present invention. That is, the field oxide film 1 is formed on the surface of the S1 substrate 11.
2. Gate oxide film 13. A gate electrode 14 is formed, and a thin phosphorus diffusion layer 1 is formed as a source and drain diffusion layer.
It is formed of two diffusion layers: 5.17 and a dense phosphorus diffusion layer of 16.degree. and 18.degree.

〔発明の効果〕〔Effect of the invention〕

本発明の如く、少くともドレイン拡散層を薄いりん拡散
層と濃いりん拡散層の２層構造となすことにより、従来
の薄いりん拡散層と濃い硅素拡散層による２層構造に比
べて濃い拡散層から薄い拡散層にかけての不純物濃度分
布かりんの拡散係数が硅素の拡散係数より大なるために
、りんの拡散濃度分布がなだらかになり、その結果、ド
レイン部、とりわけドレイン拡散層表面部での電界分布
もなだらかになり、ドレイン部でのホット・エレクトロ
ンの発生を抑制できる効果がある。As in the present invention, by forming at least the drain diffusion layer into a two-layer structure of a thin phosphorus diffusion layer and a thick phosphorus diffusion layer, the diffusion layer becomes thicker than the conventional two-layer structure consisting of a thin phosphorus diffusion layer and a thick silicon diffusion layer. Since the diffusion coefficient of phosphorus is larger than the diffusion coefficient of silicon, the distribution of impurity concentration in the drain region, especially in the surface area of the drain diffusion layer, becomes gradual. This has the effect of suppressing the generation of hot electrons in the drain region.

更に、りんは硅素の如き毒性が少なく、生産上も完全に
生産できるという効果もある。Furthermore, phosphorus has less toxicity than silicon and has the advantage that it can be produced completely.

尚、高濃度りん拡散層を多結晶Ｓｉ層にしても効果は同
じであることは云うまでもない。It goes without saying that the effect is the same even if the high concentration phosphorus diffusion layer is a polycrystalline Si layer.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来技術によるＭＯＳ型’ＦＥＴの断面図、第
２図は本発明の一実施例を示すＭＯ８型ＦＥｉＴの断面
図である。FIG. 1 is a sectional view of a MOS type FET according to the prior art, and FIG. 2 is a sectional view of an MO8 type FEiT showing an embodiment of the present invention.

Claims (1)

【特許請求の範囲】[Claims] 　ＭＯＳ型ＦＥＴの少くともドレイン拡散層が、薄いリ
ン拡散層と濃いリン拡散層の２層構造にて形成されて成
ることを特徴とする半導体装置。A semiconductor device characterized in that at least a drain diffusion layer of a MOS type FET is formed with a two-layer structure of a thin phosphorus diffusion layer and a thick phosphorus diffusion layer.
JP22750784A 1984-10-29 1984-10-29 Semiconductor device Pending JPS61105868A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22750784A JPS61105868A (en) 1984-10-29 1984-10-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22750784A JPS61105868A (en) 1984-10-29 1984-10-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61105868A true JPS61105868A (en) 1986-05-23

Family

ID=16861977

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22750784A Pending JPS61105868A (en) 1984-10-29 1984-10-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61105868A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3935411A1 (en) * 1988-10-24 1990-04-26 Mitsubishi Electric Corp FIELD EFFECT SEMICONDUCTOR DEVICE OR FIELD EFFECT TRANSISTOR AND METHOD FOR THEIR OR THEIR PRODUCTION
US4949136A (en) * 1988-06-09 1990-08-14 University Of Connecticut Submicron lightly doped field effect transistors
WO1991004577A1 (en) * 1989-09-22 1991-04-04 Board Of Regents, The University Of Texas System Hot-carrier suppressed sub-micron misfet device
US5093275A (en) * 1989-09-22 1992-03-03 The Board Of Regents, The University Of Texas System Method for forming hot-carrier suppressed sub-micron MISFET device
US6054743A (en) * 1995-08-17 2000-04-25 Oki Electric Industry Co., Ltd. High voltage MOS transistor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4949136A (en) * 1988-06-09 1990-08-14 University Of Connecticut Submicron lightly doped field effect transistors
DE3935411A1 (en) * 1988-10-24 1990-04-26 Mitsubishi Electric Corp FIELD EFFECT SEMICONDUCTOR DEVICE OR FIELD EFFECT TRANSISTOR AND METHOD FOR THEIR OR THEIR PRODUCTION
WO1991004577A1 (en) * 1989-09-22 1991-04-04 Board Of Regents, The University Of Texas System Hot-carrier suppressed sub-micron misfet device
US5012306A (en) * 1989-09-22 1991-04-30 Board Of Regents, The University Of Texas System Hot-carrier suppressed sub-micron MISFET device
US5093275A (en) * 1989-09-22 1992-03-03 The Board Of Regents, The University Of Texas System Method for forming hot-carrier suppressed sub-micron MISFET device
US6054743A (en) * 1995-08-17 2000-04-25 Oki Electric Industry Co., Ltd. High voltage MOS transistor

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