JPH04260373A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable an influence which a gate electrode or a source electrode which are wired to other isolation islands give to a depletion layer of a drain region to be relaxed and prevent withstand voltage deterioration in a semiconductor integrated circuit where DMOSFET is formed at least at one separation island of a dielectric isolation substrate. CONSTITUTION:Polycrystalline silicon layers 12 and 13 were provided within an insulating film below a gate electrode G and a source electrode S. These polycrystalline silicon layers 12 and 13 should preferably at the same potential as the drain. The polycrystalline silicon layers 12 and 13 operate as a field plate, influence which the gate potential and the source potential give to the depletion layer of the drain region can be relaxed, thus preventing deterioration of withstand voltage.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit using a dielectric isolation substrate, and is particularly suitable for a semiconductor integrated circuit including a high breakdown voltage DMOSFET.

0002

[Prior Art] Figure 4 shows the planar structure of a conventional DMOSFET.
Shown below. Further, a cross-sectional structure taken along line AA' is shown in FIG. This DMOSFET uses double diffusion in each of the dielectric isolation islands in the dielectric isolation substrate to form a four-cell N-channel MOSFET. Here, the dielectric isolation substrate is, as is well known, a plurality of monocrystalline silicon islands separated on a polycrystalline silicon substrate 1 via an insulating film 2 made of a silicon oxide film or the like. This is a substrate for an integrated circuit. Here, N-type impurities are diffused into the dielectric isolation island to form an N-type substrate 3. This N-type substrate 3 becomes the drain of the DMOSFET. Also,
A P type diffusion region 4 is formed on the surface of an N type substrate 3, and an N type diffusion region 5 serving as a source is formed on the surface of this P type diffusion region 4. Then, polycrystalline silicon is deposited via an insulating film 6 made of a silicon oxide film or the like so that an N-channel conductive path is formed on the surface of the P-type diffusion region 4 between the N-type diffusion region 5 and the N-type substrate 3. A gate 7 consisting of the following is arranged.

The drain electrode D is connected to the N-type substrate 3 through a window 8 formed in the insulating film 6. Source electrode S
is connected to the N-type diffusion region 5 and the P-type diffusion region 4 via a window 9 formed in the insulating film 6. The gate electrode G is connected to a gate 7 made of polycrystalline silicon via a window 10 formed in the insulating film 6. These drain, source, and gate electrodes D, S, and G are all made of aluminum wiring, and are wired to other dielectric isolation islands in order to form an integrated circuit. Note that 11 is a guard ring made of a P-type diffusion region.

0004

[Problem to be solved by the invention] The above-mentioned DMOSFET
In this case, the N-type substrate 3 of the dielectric isolation island becomes a drain, and in the case of a high breakdown voltage MOSFET, a depletion layer spreads in this drain to ensure breakdown voltage between the drain and source. However, in order to connect to elements on other dielectric isolation islands, the gate electrode G and source electrode S pass over the drain region via the insulating film 6, and the gate potential and source potential are lower than the drain potential. Therefore, there was a problem in that it affected the shape of the depletion layer in the underlying drain region and deteriorated the breakdown voltage.

The present invention has been made in view of the above points, and its object is to provide a semiconductor integrated circuit in which a DMOSFET is formed on at least one isolation island of a dielectric isolation substrate. The purpose is to alleviate the influence of the gate electrode and source electrode wired on the depletion layer of the drain region, and to prevent breakdown voltage deterioration.

[0006]

[Means for Solving the Problems] In order to solve the above problems, in the semiconductor integrated circuit of the present invention, as shown in FIGS. 1 and 2, at least one isolation island of a dielectric isolation substrate is In a semiconductor integrated circuit in which a DMOSFET is formed and a gate electrode G and a source electrode S are disposed on the surface of an isolation island serving as a drain of the DMOSFET and are drawn out to another isolation island via an insulating film 6, the gate electrode G and the source electrode S This is characterized in that polycrystalline silicon layers 12 and 13 are provided in the insulating film 6 under the insulating film 6.

Note that it is preferable that the potential of the polycrystalline silicon layer 12 provided in the insulating film 6 under the gate electrode G be the same as that of the drain (see FIG. 3). Further, although not particularly shown, it is preferable that the polycrystalline silicon layer 13 provided in the insulating film 6 under the source electrode S is also at the same potential as the drain.

[0008]

[Operation] In the present invention, as described above, the gate electrode G
and a polycrystalline silicon layer 1 in the insulating film 6 under the source electrode S.
2 and 13, the polycrystalline silicon layers 12 and 1
3 acts as a field plate, which can alleviate the influence of the gate potential and source potential on the depletion layer of the drain region, and can prevent deterioration of breakdown voltage.

Note that if the polycrystalline silicon layers 12 and 13 are connected to the drain electrode D to have the same potential as the drain, it is possible to completely eliminate the influence of the gate potential and source potential on the depletion layer in the drain region. can.

0010

[Embodiment] A planar structure of an embodiment of the present invention is shown in FIG.
A cross-sectional structure along line BB' is shown in FIG. In this embodiment, a polycrystalline silicon layer 12 is placed in an insulating film 6 under a gate electrode G made of aluminum wiring. The width of this polycrystalline silicon layer 12 is set to be slightly wider than the width of the gate electrode G. Further, a polycrystalline silicon layer 13 is also arranged in the insulating film 6 under the source electrode S made of aluminum wiring. This polycrystalline silicon layer 1
The width of the source electrode S is set to be slightly wider than the width of the source electrode S. Thereby, each of the polycrystalline silicon layers 12 and 13 acts as a field plate, and can alleviate the influence of the gate potential and source potential on the shape of the depletion layer in the drain region below. Other structures are similar to the conventional example shown in FIGS. 4 and 5. In this embodiment, both polycrystalline silicon layers 12 and 13 are in a floating state.

FIG. 3 shows a planar structure of another embodiment of the present invention. The cross-sectional structure along line CC' is the same as that in FIG. In this embodiment, the polycrystalline silicon layer 12 in the insulating film 6 under the gate electrode G is at the same potential as the drain. Specifically, the polycrystalline silicon layer 12 in the insulating film 6 below the gate electrode G is extended to below the drain electrode D, and the window 1 formed in the insulating film 6 below the drain electrode D is
4, the aluminum wiring of the drain electrode D is connected to the polycrystalline silicon layer 12. Note that the polycrystalline silicon layer 13 in the insulating film 6 under the source electrode S may also be set to the same potential as the drain. In this way, the influence of the gate potential and source potential on the shape of the underlying drain depletion layer can be completely eliminated.

[0012] In the illustrated embodiments, N
Although a channel DMOSFET is illustrated, it goes without saying that the present invention can also be implemented in a P-channel DMOSFET.

[0013]

According to the invention as claimed in claim 1, a DMOSFET is formed on at least one isolation island of a dielectric isolation substrate, and a DMOSFET is drawn out to another isolation island via an insulating film on the surface of the isolation island that becomes the drain of the DMOSFET. In a semiconductor integrated circuit in which a gate electrode and a source electrode are arranged, a polycrystalline silicon layer is provided in an insulating film under the gate electrode and source electrode, so this polycrystalline silicon layer acts as a field plate and changes the gate potential and This has the effect that the influence of the source potential on the depletion layer in the drain region can be alleviated, and the breakdown voltage between the drain and the source can be improved.

According to the second aspect of the invention, by setting the polycrystalline silicon layer at the same potential as the drain, it is possible to completely eliminate the influence of the gate potential and source potential on the depletion layer in the drain region. be.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a first embodiment of the invention.

FIG. 2 is a sectional view of a first embodiment of the invention.

FIG. 3 is a plan view of a second embodiment of the invention.

FIG. 4 is a plan view of a conventional example.

FIG. 5 is a sectional view of a conventional example.

[Explanation of symbols]

1 Polycrystalline silicon substrate 2 Insulating film 3 N type board 4 P-type diffusion region 5 N-type diffusion region 6 Insulating film 7 Gate 8 Window 9 Window 10 Window 11 Guard ring 12 Polycrystalline silicon layer 13 Polycrystalline silicon layer 14 Window D Drain electrode G Gate electrode S Source electrode

Claims (2)

[Claims] 1. A DMOSFET is formed on at least one isolation island of a dielectric isolation substrate, and a gate electrode and a source electrode are arranged on the surface of the isolation island that serves as the drain of the DMOSFET to be drawn out to other isolation islands via an insulating film. 1. A semiconductor integrated circuit characterized in that a polycrystalline silicon layer is provided in an insulating film under a gate electrode and a source electrode. 2. At least one of the polycrystalline silicon layer provided in the insulating film under the gate electrode and the polycrystalline silicon layer provided in the insulating film under the source electrode is set to the same potential as the drain. The semiconductor integrated circuit according to claim 1.