JPH09129878A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce ON resistance of a power MOS FET by increasing the channel width per unit area. SOLUTION: On a P-type silicon substrate 101, an N buried layer 104 is formed, on which an N-type epitaxial layer 102 is formed. An N<+> type drain leading-out layer 105 is formed which penetrates the epitaxial layer 102 and reaches the buried layer 104. A gate electrode 109 is formed, and a P-type diffusion layer 110 turning to a channel region and an N-type diffusion layer 111 turning to a source region are formed by a double diffusion method using the source aperture of the gate electrode. After a first interlayer insulating film 112 is formed and a contact hole is made, a first drain electrode 114 and a source electrode 115 are formed, on which a second interlayer insulating film 116 is formed. After a through hole is formed, a second drain electrode 118 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which at least one output-stage power MOSFET and a small-signal semiconductor element for control are monolithically integrated, and more particularly to a semiconductor device capable of reducing the on-resistance of a power MOSFET. It is.

[0002]

2. Description of the Related Art Conventionally, power MOSFETs have been widely constructed as vertical devices.
FIG. 5 shows VDMOS (Vertical Double-diffused MOS).
FIG. 6 is a cross-sectional view of a power MOSFET having a vertical structure, which is called a vertical structure. However, FIG. 6 is a plan view of the power MOSFET. The illustration of the portion is omitted).

This device is manufactured as follows.
n-type epitaxial layer 2 on n ⁺ -type silicon substrate 201
Then, a gate electrode 209 made of polysilicon or the like is formed on the substrate with a gate oxide film 208 interposed therebetween. The gate electrode 209 has a source opening 209a. Boron is implanted through the source opening 209a to form a p-type diffusion layer 210 serving as a base region (channel region). After forming a photoresist mask in the source opening to introduce the arsenic further by introducing boron and removing the mask, the n ⁺ -type diffusion layer 211 and the back gate region to be a source diffusion layer p ⁺ -type diffusion Layer 22
Form 3 Forming an interlayer insulating film 212 on the substrate surface,
After opening the contact holes, a source electrode 215 is formed, and a drain electrode is formed on the back surface of the substrate to complete the fabrication of the illustrated device.

In recent years, as the cell (basic transistor) density has been improved due to the progress of microfabrication technology, the current path per unit area has increased, and accordingly the on-resistance has decreased. Has a low on-resistance of less than 100 mΩ · mm ² .

However, as the miniaturization proceeds as described above, the channel resistance decreases, but the resistance R _{sub of the} n ⁺ type silicon substrate 201 occupying most of the thickness of the chip cannot be ignored. In other words, the on resistance R _on is a series resistance of each part of the device, and R _on = R _ch + R _jFET + R _epi + R _sub where R _ch : channel resistance R _jFET : junction FET part resistance R _epi : epitaxial layer resistance R _sub : Substrate resistance According to the calculation by the present inventors, when the cell size becomes smaller than 12 × 12 μm, the substrate resistance R _{sub of the} n ⁺ type silicon substrate 201 occupies 30 to 40% of the whole. It turned out to be like that.

Note that the above value is obtained when the gate oxide film thickness = 50
0 °, gate voltage = 10 V, specific resistance of n-type epitaxial layer = 0.4 Ω · cm, thickness of n-type epitaxial layer =
6 μm, specific resistance of n ⁺ type silicon substrate = 0.015Ω ·
cm, n ⁺ type silicon substrate thickness = 270 μm, cell size = 12 × 12 μm. As a method of reducing the resistance of the n ⁺ -type silicon substrate 201, there is a method of increasing the impurity concentration or a method of reducing the thickness, but the former has a problem that the crystallinity of the n-type epitaxial layer 202 deteriorates. Have a problem of wafer cracking due to a decrease in mechanical strength, and all of them have reached their limits.

In addition, since the drain electrode is formed from the back surface of the silicon substrate, there is a problem that it is impossible to increase the number of output power MOSFETs except for a high-side switch whose drain terminal is directly connected to a power supply. These VDMOs
As a solution to the problem of S, an LDMOS (Lateral Double-diffused MO) with drains arranged in the horizontal direction
There is a power MOSFET called S). FIG. 7 shows an LDMOS disclosed in Japanese Patent Application Laid-Open No. 3-257969.
FIG. 8 is a plan view of the same.

As shown in FIG. 7, in the surface region of the n-type epitaxial layer 302 on the p-type silicon substrate 301, an n ⁺ -type drain diffusion layer 305 and a p-type diffusion layer 310 serving as a base layer are provided. In the p-type diffusion layer 310, an n ⁺ -type diffusion layer 311 and a p ⁺ -type diffusion layer 311 which will be source diffusion layers are further formed.
A mold diffusion layer 323 is formed. On the substrate, a gate electrode 309 is formed via a gate oxide film 308, and a first interlayer insulating film 312 is formed thereon. The source electrode 315 and the first drain electrode 3 are formed through a contact hole opened in the first interlayer insulating film 312.
14 are formed. A second interlayer insulating film 3 is formed thereon.
16 and a second drain electrode 318 are formed.

As shown in FIG. 8, a square drain opening (contact hole formed in first interlayer insulating film 312) 305a and a hexagonal source opening (opening formed in gate electrode 309) 309a. Are alternately formed. In the device shown in FIGS. 7 and 8,
The current flows from the n ⁺ -type drain diffusion layer 305 to the n ⁺ -type diffusion layer 311 of the source diffusion layer through the n-type epitaxial layer 302, the inversion layer of the p-type diffusion layer 310, and mainly to the substrate surface. The effect of the substrate resistance is reduced.

[0010]

As described above, in the conventional VDMOS shown in FIGS. 5 and 6, there is a limit to lowering the on-resistance due to the influence of the substrate resistance. In applications other than switches, there has been a problem that it is not possible to increase the number of output power MOSFETs.

In the LDMOS structure shown in FIGS. 7 and 8, the n ⁺ -type drain diffusion layer 30 is located at a position facing the n ⁺ -type diffusion layer 311 in the p-type diffusion layer (channel region) 310.
5, the p-type diffusion layer 310 and n
^{The +} type drain diffusion layers 305 must be alternately arranged, and the cell density cannot be effectively improved. Furthermore, since a channel is not effectively formed in a region where the p-type diffusion layers 310 face each other, the overall on-resistance cannot be significantly reduced.

Further, in the conventional LDMOS, since the p-type diffusion layer and the drain region serving as a channel region is formed on the same plane, the drain diffusion resistance corresponding to the substrate resistance R _sub of the channel resistance and the VDMOS R _dr could not be lowered at the same time. For example, when the withstand voltage is increased to 100 V or more, the ratio of the drain diffusion resistance _{Rdr to} the on-resistance increases. To reduce this, the area of the drain opening 305a must be increased. increasing the area of 305a will be lead inevitably reduced the area of the source apertures 309a, R _ch is not possible to reduce the overall on-resistance to increase.

The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a lateral structure power capable of lowering on-resistance even lower than that of the conventional power MOSFET. It is to provide a power IC including a MOSFET.

[0014]

According to the present invention, there is provided a semiconductor device comprising: a semiconductor substrate;
A first conductivity type semiconductor layer (102) formed thereon, and a buried diffusion layer (1) formed between the semiconductor layer and the semiconductor substrate, the first conductivity type impurity being heavily doped.
04), a plurality of base diffusion layers (110) of the second conductivity type regularly formed in the surface region of the semiconductor layer on the buried diffusion layer, and formed in the surface region of the base diffusion layer. And a source diffusion layer (111) of the first conductivity type, which reaches the buried diffusion layer through the semiconductor layer.
Or a plurality of drain pull-up diffusion layers (105); and a gate electrode (109) having openings on the base diffusion layer and the drain pull-up diffusion layers formed on the semiconductor layer via a gate insulating film. When dividing the semiconductor layer on which the base diffusion layer is formed into a source cell on which the base diffusion layer is formed and a drain cell on which the drain pull-up diffusion layer is formed, a square having one side having a first dimension A source cell block in which one or more first source cells (120) are arranged in the row direction and the column direction, respectively, is arranged with a second dimension longer than the first dimension in the row direction and the column direction; A rectangular second source cell (121) having a first dimension and a second dimension each having a length of each side is disposed between the first source cells. Drain cell is between the area (1
22) is arranged.

[0015] Preferably, the semiconductor layer (10
2) is divided into a plurality of regions by an insulating separation layer (103) penetrating the semiconductor layer, and the buried diffusion layer and the base diffusion layer are formed in one region insulated and separated. Another MOS type transistor and / or a bipolar transistor are formed in the region.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings. 1 and 2 are cross-sectional views of a semiconductor chip for describing an embodiment of the present invention (FIG. 1 is a right half of the cross-sectional view, and FIG. 2 is a left half of the cross-sectional view). As shown in the figure, on a p-type silicon substrate 101,
An n-type epitaxial layer 102 is formed, and a p-type insulating separation layer 103 for electrically isolating the n-type epitaxial layer 102 is formed in the n-type epitaxial layer 102. In each of the separated regions of the n-type epitaxial layer 102, a control bipolar element and a CMOS are formed in addition to the power MOSFET. In the CMOS formation region, n
P-type well layer 1 for forming channel MOSFET
06 is formed. A field insulating film 107 for separating each element is formed on the substrate.

The sheet resistance between the p-type silicon substrate 101 and the n-type epitaxial layer 102 separated from the element is 5 to 5.
An n ⁺ -type buried layer 104 of 20 Ω / □ is formed, and the buried layer 104 is drawn out onto the substrate by an n ⁺ -type drain lead-out layer 105. A p-type diffusion layer 110 serving as a base diffusion layer is formed on the n ⁺ -type buried layer 104, and an n ⁺ -type diffusion layer 111 serving as a source region is formed in a surface region of the p-type diffusion layer. Have been. Although not shown, the n ⁺ type diffusion layer 11
The p ⁺ -type diffusion layer of the back gate region is formed in the region between the two.

A gate oxide film 108 is provided on the surface of the n-type epitaxial layer 102, and a gate electrode 10 made of polysilicon is formed on the gate oxide film 108.
9 are provided. A first interlayer insulating film 112 is provided on the gate electrode 109 and the gate oxide film 108, and first to fourth contact holes 113a to 113d are provided in the first interlayer insulating film 112. Have been. First and fourth contact holes 113a, 1
13d, a first drain electrode 114 electrically connected to the n ⁺ -type drain extraction layer 105 is formed,
In the second and third contact holes 113b and 113c and on the first interlayer insulating film 112, n serving as a source region is provided.
Source electrode 11 electrically connected to ⁺ type diffusion layer 111
5 are formed.

First drain electrode 114, source electrode 1
A second interlayer insulating film 116 is provided on the first interlayer insulating film 15 and the first interlayer insulating film 112, and the second interlayer insulating film 116 has first and second through holes 117a and 1a.
17b is provided. These through holes 117
a, 117b and on the second interlayer insulating film 116,
A second drain electrode 118 connecting between the first drain electrodes 114 is provided so as to completely cover the source electrode 115. A protective insulating film 119 is provided over the second drain electrode 118 and the second interlayer insulating film.
In FIG. 1, only two p-type diffusion layers 110 are shown, but in reality, many p-type diffusion layers are regularly arranged in parallel and perpendicular to the paper surface. Also, n ⁺
The drain drain layer 105 is appropriately disposed not only at the periphery of the element but also between the p-type diffusion layers 110.

In the MOSFET thus formed, the drain current does not pass through the substrate but flows through the n ⁺ type buried layer 1.
04 and through the n ⁺ -type drain extraction layer 105, the drain diffusion resistance R _dr (n ⁺ -type buried layer 1) corresponding to the substrate resistance R _sub in the VDMOS.
04 and n ⁺ -type drain extraction layer 105). Further, since it is not necessary to form the drain diffusion layer on the substrate surface so as to face the source diffusion layer, the source cell density can be improved, and
Since the peripheral region of the diffusion layer 110 substantially functions as a channel region, the effective channel width can be greatly increased, and both the channel resistance R _ch and the junction FET unit resistance R _jFET can be effectively reduced. Can be reduced.

[0021]

Next, an embodiment of the present invention will be described.
This will be described with reference to the pattern diagram of the SFET section. [First Embodiment] FIG. 3 is a plane pattern diagram for explaining a first embodiment of the present invention. A gate electrode having a source opening 109a and a drain opening 109b is formed on the substrate. The p-type diffusion layer 110 and an n ⁺ -type diffusion layer (not shown) serving as a source region
09a through the so-called double diffusion method. Further, an n ⁺ -type drain extraction layer 105 is formed in the drain opening 109b, and is formed by a drain opening 1 formed in a diffusion mask (photoresist).
This is a diffusion layer formed via the layer 05a.

As shown in FIG. 3, the p-type diffusion layer 110
Are formed in the first and second source cells 120 and 121, and the n ⁺ type drain extraction layer 105 is
Formed within 22. In designing, the first source cells 120 are regularly arranged at an equal pitch. Next, the first
The drain cells 122 are regularly arranged at the same pitch as the first source cells 120 at positions diagonal to the source cells 120 of the first type, and at the positions facing the respective sides of the first source cells,
The second source cells 121 are regularly arranged at the same pitch as the first source cells 120.

The pattern of the first source cell 120 is a square, and the dimension A of one side is the width a of the gate electrode 109.
And an opening width b (hereinafter, referred to as a source opening width) of the gate electrode 109 that forms the p-type diffusion layer 110 and the n ⁺ -type diffusion layer 111 by double diffusion. The width a of the gate electrode 109 is designed so as to minimize the resistance _RjFET of the junction FET portion sandwiched by the lateral extension of the p-type diffusion layer 110, and the source opening width b is set to the minimum size of the fine processing technology. Is done. These dimensional designs are the same as the VDMOS design method shown in the conventional drawings, and are values that are reduced every day as the fine processing technology advances. R _ch and R _JFET of the overall on-resistance This design is optimized.

The pattern of the drain cell 122 is square, and the dimension B of one side thereof is the n ⁺ -type drain extraction layer 10.
5 is indicated by the sum of the opening width c of the mask for forming the mask 5, its lateral expansion d, and the offset length e of the n-type epitaxial layer 102. The mask opening width c is designed to have a dimension that minimizes the drain extraction resistance per unit area (resistance given by AR; A: diffusion layer cross-sectional area, R: resistance), and n
The offset length e of the type epitaxial layer 102 is designed in the same manner as the normal withstand voltage design. Further, in order to reduce the drain diffusion resistance R _dr corresponding to the substrate resistance R _sub of the VDMOS, an n ⁺ type buried layer 104 is formed on the p ⁺ type silicon substrate 101 in the region where the source cell and the drain cell are provided. Spreading. With these designs, R _epi in the overall on-resistance and the drain diffusion resistance R _dr corresponding to R _sub are optimized.

The pattern of the second source cell 121 is rectangular, and the dimension of one side is designed to be A designed by the above method, and the other side is designed to be dimension B designed by the above method. For example, if the source cell is composed of only square cells, the length of one side of the drain cell is determined to be an integral multiple of the length of one side of the source cell. Cannot be sufficiently reduced, and the overall on-resistance cannot be sufficiently reduced. However, according to the present invention, by using the above-described design method, the overall on-resistance of the output-stage power MOSFET can be reduced. , The respective resistance values R _ch , R _jFET , R _epi , and R _dr are simultaneously optimized, and the on-resistance as a whole is greatly reduced. FIG. 3 shows two rows containing only source cells.
Although only one row including a source cell and a drain cell is shown, it is possible to configure so as to include more cells by repeating a similar pattern.

[Second Embodiment] A second embodiment of the present invention will be described with reference to FIG. This embodiment is different from the first embodiment only in the design pattern and the manufacturing method, except for the arrangement pattern of each cell. In the cell arrangement of the first embodiment, one second source cell 121 is arranged between the drain cells 122 which are arranged regularly at an equal pitch, and the second source cell 1
Although the first source cell 120 is disposed between the drain cells 21 in this embodiment, the second source cell 121 is disposed between the drain cells.
Are arranged two by two, and the first source cells 120 are arranged two by two between the second source cells 121. With this configuration, the ratio of the source cell to the entire cell can be increased, the cell density can be improved, and the channel resistance _Rch can be reduced.

As described above, in the second embodiment, the channel resistance R _ch is reduced by using a plurality of columns of the first source cells and the second source cells. And the drain diffusion resistance R
_{Since dr} increases, a design that optimizes the number of columns of source cells between drain cells is required. This optimal value is
Although the sum of the R _ch and R _dr is the value that minimizes, the ratio of total resistance value of R _ch and R _dr by the breakdown voltage is different,
It is determined for each breakdown voltage. Naturally is a, if the proportion occupied in the total resistance enough breakdown voltage is low R _ch becomes higher (the breakdown voltage becomes low, the film thickness of the n-type epitaxial layer becomes thin, by the impurity concentration becomes higher, R _epi Therefore, it is more advantageous to increase the cell density by increasing the row arrangement of the source cells.

According to calculations by the present inventors, when the size of A is designed to be about 12 μm and the size of B is designed to be about 17 μm in the cell arrangement of this embodiment shown in FIG.
The withstand voltage of T is 55V and the series resistance is 124mΩ · mm
² (gate voltage = 10 V) was obtained.

[0029]

As described above, in the power MOSFET according to the present invention, the drain current is taken out through the n ⁺ -type buried layer and the n ⁺ -type drain lead-out layer. Can be greatly reduced. Further, since it is not necessary to dispose the source diffusion layer and the drain diffusion layer on the substrate surface so as to face each other, the density of the source cells can be improved, and the channel width per unit area can be increased. it is possible to reduce both the channel resistance R _ch and junction FET unit resistance R _JFET. Therefore, according to the present invention, a high-performance power MO having a high current density and a low on-resistance is provided.
A semiconductor device having an SFET can be provided.

[Brief description of the drawings]

FIG. 1 is a right half of a cross-sectional view for describing an embodiment of the present invention.

FIG. 2 is a left half of a cross-sectional view for describing an embodiment of the present invention.

FIG. 3 is a plane pattern diagram showing the first embodiment of the present invention.

FIG. 4 is a plane pattern diagram showing a second embodiment of the present invention.

FIG. 5 is a sectional view of a first conventional example.

FIG. 6 is a plane pattern diagram of a first conventional example.

FIG. 7 is a sectional view of a second conventional example.

FIG. 8 is a plane pattern diagram of a second conventional example.

[Explanation of symbols]

101, 301 p-type silicon substrate 201 n ⁺ -type silicon substrate 102, 202, 302 n-type epitaxial layer 103 p-type insulating separation layer 104 n ⁺ -type buried layer 105 n ⁺ -type drain extraction layer 105a, 305a Drain opening 305 n ⁺ Drain diffusion layer 106 P-type well layer 107 Field insulating film 108, 208, 308 Gate oxide film 109, 209, 309 Gate electrode 109a, 209a, 309a Source opening of gate electrode 109b Drain opening 110, 210 of gate electrode 310 p-type diffusion layer (base layer; channel region) 111, 211, 311 n ⁺ type diffusion layer (source diffusion layer) 112, 312 first interlayer insulating film 212 interlayer insulating film 113a first contact hole 113b second Contact hole 113c No. Contact hole 113d fourth contact hole 114, 314 first drain electrode 214 drain electrode 115, 215, 315 source electrode 116, 316 second interlayer insulating film 117a first through hole 117b second through hole 118, 318 second drain electrode 119 protective insulating film 120 first source cell 121 second source cell 122 drain cell 223, 323 p ⁺ type diffusion layer (back gate region)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location 9055-4M H01L 29/78 656C (72) Inventor Teruyoshi Mihara 2 Takaracho, Kanagawa-ku, Yokohama-shi, Kanagawa Within Nissan Motor Co., Ltd.

Claims (2)

[Claims] 1. A semiconductor layer of a first conductivity type formed on a semiconductor substrate, and a buried diffusion layer formed between the semiconductor layer and the semiconductor substrate and doped with a first conductivity type impurity at a high concentration. A plurality of base diffusion layers of a second conductivity type regularly formed in a surface region of the semiconductor layer on the buried diffusion layer; and a first conductivity type formed in a surface region of the base diffusion layer. A source diffusion layer, one or more drain pull-up diffusion layers penetrating the semiconductor layer and reaching the buried diffusion layer, the base diffusion layer formed on the semiconductor layer via a gate insulating film, and In a semiconductor device having a gate electrode having an opening on a drain pull-up diffusion layer, the semiconductor layer on which the base diffusion layer is formed is replaced with a source cell on which the base diffusion layer is formed and the drain pull-up. When the cell is divided into drain cells each having a raised diffusion layer, a source cell block in which one or a plurality of square first source cells each having a first dimension on one side are arranged in a row direction and a column direction, respectively. A second dimension longer than the first dimension in each of the direction and the column direction, and between the first source cells, a rectangular shape having the first dimension and the second dimension as the length of each side. 2. A semiconductor device, wherein two source cells are arranged, and a drain cell is arranged in a region sandwiched between the second source cells. 2. The semiconductor layer is separated into a plurality of regions by an insulating separation layer penetrating the semiconductor layer, wherein the buried diffusion layer and the base diffusion layer are formed in one region insulated and separated, 2. The semiconductor device according to claim 1, wherein another MOS type transistor and / or a bipolar transistor are formed in another region that is insulated and separated.