JPH1041499A - Dmos fet of high breakdown voltage - Google Patents
Dmos fet of high breakdown voltageInfo
- Publication number
- JPH1041499A JPH1041499A JP8189229A JP18922996A JPH1041499A JP H1041499 A JPH1041499 A JP H1041499A JP 8189229 A JP8189229 A JP 8189229A JP 18922996 A JP18922996 A JP 18922996A JP H1041499 A JPH1041499 A JP H1041499A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- drift
- source
- type
- impurities
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015556 catabolic process Effects 0.000 title abstract description 13
- 239000012535 impurity Substances 0.000 claims abstract description 23
- 230000005684 electric field Effects 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 13
- 239000012141 concentrate Substances 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract 1
- 108091006146 Channels Proteins 0.000 description 41
- 238000009792 diffusion process Methods 0.000 description 9
- 230000007423 decrease Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000004904 shortening Methods 0.000 description 3
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体の各層が帯
状に形成された横型高耐圧ＤＭＯＳ ＦＥＴ（以下ＤＭ
ＯＳ ＦＥＴと言う）の端部及び折り曲げ部での耐圧の
向上に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral high withstand voltage DMOS FET (hereinafter referred to as DM) in which each layer of a semiconductor is formed in a band shape.
(Referred to as an OS FET) at the end portion and at the bent portion.
【０００２】[0002]
【従来の技術】図４は従来のｎ型ＤＭＯＳ ＦＥＴの基
本的な構造を示す断面図である。ｐ型基板１の中にｐ型
ベース層２が形成されている。この中にソース層３（ｎ
型拡散層）及びコンタクトＰ+層４（ｐ型拡散層）が形
成され、これらソース層３とコンタクトＰ+層４に共通
にソース電極５が接続されている。また、ｐ型基板１の
中にｐ型ベース層２に接してソース層３側にドリフト・
チャンネル６ａ（ｎ型拡散層）が形成されており、この
ドリフト・チャンネル６ａ内にドレイン層７（ｎ型拡散
層）が形成されている。このドレイン層７にはドレイン
電極８が接続されている。一方、ソース層３及びｐ型ベ
ース層２に対向してＬＯＣＯＳ９（絶縁膜）で隔てられ
たゲート電極１０が形成されている。このＬＯＣＯＳ９
はシリコン酸化膜でありＬＯＣＯＳプロセスにより形成
される。上記の加工工程は既に知られたプロセスにより
すすめることができる。2. Description of the Related Art FIG. 4 is a sectional view showing a basic structure of a conventional n-type DMOS FET. A p-type base layer 2 is formed in a p-type substrate 1. The source layer 3 (n
A source diffusion layer) and a contact P + layer 4 (p-type diffusion layer) are formed, and a source electrode 5 is commonly connected to the source layer 3 and the contact P + layer 4. In the p-type substrate 1, there is a drift in contact with the p-type base layer 2 and the source layer 3 side.
A channel 6a (n-type diffusion layer) is formed, and a drain layer 7 (n-type diffusion layer) is formed in the drift channel 6a. The drain electrode 7 is connected to the drain layer 7. On the other hand, a gate electrode 10 is formed facing the source layer 3 and the p-type base layer 2 and separated by a LOCOS 9 (insulating film). This LOCOS9
Is a silicon oxide film formed by a LOCOS process. The above processing steps can be performed by a known process.
【０００３】上記のｎ型ＤＭＯＳ ＦＥＴが通常のＭＯ
Ｓ ＦＥＴと大きく違る点は、ソース電極５とドレイ
ン電極８の間がドリフト・チャンネル６ａの存在により
大きく離れていること（通常のＭＯＳ ＦＥＴにはドリ
フト・チャンネル６ａが無い）、ゲート電極１０に対
向したチャンネルがｐ型ベースでできている点にある。
ここに述べたｎ型ＤＭＯＳ ＦＥＴが高耐圧を吸収でき
るのは、ドリフト・チャンネル長（図４のＬD）を充分
長く取ってあるため、高電圧印加時にｐ形ベース２とド
リフト・チャンネル６ａのｐｎ接合点を起点としてドリ
フト・チャンネル６ａ内に空乏層が広がり、電界の集中
が緩和されるからである。尚、以下の説明の便宜上ソー
ス層とゲート電極のある領域をソース・ゲート領域、ド
レイン層及びドレイン電極のある領域をドレイン領域、
ドレイン層とドリフトチャンネルがある領域をドレイン
・ドリフト領域と大まかに区分して呼ぶ。The above-mentioned n-type DMOS FET is an ordinary MO
The difference from the SFET is that the source electrode 5 and the drain electrode 8 are largely separated by the presence of the drift channel 6a (the normal MOSFET does not have the drift channel 6a). The point is that the opposing channels are formed on a p-type base.
Here in n-type DMOS FET mentioned can absorb a high breakdown voltage, a drift channel length because you have taken enough long (L D in FIG. 4), the p-type base 2 and the drift channels 6a at the time of high voltage application This is because the depletion layer spreads in the drift channel 6a starting from the pn junction and the concentration of the electric field is reduced. For convenience of the following description, a region having a source layer and a gate electrode is a source / gate region, and a region having a drain layer and a drain electrode is a drain region.
The region where the drain layer and the drift channel are located is roughly classified as a drain drift region.
【０００４】次に図４を参照して動作の説明をする。ド
レイン電極８とソース電極５の間に高電圧が印加されて
いるときにゲート電極１０に電圧を印加すると、この電
極に対向するｐ型ベース層２の表面が反転してｎ型のチ
ャンネルができる。この状態では、ドレイン電極８−ド
リフト・チャンネル６ａ−ｎ型反転層（ｐ型ベース層２
の表面にできた反転層）−ソース電極５と電流が流れ
る。この状態をＤＭＯＳ ＦＥＴのｏｎ状態と言い、ド
レイン電極８とソース電極５の間の抵抗をｏｎ抵抗と呼
ぶ。消費電力の低減や発熱を抑えるためにこのｏｎ抵抗
を低くする必要がある。そのために、ドリフト．チャ
ンネル長ＬDを短くする、ドリフト・チャンネルの濃
度を濃くする、等の方法がとられる。しかし、ドリフ
ト．チャンネル長ＬDを短くすると高耐圧化の妨げにな
り、ドリフト・チャンネルの濃度を上げるほど空乏層は
伸び難く耐圧が下がる。そこで、高耐圧化とｏｎ抵抗の
低減のためにＤＭＯＳ ＦＥＴの構造を、ドリフト・
チャンネル長ＬDを大きくとって高耐圧吸収構造にす
る、ドリフト・チャンネル幅を広げてｏｎ抵抗を低減
させる、等の方法をとる。次にその形状パターンの例を
示す。Next, the operation will be described with reference to FIG. When a voltage is applied to the gate electrode 10 while a high voltage is applied between the drain electrode 8 and the source electrode 5, the surface of the p-type base layer 2 facing this electrode is inverted to form an n-type channel. . In this state, the drain electrode 8-drift channel 6a-n-type inversion layer (p-type base layer 2
Current flows through the inversion layer formed on the surface of the source electrode 5) -source electrode 5. This state is called the on state of the DMOS FET, and the resistance between the drain electrode 8 and the source electrode 5 is called the on resistance. It is necessary to reduce the on-resistance in order to reduce power consumption and heat generation. Therefore, drift. Methods such as shortening the channel length L D and increasing the concentration of the drift channel are adopted. However, drift. Shortening the channel length L D hinders high breakdown voltage, and increasing the concentration of the drift channel makes the depletion layer harder to extend and lowers the breakdown voltage. In order to increase the breakdown voltage and reduce the on-resistance, the structure of the DMOS FET has been
Methods such as increasing the channel length L D to provide a high breakdown voltage absorbing structure, and increasing the drift channel width to reduce the on-resistance are adopted. Next, an example of the shape pattern will be described.
【０００５】図５は従来のｎ型ＤＭＯＳ ＦＥＴの各層
の配列パターンを円形にした平面図である。Ｘ−Ｙで表
示した部分の断面は図４のＸ、Ｙにそれぞれ一致する。
図４の符号と同じで、ソース・ゲート領域５１にはソー
ス層３、ソース電極５及びゲート電極１０があり、ドレ
イン領域５２にはドレイン層７及びドレイン電極８があ
り、ドレイン・ドリフト領域５３にはドレイン層７とド
リフト・チャンネル６ｂがある。これらはおおよその配
列パターンを示したものであって細部を示したものでは
ない。図６はｎ型ＤＭＯＳ ＦＥＴの各層の配列パター
ンをトラック形にした平面図である。その他は図５の説
明と同じである。図７はｎ型ＤＭＯＳ ＦＥＴの各層の
配列パターンを櫛形にした平面図である。小円で描いた
端部７１、７２を折り曲げ部と呼んでいる。折り曲げ部
７１の外側が図４のソース・ゲート側（Ｙ側）、内側が
ドレイン側（Ｘ側）にそれぞれ対応する。折り曲げ部７
２では内側がソース・ゲート側（Ｙ側）に外側がドレイ
ン側（Ｘ側）にそれぞれ対応する。製品化にあたっては
小さい面積の中で各層を広く確保するために配列パター
ンを櫛形にすることが多い。しかし、図７に示す折り曲
げ部分７１、７２では他の部分より電界が集中しやすく
耐圧低下の原因になるという問題がある。その他は図５
の説明と同じである。FIG. 5 is a plan view in which the arrangement pattern of each layer of the conventional n-type DMOS FET is circular. The cross section of the portion indicated by XY corresponds to X and Y in FIG. 4, respectively.
4, the source / gate region 51 has the source layer 3, the source electrode 5 and the gate electrode 10, the drain region 52 has the drain layer 7 and the drain electrode 8, and the drain / drift region 53 has the same. Have a drain layer 7 and a drift channel 6b. These show approximate arrangement patterns and do not show details. FIG. 6 is a plan view in which the arrangement pattern of each layer of the n-type DMOS FET has a track shape. Others are the same as the description of FIG. FIG. 7 is a plan view showing the arrangement pattern of each layer of the n-type DMOS FET in a comb shape. The ends 71 and 72 drawn by small circles are called bent portions. The outer side of the bent portion 71 corresponds to the source / gate side (Y side) and the inner side corresponds to the drain side (X side) in FIG. Bending part 7
In 2, the inside corresponds to the source / gate side (Y side), and the outside corresponds to the drain side (X side). In commercialization, the arrangement pattern is often comb-shaped in order to secure each layer widely in a small area. However, the bent portions 71 and 72 shown in FIG. 7 have a problem that the electric field tends to concentrate more than the other portions, which causes a decrease in withstand voltage. Others are Fig.5
It is the same as the description.
【０００６】[0006]
【発明が解決しようとする課題】本発明の目的は、上記
のように折り曲げ部分や端部で起きやすい電界の集中を
抑えて高耐圧のＤＭＯＳ ＦＥＴを実現することにあ
る。SUMMARY OF THE INVENTION It is an object of the present invention to realize a high breakdown voltage DMOS FET by suppressing the concentration of an electric field which tends to occur at a bent portion or an end as described above.
【０００７】[0007]
【課題を解決するための手段】本発明の高耐圧ＤＭＯＳ
ＦＥＴは、半導体基板の一つの面にソース層とコンタ
クト層とを含んだＰベース層と、このＰベース層に隣接
し所定の耐電圧が得られるよう一定の幅をもったドリフ
トチャンネル層と、このドリフトチャンネル層に接する
よう配置したドレイン層とを含み、帯状に形成した横型
ＤＭＯＳ ＦＥＴにおいて、前記帯状に形成した横型Ｄ
ＭＯＳ ＦＥＴの端部や折り曲げ部にある前記ドリフト
・チャンネル層に不純物を注入する領域と注入しない領
域とを交互に設けることにより端部や折り曲げ部の局部
的な電界の集中を防止して耐圧を大きくすることを特徴
とする。また、小型化するために櫛形に形成すると折り
曲げ部の内側に電界が集中して耐圧がさがる。そこで折
り曲げ部の外側にあるドリフト・チャンネル層に、不純
物を注入する領域と注入しない領域とを交互に配置する
と共に、不純物を注入しない領域の形状を適当に選ぶこ
とにより折り曲げ部の局部的な電界の集中を緩和する。SUMMARY OF THE INVENTION A high breakdown voltage DMOS of the present invention
The FET has a P base layer including a source layer and a contact layer on one surface of a semiconductor substrate, a drift channel layer adjacent to the P base layer and having a certain width so as to obtain a predetermined withstand voltage, A lateral DMOS FET including a drain layer disposed in contact with the drift channel layer and having a band shape.
By alternately providing a region into which impurities are implanted and a region into which impurities are not implanted into the drift channel layer at the end or bent portion of the MOS FET, local electric field concentration at the end or bent portion is prevented, and the breakdown voltage is reduced. It is characterized in that it is increased. Further, when the antenna is formed in a comb shape for miniaturization, the electric field is concentrated inside the bent portion, and the withstand voltage decreases. Therefore, the region into which impurities are implanted and the region into which impurities are not implanted are alternately arranged in the drift channel layer outside the bent portion, and the shape of the region into which impurities are not implanted is appropriately selected, so that the local electric field of the bent portion is obtained. Alleviate concentration.
【０００８】[0008]
【発明の実施の形態】以下図面を用いて本発明を説明す
る。図１は本発明の実施の一形態を示したｎ型ＤＭＯＳ
ＦＥＴの構造断面図である。ｐ型基板１の中にｐ型ベ
ース層２が形成されている。この中にソース層３（ｎ型
拡散層）及びコンタクトＰ+層４（ｐ型拡散層）が形成
され、これらソース層３とコンタクトＰ+層４に共通に
ソース電極５が接続されている。また、ｐ型基板１の中
にｐ型ベース層２に接してソース層３側にｎ型ドリフト
・チャンネル６ｂ〜６ｍ（ｎ型拡散層）が形成されてお
り、このｎ型ドリフト・チャンネル６ｂ〜６ｍ内にドレ
イン層７（ｎ型拡散層）が形成されている。このドレイ
ン層７にはドレイン電極８が接続されている。一方、ソ
ース層３及びｐ型ベース層２に対向してＬＯＣＯＳ９
（絶縁膜）で隔てられたゲート電極１０が形成されてい
る。このＬＯＣＯＳ９はＬＯＣＯＳプロセスにより形成
されたシリコン酸化膜である。上記の加工工程は既に知
られたプロセスによることができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is an n-type DMOS showing an embodiment of the present invention.
FIG. 3 is a sectional view of the structure of the FET. A p-type base layer 2 is formed in a p-type substrate 1. A source layer 3 (n-type diffusion layer) and a contact P + layer 4 (p-type diffusion layer) are formed therein, and a source electrode 5 is commonly connected to the source layer 3 and the contact P + layer 4. In the p-type substrate 1, n-type drift channels 6b to 6m (n-type diffusion layers) are formed on the source layer 3 side in contact with the p-type base layer 2, and the n-type drift channels 6b to 6m are formed. A drain layer 7 (n-type diffusion layer) is formed within 6 m. The drain electrode 7 is connected to the drain layer 7. On the other hand, LOCOS 9 faces the source layer 3 and the p-type base layer 2.
Gate electrodes 10 separated by (insulating film) are formed. This LOCOS 9 is a silicon oxide film formed by the LOCOS process. The processing steps described above can be based on known processes.
【０００９】本発明の横型高耐圧ＭＯＳ ＦＥＴの特徴
は、図４で示した従来のｎ形ＤＭＯＳ ＦＥＴと比べ
て、ソース・ゲート領域５１とドレイン領域５２の間に
あるｎ型ドリフト・チャンネル６ｂ〜６ｍ（ｎ型拡散
層）の構造が、折り曲げ部のみで異なっている点にあ
る。即ち、ソース・ゲート領域５１とドレイン領域５２
の間の距離がドリフト・チャンネル６ｂ〜６ｍの存在に
より大きく離れていることに加えて、図７の７１、７２
で示したように折り曲げ部で電界が集中するところでは
不純物を注入する領域と注入しない領域を交互に設ける
ことで前記折り曲げ部の平均的な濃度をさげてゆく。こ
うすることにより空乏層がドリフトチャンネル６ｂ〜６
ｍ全体に伸びやすくなり、折り曲げ部内側の電界の集中
を緩和して耐圧の劣化を防ぐことができる。また、不純
物の濃度を折り曲げ部以外の直線部の最適不純物濃度と
同じとして一定とするならば、不純物を注入しない領域
の幅を広げるほど濃度を薄くしたのと同じ効果を得るこ
とができる。つまり不純物を注入しない領域の形状を適
当に選ぶことにより局所的な電界の集中を緩和すること
ができる。このような電界の集中を緩和する効果はシュ
ミレーションにより予め推定することができる。以上の
理由から図１はソース・ゲート領域５１のｐベース層２
側の電界の集中を緩和するようにドリフト・チャンネル
６ｂ〜６ｍはｐベース層２に近づくほど不純物を注入し
ない領域の幅を広げている。図１は図７の折り曲げ部７
２に対応して描いている。The feature of the lateral high withstand voltage MOS FET of the present invention is that the n-type drift channel 6b to between the source / gate region 51 and the drain region 52 is different from the conventional n-type DMOS FET shown in FIG. The point is that the structure of 6 m (n-type diffusion layer) is different only in the bent portion. That is, the source / gate region 51 and the drain region 52
7 in addition to the fact that the distance between is significantly greater due to the presence of the drift channels 6b-6m.
As shown in the above, where the electric field is concentrated at the bent portion, the region into which impurities are implanted and the region into which impurities are not implanted are alternately provided to reduce the average concentration of the bent portion. By doing so, the depletion layer is changed to drift channels 6b-6
m, it is easy to extend over the entire area, and the concentration of the electric field inside the bent portion can be reduced to prevent the withstand voltage from deteriorating. In addition, if the impurity concentration is made constant and the same as the optimum impurity concentration of the linear portion other than the bent portion, the same effect can be obtained as the width of the region into which the impurity is not implanted becomes wider and the concentration becomes lower. That is, by appropriately selecting the shape of the region into which the impurity is not implanted, local concentration of the electric field can be reduced. The effect of reducing the concentration of the electric field can be estimated in advance by simulation. FIG. 1 shows the p base layer 2 of the source / gate region 51 for the above reasons.
Drift channels 6b to 6m are formed such that the width of the region into which impurities are not implanted increases toward p base layer 2 so as to reduce the concentration of the electric field on the side. FIG. 1 shows the bent portion 7 of FIG.
It is drawn corresponding to 2.
【００１０】図２は本発明のｎ型ＤＭＯＳ ＦＥＴの折
り曲げ部の平面図である。折り曲げ部の加工工程で使用
するホトレジストのマスクパターンを用いてドリフト・
チャンネル６ｂ〜６ｍの形状を分かりやすく示したもの
である。２１は図１のＰベース層２の近傍を包括して示
している。図７であればソース・ゲート領域５１側に対
応する。２２は図１で示したドレイン層７及びドレイン
電極８の近傍を示す。図７であればドレイン領域５２側
に対応する。図２のソース・ゲート領域２１の端部イの
近傍に向かって電界が集中するのでソース・ゲート領域
２１（内側）に向かうほどｐ型基板内の不純物を注入し
ない領域の幅を広げてゆく。上記の不純物を注入しない
領域を作る方法を次に説明する。ドリフト・チャンネル
６ｂ〜６ｍを作るためにｐ型基板の中へｎ型不純物イオ
ンを打ち込む際、ホトレジストにより所定のマスクを設
けてイオンの通過を阻止することにより実現する。本図
はこのマスクパターンを示したものである。図ではイオ
ンを打ち込む部分は点を付してある。（ローハ）〜（オ
−ワ）はドリフト・チャンネル６ｂ〜６ｍ部分（図１）
にイオンを打ち込む幅である。実際にｎ型不純物イオン
を打ち込んでアニールして仕上げるとドリフトチャンネ
ルの幅は図１の６ｂ〜６ｍようにかなり広がったものに
なる。このようにホトレジストのマスクを適宜作成して
直線部と折り曲げ部のドリフトチャンネルの平均濃度を
自由に変えることができる。また、ドリフトチャンネル
のイオン注入工程は１つのマスクを用いて１回で終了さ
せることができるので工程の短縮につながる。FIG. 2 is a plan view of a bent portion of the n-type DMOS FET of the present invention. Using the photoresist mask pattern used in the bending process,
The shapes of the channels 6b to 6m are shown in an easily understandable manner. Reference numeral 21 indicates the vicinity of the P base layer 2 in FIG. 7 corresponds to the source / gate region 51 side. Reference numeral 22 denotes the vicinity of the drain layer 7 and the drain electrode 8 shown in FIG. 7 corresponds to the drain region 52 side. Since the electric field concentrates near the end A of the source / gate region 21 in FIG. 2, the width of the region into which impurities are not implanted in the p-type substrate increases toward the source / gate region 21 (inside). Next, a method for forming the above-described region into which impurities are not implanted will be described. When the n-type impurity ions are implanted into the p-type substrate to form the drift channels 6b to 6m, this is realized by providing a predetermined mask with a photoresist to prevent the passage of the ions. This figure shows this mask pattern. In the figure, the portions where ions are implanted are indicated by dots. (Loha) to (Ohwa) are the drift channels 6b to 6m (Fig. 1)
The width of the ion implantation. When the n-type impurity ions are actually implanted and finished by annealing, the width of the drift channel becomes considerably wide as shown in FIGS. As described above, by appropriately preparing a photoresist mask, the average concentration of the drift channel in the linear portion and the bent portion can be freely changed. In addition, the process of ion-implanting the drift channel can be completed in one process using one mask, which leads to shortening of the process.
【００１１】以上のようにして折り曲げ部のドリフト・
チャンネルの平均濃度を変えた本発明のｎ型ＤＭＯＳ
ＦＥＴの動作を次に説明する。図１のドレイン電極８と
ソース電極５の間に高電圧が印加されているときにゲー
ト電極１０に電圧を印加すると、この電極に対向するｐ
型ベース層２の表面が反転してｎ型のチャンネルができ
る。この状態では、ドレイン電極８−ドリフト・チャン
ネル６ｍ→６ａ−ｎ型反転層（ｐ型ベース層２の表面に
できた反転層）−ソース電極５の経路でゲート電圧に制
御された電流が流れる。これを図２で説明すると、ドレ
イン領域２２から流れ出た電流はドリフト・チャンネル
６ｍ→６ｂ−ソースゲート領域２１の方向に流れる。ド
リフト・チャンネルの平均濃度を半円形のように適宜変
えることにより、電流はソースゲート領域２１のイなど
端部の一点にだけ集中して流れ込むことがなく端部へ分
散して流れ込むようになる。これは電界が端部の一点に
にだけ集中することを防止することであり局部的な耐圧
の低下を防止することになる。尚、図７の７１部分では
図２のソース・ゲート領域２１とドレイン領域２２が入
れ代わった構造となっているが、端部の内側で電界が集
中しないようドリフト・チャンネルの平均濃度を変える
ことは先に説明した７２部分と全く同様にすることがで
きる。図３は電界の局部的な集中を防止したことにより
ＤＭＯＳ ＦＥＴが高耐圧化したことを示している。一
例を見ると、ドリフト・チャンネルの長さＬDを５０μ
ｍとした場合に、ドレイン電極とソース電極の間の耐圧
が従来は４００Ｖであったのに比べて、本願発明のドリ
フト・チャンネル構造にすることで５９０Ｖまで上げる
ことができたことを示している。As described above, the drift of the bent portion
N-type DMOS of the present invention having different average channel density
The operation of the FET will now be described. When a voltage is applied to the gate electrode 10 while a high voltage is applied between the drain electrode 8 and the source electrode 5 in FIG.
The surface of the mold base layer 2 is inverted to form an n-type channel. In this state, a current controlled by the gate voltage flows through the route of the drain electrode 8-the drift channel 6 m → 6 a-the n-type inversion layer (inversion layer formed on the surface of the p-type base layer 2)-the source electrode 5. Referring to FIG. 2, the current flowing from the drain region 22 flows in the direction of the drift channel 6m → 6b—the source gate region 21. By appropriately changing the average concentration of the drift channel into a semicircular shape, the current does not flow into one point such as the end of the source gate region 21 but concentrates and flows into the end. This is to prevent the electric field from being concentrated only at one point at the end, and to prevent a local decrease in withstand voltage. Although the source / gate region 21 and the drain region 22 in FIG. 2 are replaced with each other in a portion 71 in FIG. 7, it is necessary to change the average concentration of the drift channel so that the electric field is not concentrated inside the end portion. Can be exactly the same as the previously described 72 portion. FIG. 3 shows that the breakdown voltage of the DMOS FET has been increased by preventing the local concentration of the electric field. In one example, the length L D of the drift channel is 50 μm.
In the case of m, the withstand voltage between the drain electrode and the source electrode can be increased to 590 V by using the drift channel structure of the present invention, as compared with 400 V in the related art. .
【００１２】[0012]
【発明の効果】高耐圧ＤＭＯＳ ＦＥＴの製品化にあた
って小型化するために、半導体の各層の配列パターンを
櫛形にすることが多い。このため折り曲げ部分では他の
部分より電界が集中しやすく耐圧低下の原因になってい
たが、本発明の方法により電界の集中を抑えて高耐圧の
ＤＭＯＳ ＦＥＴを実現することができた。In commercializing high voltage DMOS FETs, the arrangement pattern of each semiconductor layer is often comb-shaped in order to reduce the size. For this reason, the electric field is more likely to be concentrated in the bent portion than in other portions, causing a decrease in withstand voltage. However, the method of the present invention has realized a DMOS FET with a high withstand voltage by suppressing the concentration of the electric field.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の実施の一形態を示したｎ型ＤＭＯＳ
ＦＥＴの構造断面図である。FIG. 1 shows an n-type DMOS showing an embodiment of the present invention.
FIG. 3 is a sectional view of the structure of the FET.
【図２】本発明のｎ型ＤＭＯＳ ＦＥＴの折り曲げ部を
含む平面図である。FIG. 2 is a plan view including a bent portion of the n-type DMOS FET of the present invention.
【図３】本発明の構造と従来の構造との耐圧比較図であ
る。FIG. 3 is a diagram showing a breakdown voltage comparison between the structure of the present invention and a conventional structure.
【図４】従来のｎ型ＤＭＯＳ ＦＥＴの構造断面図であ
る。FIG. 4 is a structural sectional view of a conventional n-type DMOS FET.
【図５】従来のｎ型ＤＭＯＳ ＦＥＴの平面図である。FIG. 5 is a plan view of a conventional n-type DMOS FET.
【図６】各層の配列パターンがトラック形のｎ型ＤＭＯ
Ｓ ＦＥＴの平面図である。FIG. 6 shows an n-type DMO in which the arrangement pattern of each layer is a track type.
It is a top view of SFET.
【図７】各層の配列パターンが櫛形のｎ型ＤＭＯＳ Ｆ
ＥＴの平面図である。FIG. 7 shows an n-type DMOS F in which the arrangement pattern of each layer is a comb shape.
It is a top view of ET.
１ 半導体基板 ２ ｐベース層 ３ ソース層 ４ コンタクト層 ５ ソース電極 ６ａ、６ｂ〜６ｍ ドリフト・チャンネル ７ ドレイン層 ８ ドレイン電極 ９ 酸化膜 １０ ゲート電極 ２１ ソース・ゲート領域 ２２ ドレイン領域 ７１、７２ 電極のコーナ部分 Reference Signs List 1 semiconductor substrate 2 p base layer 3 source layer 4 contact layer 5 source electrode 6a, 6b to 6m drift channel 7 drain layer 8 drain electrode 9 oxide film 10 gate electrode 21 source / gate region 22 drain region 71, 72 electrode corner part
Claims (1)
クト層とを含んだＰベース層と、このＰベース層に隣接
し所定の耐電圧が得られるよう一定の幅をもったドリフ
トチャンネル層と、このドリフトチャンネル層に接する
よう配置したドレイン層と、前記ソース層からＰベース
層にわたって絶縁膜を介して対向させたゲート電極とを
帯状に形成した横型ＤＭＯＳ ＦＥＴにおいて、 前記帯状に形成した横型ＤＭＯＳ ＦＥＴの端部や折り
曲げ部の外側にある前記ドリフト・チャンネル層に不純
物を注入する領域と注入しない領域とを交互に設けるこ
とにより端部や折り曲げ部の局部的な電界の集中を防止
して耐圧を大きくしたことを特徴とする高耐圧ＤＭＯＳ
ＦＥＴ。1. A P-base layer including a source layer and a contact layer on one surface of a semiconductor substrate, and a drift channel layer adjacent to the P-base layer and having a predetermined width so as to obtain a predetermined withstand voltage. A drain layer disposed in contact with the drift channel layer, and a gate electrode opposed to the source layer from the P base layer via an insulating film in a band shape. By alternately providing a region into which impurities are implanted and a region into which impurities are not implanted into the drift channel layer outside the ends and bent portions of the DMOS FET, local electric field concentration at the ends and bent portions is prevented. High withstand voltage DMOS characterized by increased withstand voltage
FET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8189229A JPH1041499A (en) | 1996-07-18 | 1996-07-18 | Dmos fet of high breakdown voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8189229A JPH1041499A (en) | 1996-07-18 | 1996-07-18 | Dmos fet of high breakdown voltage |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1041499A true JPH1041499A (en) | 1998-02-13 |
Family
ID=16237758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8189229A Pending JPH1041499A (en) | 1996-07-18 | 1996-07-18 | Dmos fet of high breakdown voltage |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1041499A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001102569A (en) * | 1999-09-28 | 2001-04-13 | Fuji Electric Co Ltd | Semiconductor device |
| KR100393201B1 (en) * | 2001-04-16 | 2003-07-31 | 페어차일드코리아반도체 주식회사 | High voltage lateral DMOS transistor having low on-resistance and high breakdown voltage |
| KR100425435B1 (en) * | 2002-02-08 | 2004-03-30 | 페어차일드코리아반도체 주식회사 | Lateral DMOS transistor having RESURF structure and method for fabricating the same |
| JP2007294872A (en) * | 2006-03-29 | 2007-11-08 | Fuji Electric Device Technology Co Ltd | High voltage resistant horizontal mosfet |
| JP2010016041A (en) * | 2008-07-01 | 2010-01-21 | Sharp Corp | Semiconductor device |
| JP2010109343A (en) * | 2008-09-30 | 2010-05-13 | Sanken Electric Co Ltd | Semiconductor device |
| JP2010109344A (en) * | 2008-09-30 | 2010-05-13 | Sanken Electric Co Ltd | Semiconductor device |
| CN102694008A (en) * | 2011-03-22 | 2012-09-26 | 立锜科技股份有限公司 | High voltage component and method for manufacturing the same |
| CN116799040A (en) * | 2023-08-28 | 2023-09-22 | 合肥晶合集成电路股份有限公司 | Semiconductor device with reduced surface electric field and method of manufacturing the same |
-
1996
- 1996-07-18 JP JP8189229A patent/JPH1041499A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001102569A (en) * | 1999-09-28 | 2001-04-13 | Fuji Electric Co Ltd | Semiconductor device |
| KR100393201B1 (en) * | 2001-04-16 | 2003-07-31 | 페어차일드코리아반도체 주식회사 | High voltage lateral DMOS transistor having low on-resistance and high breakdown voltage |
| KR100425435B1 (en) * | 2002-02-08 | 2004-03-30 | 페어차일드코리아반도체 주식회사 | Lateral DMOS transistor having RESURF structure and method for fabricating the same |
| JP2007294872A (en) * | 2006-03-29 | 2007-11-08 | Fuji Electric Device Technology Co Ltd | High voltage resistant horizontal mosfet |
| JP2010016041A (en) * | 2008-07-01 | 2010-01-21 | Sharp Corp | Semiconductor device |
| JP2010109343A (en) * | 2008-09-30 | 2010-05-13 | Sanken Electric Co Ltd | Semiconductor device |
| JP2010109344A (en) * | 2008-09-30 | 2010-05-13 | Sanken Electric Co Ltd | Semiconductor device |
| CN102694008A (en) * | 2011-03-22 | 2012-09-26 | 立锜科技股份有限公司 | High voltage component and method for manufacturing the same |
| CN116799040A (en) * | 2023-08-28 | 2023-09-22 | 合肥晶合集成电路股份有限公司 | Semiconductor device with reduced surface electric field and method of manufacturing the same |
| CN116799040B (en) * | 2023-08-28 | 2023-11-03 | 合肥晶合集成电路股份有限公司 | Semiconductor device with reduced surface electric field and method of manufacturing the same |
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