JPS6216572A - Vertical type semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent an extension in the lateral direction of a first semiconductor layer even when the first semiconductor layer is formed deeply, and to shorten channel length while obviating a punch-through phenomenon by shaping a groove to a semiconductor base body and regulating the edge sections of first and second semiconductor layers by the side surface of the groove. CONSTITUTION:The plane shape of an opening pattern for a polycrystalline silicon film 6 is formed continuously by octagonal extension sections 4A-4C and connecting sections 4D, 4E in narrow width mutually tying adjacent one sides in these three octagonal patterns. l1=l2 holds in a distance l1 between several side of the edge sections 6A of the polycrystalline silicon films 6 in adjacent cells in the horizontal and vertical directions and a distance l2 between respective side of adjacent cells in the oblique direction at that time. Accordingly, the arrangement of cell patterns can be integrated to a central section as a whole in spite of the same design rule by mutually displacing and disposing the cells alternately at every half pitch, thus integrating the cells more than conventional devices.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a vertical semiconductor device for the purpose of switching or amplification and a method of manufacturing the same, and particularly relates to techniques for miniaturization and high performance.

(Prior art) Among MIS type semiconductor devices, MOSFETs in particular were traditionally considered to be low-voltage, low-power devices, but with recent developments in semiconductor manufacturing technology and circuit design technology, they have been It has become possible to design it, and it has now secured its place as a power device.

Typical examples of such high-voltage power MO8FETs include: ■offset gate structure, ■■-G root or U-Q root structure, and ■DSA (Diffusi
On 5elf-Aliarvent) structures are known, but among these, the conventional DSA II power MO8FET (j, (lower D) is advantageous in terms of manufacturing technology and high performance.
FIG. 9 (referred to as SA MOS) is a plan view after electrode formation and a cross-sectional structure diagram taken along line A-A in this plan view.
10(a) to (r) show cross-sectional structures in the sequential manufacturing steps.

However, the source electrode is omitted in FIG. 9(a).

DSA MOS forms a channel by double diffusion, and impurities are added to form the channel region through the same diffusion window surrounded by a lattice-shaped gate polycrystalline silicon 116 formed through gate oxide 1115a. The feature is that diffusion (p-type semiconductor layer 4) and impurity diffusion (n-small semiconductor layer 8) for forming a source region are performed. Since the channel length is determined by the difference in diffusion depth between the p-type semiconductor layer 4 and the n-sized semiconductor layer 8, it can be formed extremely short, several microns or less. The source electrode 9 formed on the insulating film 5d is in ohmic contact with both the n-sized semiconductor layer 8 forming the source region and the p-type semiconductor layer 4 (or the p-type semiconductor layer 3) forming the channel region. . Generally, the gate electrode has a lattice shape or a stripe shape, and the lattice shape is shown here.

The n-type semiconductor substrate 1 is a drain region, and the n-type semiconductor substrate 1 is a drain region on which the n-type semiconductor substrate 1 is formed.
It has an n-on-n+ structure in which a type epitaxial growth layer 2 is deposited. A drain electrode (not shown) is formed on the back surface of the chip, and when a positive voltage is applied between the gate and source to turn on the channel, current flows vertically from the substrate 1, passing through the channel region 4 and reaching the source region. Flows into 8. Note that the broken line in FIG. 9(a) indicates the outline of the opening in the polycrystalline silicon film pattern 6 constituting each cell.

Next, using FIGS. 10(a) to (f),
A The manufacturing process of MOS will be explained. An n-type epitaxial growth layer 2 is formed on an n-type semiconductor substrate 1 with a specific resistance of 1, for example.
After forming a 0 to 25 Ω mark and a thickness of 30 to 60 μm, a p-type semiconductor layer 3 is formed from the surface. After that, the gate oxide film 5
Figure 10 (a) shows how a is formed to a thickness of about 1000
).

Next, the polycrystalline silicon film 6 deposited to a thickness of, for example, 6000 nm is selectively patterned, and ions are implanted using this polycrystalline silicon film pattern as a mask to form the p-type semiconductor layer 4 that will become the channel region. Form in a self-consistent manner. This situation is shown in FIG. 10(b).

Next, using photo-etching technology, an opening is selectively formed in the area where the n0 type semiconductor layer 8 which will become the source region is to be formed using the photoresist 7, as shown in FIG. 10(C).
Shown below.

Next, the n-type semiconductor W which will become the source region! J8 and oxide film 5b are formed (as shown in FIG. 10(d)), and C
PSG (Dhospho 5ilicat) by VD method
Fig. 10(e) shows the thickness of 111I5c (111I5c) with a thickness of about aooo. In FIG. 9(b), this oxide film 5b and PSG film 5G are combined into a second
It is shown as an insulating film 5d.

Next, after performing various heat treatments, the oxide film 5b and the PSG
By forming an electrode extraction opening 10a in the film 5C and forming an aluminum (AJ2) electrode 9, the source φ
Drain-to-drain breakdown voltage VDss is approximately 200 to 600v (7)
DSA MOS FET is completed.

This situation is shown in FIG. 10(f).

In general, MOS FETs have the advantage of high-speed switching because there is no accumulation of minority carriers, and high thermal stability because the drain current has a negative temperature coefficient, so they can be used as equal-power devices, but bipolar transistors Compared to this, since it is a majority carrier element, there is a significant trade-off between high withstand voltage and high power, and the substrate resistance layer required for high withstand voltage directly leads to an increase in saturation voltage, resulting in a large on-resistance for the same chip area. There was a drawback. In order to solve this problem, it is necessary to reduce the resistance of the power path of the FET, especially the drain resistance. In other words, the question is how to increase the area efficiency of the drain, and for this purpose, it is necessary to design the best pattern by making full use of microfabrication technology. A DSA MOS FET is generally employed as a structure that satisfies these requirements.

However, the pattern design of conventional DSA MOS FETs is not necessarily an optimal design. In order to increase the width of the current path, i.e. the peripheral length of the channel, or shorten the channel length within the limited silicon chip area, various ideas are needed for the polycrystalline silicon film pattern and the shape of the channel region. It is. By increasing the channel width, the drain current can be increased, and the mutual conductance g in the large current region can be increased. You can also get something big.

Since these are the biggest factors that make it possible to reduce on-resistance, the biggest goal was how to increase the channel width within a limited area.

Therefore, when we examine the gate polycrystalline silicon patterns of high-voltage power MO8FETs conventionally used in switching power supplies, we find that most exhibit a square lattice shape as shown in Figure 9(a). There is.

In the plan view of FIG. 9 (a), the length of the gate polycrystalline silicon film from the edge of the open pattern of the polycrystalline silicon film 6 of the cell to the edge of the open pattern of the cell adjacent vertically and horizontally is 11, If the length between cells adjacent in the diagonal direction is 12, J22 is f2 times longer than l.
In order to integrate a large number of gate polycrystalline silicon films 6, it is desirable that the above length fl+ and J12 be equal. That is, since the channel region 4 exists along the pattern edge of the gate polycrystalline silicon 1116, it is desirable to set it to jl+-J22 in order to obtain a large channel width.
22>β1. In this case, the polycrystalline silicon film 6 occupies an extra area corresponding to 2-4. This also causes the gate area to be widened and the capacitance between the drain and the gate to be increased, which impedes the switching speed.

In addition, it is well known that each pattern is generally miniaturized to increase the channel width, and as a result, the gate polycrystalline silicon film pattern and source region are reduced, and the channel width increases accordingly. I can figure it out. However, conventional rectangular, lattice-shaped gate polycrystalline silicon patterns tend to have too many source electrode openings relative to the drain current capacity. Although miniaturization allows the formation of a large number of independent channel regions, which results in an overall increase in channel width, the channel width within one cell becomes smaller. In other words, when operating as a MOS transistor under the same conditions, even though the smaller the channel width, the smaller the current capacity, there are many electrode extraction openings in the source region formed in the cell. It turns out.

As is well known, a MOS FET has less thermal runaway than a bipolar transistor, and the current density obtained from one cell area is small, so there is no need for an unnecessary opening for the source electrode.

It is necessary to use this unnecessary portion to form more channel regions and to arrange patterns to increase the channel width. Therefore, it is important to devise a pattern to reduce the area of the source electrode extraction opening and effectively increase the channel width accordingly.

In terms of performance, especially with regard to improving switching speed, it is important to reduce the capacitance between the gate and drain. Typical methods for achieving this are increasing the thickness of the gate oxide film and reducing the area occupied by the gate polycrystalline silicon film pattern. However, the threshold voltage ★★h, which is one of the MO8 operating characteristics, and the mutual conductance 9m
For these reasons, there is a limit to increasing the thickness of the gate oxide film. Therefore, another typical method is to reduce the area occupied by the gate polycrystalline silicon film pattern on the gate oxide film. The easiest way to implement this method is to make the gate polycrystalline silicon film pattern thin. However, making it thinner has the drawback of increasing resistance and slowing down switching speed.

Most conventional gate electrode materials include polycrystalline silicon films and films of high melting point metals such as molybdenum group metals, and these materials are used as multilayer wiring material films because they are resistant to high-temperature processes.

For this reason, in high-power O8A MOS FETs, a polycrystalline silicon film is used as a typical gate electrode material, and two layers are connected to the source electrode An film via an insulating film.
It has a layered electrode structure. Moreover, in order to increase the channel width, the gate polycrystalline silicon film pattern is designed to be thin and extremely long. Within a limited silicon chip, the relationship between the length of the channel width and the wiring resistance of the gate polycrystalline silicon film pattern is that if the channel width is designed to be long in order to lower the on-resistance, the gate resistance will increase and the switching speed will increase. The disadvantage was that it was slow. For this reason, in the past, the channel region within the chip was sacrificed to create several highly conductive Ag stripe patterns, and this was connected to the gate polycrystalline silicon film in an effort to reduce gate resistance. . However, since the gate is a polycrystalline silicon gate with a length of several hundred to several thousand microns between the eight β electrodes, the gate resistance is still high.

On the other hand, as another method of lowering the gate resistance, see Figure 11 (
As shown in a) and (b), there is a comb-shaped electrode structure in which a gate/l pattern and a source Ai pattern are alternately arranged on a gate polycrystalline silicon film with an insulating film interposed therebetween.

In FIG. 11, the same parts as those shown in FIG. 9 are designated by the same reference numerals. This semiconductor device having a comb-shaped electrode structure has an n-type epitaxial layer M2 grown on an n-type semiconductor substrate 1, and has openings in a lattice pattern on its main surface through a first insulating film 5a. A polycrystalline silicon film 16 is patterned, and a p-type first semiconductor layer 2 is formed within the opening of this polycrystalline silicon film 6.

A portion of the main surface of the epitaxial layer 2 is covered with a first insulator 115.
A p-type second layer is formed so as to overlap the polycrystalline silicon film through a.
A semiconductor layer 4 is formed, and in this second semiconductor layer, an n-type third semiconductor layer 8 is formed so as to partially overlap with the polycrystalline silicon film 6 via the first insulating layer 115a, and is made of polycrystalline silicon! A second insulator 115d is formed to cover 16 and its opening. Striped source and gate electrodes 9a and 9 are provided on this second insulating crotch.
b is formed, and the source/l electrode 9a is ohmically connected to the first and third semiconductor layers 3 and 8 through the opening 10a made in the second insulating film 5d and the opening made in the polycrystalline silicon film 6. The gate AJ electrode 9b is connected to the polycrystalline silicon 116 through the opening 10b formed in the second insulating film 5d.
It is connected to the.

(Problems to be Solved by the Invention) The semiconductor device having the conventional comb-shaped electrode structure shown in FIG.
The source/l electrode 9a and the gate AJ2 electrode 9b must be separated by a certain distance in consideration of pattern recession due to isotropic etching of the film thickness of the n electrodes 9a and 9b. Therefore, unless the pattern width of the gate polycrystalline silicon film 6 is increased or the cell area is increased, it will be extremely difficult to separate the source A-b electrode 9a and the gate-b3 electrode 9b due to photolithography. In particular, the gate-source capacitance increases,
This in turn was a factor that hindered the improvement of switching speed. On the other hand, the simplest way to lower the gate resistance is to increase the thickness of the gate polycrystalline silicon film 6, which has a slight effect.
There is a drawback that the electrode 9b is easily cut off at the edge of the opening formed in the polycrystalline silicon film 6.

Another factor for improving switching speed is to narrow the channel length. This channel length is determined by the difference in diffusion depth between the p-type semiconductor layer 4 in the channel region and the source n-medium semiconductor layer 8.

However, when considering switching speed, the following conditions must be met. In general, drain current flows from the source n-medium semiconductor layer 8 through the p-type semiconductor layer 4 in the channel region, from the n-type epitaxial layer 2 in the vertical direction to the drain region of the n-medium semiconductor substrate 1, and flows through the drain electrode on the back surface of the substrate. taken from. Therefore, the drain current flows between the p-type semiconductor layers 4 forming the channel region. Therefore, since the p-type semiconductor layers 4 are formed on both sides of the gate polycrystalline silicon film 6 so as to face each other, if the p-type semiconductor layer is formed deeply, the flow path for the drain current becomes narrower, and the current path becomes narrower. It has a resistance valve, which in turn causes an increase in on-resistance. In addition, the p-type semiconductor layer 4 forming the channel region
By forming the gate polycrystalline silicon film deeply, firstly, the area overlapping with the gate polycrystalline silicon film 6 increases. As is well known, the gate insulating film 5a has conventionally been formed extremely thin with a thickness of 500 to 1,200.
It is clear that the source-to-source capacitance increases and hinders the switching speed. Therefore, the p-type semiconductor layer 4 forming the channel region is formed as shallowly as possible,
Along with this, the channel length is shortened by forming the source n medium semiconductor layer 8 shallowly, and the mutual conductance g. It becomes possible to realize a DSA MOS FET with a large resistance, a low on-resistance, and a high switching speed.

However, by forming the p-type semiconductor layer 4 forming the channel region shallowly and narrowing the channel length, the following new problem arises.

First, during MO8 operation, a depletion layer spreads from the p-type semiconductor layer 4 forming the channel region to the n-type epitaxial layer 2 side of the drain region. At the same time, a depletion layer also spreads within the p-type semiconductor layer 4.

This depletion layer spreads more easily as the concentration of the semiconductor layer or the diffusion layer becomes lower, and as the drain voltage becomes higher. Therefore, as a matter of course, a large amount of the depletion layer spreads toward the n-type epitaxial layer 2 side of the drain region where the concentration is low. However, in the case of an MO8 type FET having a DSA structure, since the channel regions 4 are formed to face each other in the cell portion, the depletion layers of both regions are spread close to each other, and the channel regions 4 are formed to face each other in the cell portion, so that the depletion layers of both regions are spread close to each other, and the channel regions 4 are formed to face each other in the cell portion. Since they collide in the nearby drain region, there is no obstacle to obtaining a large source-drain breakdown voltage. On the other hand, on the p-type semiconductor layer 4 side, by increasing the drain voltage higher and higher, the depletion layer in the p-type semiconductor layer 4 forming the channel region expands and reaches the source n-type semiconductor layer 8. Put it away. This is the so-called bunch-through phenomenon. At this point, the voltage between the source and drain has already broken down. In other words, since the channel length is narrow, the depletion layer quickly reaches the n medium semiconductor layer 8, resulting in breakdown at a value smaller than the breakdown voltage determined by the bulk characteristics. In particular, in order to obtain a long channel width, the gate polycrystalline silicon film pattern must be miniaturized, and accordingly, the p-type semiconductor layer 4 constituting the channel must be formed by shallow diffusion. Naturally, thin and long patterns are formed between the gate polycrystalline silicon film patterns, so punch-through phenomenon is likely to occur in such portions.

In addition, as a way to make the punch-through phenomenon less likely to occur,
In a conventional DSA MOS FET, a p-type semiconductor layer 3 is formed within the cell by photoetching technology. However, this method has the following drawbacks. First, with photolithography technology,
In order to form the pattern of the gate polycrystalline silicon film 6 by aligning the p-type semiconductor layer 3 with respect to the p-type semiconductor layer 3, the p-type semiconductor in the channel region is formed in a self-aligned manner by the pattern of the gate polycrystalline silicon film 6. The positional relationship between the layer 4 and the p+ type ring conductor layer 3, which is not formed in a self-aligned manner, becomes inaccurate, and the long and short portions of the p type semiconductor layer (channel region) 4 narrowed by the n medium semiconductor layer 8 are It is formed under the n+ type semiconductor layer 8 . In this case, bunch-through tends to occur in the long narrow p-type semiconductor layer 4, and conversely, in the short part, a part of the high concentration p-type semiconductor layer 3 reaches the channel p-type semiconductor layer 4, and the M
This is a characteristic of O8 type transistors that affects the threshold voltage value. Furthermore, when performing the alignment, it is necessary to form a pattern taking into account alignment errors, resulting in an increase in cell area and a corresponding decrease in channel width.

Furthermore, since the p-type semiconductor layer 3 is formed by alignment using photolithography, the number of photo-etching steps is increased, which in turn impedes productivity improvement.

Furthermore, in order to improve the area utilization efficiency of the chip and obtain a long channel width, the opening pattern of the gate polycrystalline silicon film is connected to two or more enlarged portions with a large area and a narrow connection connecting the adjacent enlarged portions. The present inventor proposes a structure having a section. In such a semiconductor device, since an elongated channel region is formed along the edge of the connecting portion, the channel width can be increased, but there is a drawback that bunch-through is particularly likely to occur in this elongated channel region.

The present invention has been made in view of the above-mentioned points, and even if the width of the gate polycrystalline silicon pattern is made as equal as possible, and the overall pattern is made finer, the source electrode extraction opening can be optimized according to the current capacity. so that you can get
Roughly speaking, the p flat type semiconductor layer 3 and the n medium type semiconductor layer 8 are formed in a self-aligned manner especially at the source electrode extraction opening.
are electrically connected by the metal electrode film 9,
The purpose is to miniaturize the barrier gate, and to achieve this purpose, it is possible to arrange an appropriate pattern, and to effectively form a channel region in the extra area obtained by these effects, especially in a long and narrow channel region. It prevents the punch-through phenomenon, allows narrowing the channel length, reduces the photo-etching process, lowers the on-resistance, and reduces the transconductance. The present invention provides a vertical semiconductor device and a method for manufacturing the same, which improve element performance such as switching speed, reduce chip area, and improve productivity.

(Means for Solving the Problems) A vertical semiconductor device according to the present invention includes a semiconductor substrate of one conductivity type having a groove on its main surface, and a first insulating film placed over the groove on the main surface of the semiconductor substrate. a semiconductor film or a conductive film pattern formed using a semiconductor film or a conductive film pattern, and a position where a part of the semiconductor film or a conductive film pattern partially overlaps with the main surface of the semiconductor substrate via the first insulating film in the opening of this pattern. a first semiconductor layer of an opposite conductivity type with a low impurity concentration and whose edges are regulated by the side surfaces of the groove, and a portion of a semiconductor film or a conductive film pattern within this first semiconductor layer. a second semiconductor layer of one conductivity type formed to overlap with each other and having an edge regulated by the side surface of the groove; and a second insulating film formed to cover the semiconductor film or the conductor film and having an opening. and a metal electrode film formed on the second insulating film to include the opening.

Furthermore, the manufacturing method of the present invention includes the steps of: forming a groove on the main surface of a semiconductor substrate of one conductivity type by anisotropic etching; forming a first insulating film on the main surface of the semiconductor substrate; and the groove. A process of forming a semiconductor film or a conductive film pattern on the first insulating film located above, and implanting ions of the opposite conductivity type at a low concentration using the semiconductor film or conductive film pattern as a mask to form an edge. forming a first semiconductor layer of an opposite conductivity type in which is regulated by the side surfaces of the groove; and implanting ions of one conductivity type into the first semiconductor layer using the semiconductor film or conductor film pattern as a mask. a step of forming a second semiconductor layer of one conductivity type whose edge is regulated by the side surface of the groove; a step of forming a second insulating film so as to cover the semiconductor film or conductor film and its opening; selectively forming an opening in a second insulating film to partially expose the first and second semiconductor chips; and forming a metal electrode film on the second insulating film to cover the opening. It is characterized by having the following.

(Function) In the semiconductor device of the present invention, since the third semiconductor layer of the opposite conductivity type has a higher impurity concentration and is formed deeper than the second semiconductor layer, miniaturization and high integration of cells are possible. At the same time, the bunch-through phenomenon can also be effectively prevented. Furthermore, by forming the second semiconductor layer and the fourth semiconductor layer shallowly, it is possible to reduce the capacitance between the gate and the source, and also to increase the mutual conductance □, thereby improving the switching speed. . Furthermore, in the semiconductor device of the present invention, the channel width can be increased within a predetermined chip area, and the gate-drain capacitance can be reduced by reducing the area occupied by the polycrystalline silicon film. can.

Therefore, a large drain current can be obtained and at the same time a fast switching speed can be obtained.

In particular, as in the embodiment described later, the opening of the polycrystalline silicon film pattern is connected to an annular portion surrounding the independent pattern portion, an end portion located symmetrically on both sides of this annular portion, and an end portion between the annular portion and the end portion. By arranging a plurality of such openings so that the end portions of adjacent openings are arranged in an interdigital manner, the utilization efficiency of the chip area can be improved. The above-mentioned effects will be exhibited even more effectively.

(Example) The present invention will be specifically explained below using examples.

FIGS. 1(a) and (b) are a plan view and a cross-sectional view of an O8A MOS FET, which is an embodiment of the present invention. It is.

In this device, an n-type epitaxial growth layer 2 is provided on an n-medium sized semiconductor substrate 1, a substantially U-shaped groove is formed on the main surface of this epitaxial layer 2, and an insulating oxide film (a first insulating layer) is formed on the surface of this groove. A polycrystalline silicon film (semiconductor film or conductor pattern 6) is provided through the film) 5a, and in the epitaxial layer 2 within the opening of this pattern is a p-type semiconductor doped with impurities of the opposite conductivity type at a high concentration. A layer 3 is provided. Further, in the epitaxial layer 2, an impurity of the opposite conductivity type is added at a low concentration at a position partially overlapping with a part of the polycrystalline silicon film pattern 6 via the first insulating layer 1I5a. A doped p-type semiconductor layer (first semiconductor layer) 4 is deeply provided, and the surface of the first semiconductor layer 4 is
An n+ type semiconductor layer (second semiconductor layer) 8 is formed at a position partially overlapping with a part of the conductive film pattern 6 via the insulating film 5a.
is formed, an insulating oxide film (second insulating film) 5d is formed to cover the polycrystalline silicon film pattern 6, and a source AJ electrode film 9 is formed on this insulating film.

The source eight β electrode film 9 passes through the source electrode extraction opening 10a in the cell formed in the insulator 1115d, and the semiconductor
l! Ohmic connected to I4 and 8.

A p-type semiconductor 114 surrounded by a polycrystalline silicon film pattern 6 and formed on the surface of the n-type epitaxial layer 2
The planar shape of the open pattern of the polycrystalline silicon film 6 is a hexagonal enlarged portion 4A, 4B as shown in FIG. 1(a).

4G and narrow connecting portions 4D and 4E connecting adjacent sides of these three hexagonal patterns. Here, the distance between each side of the edge 6A of the polycrystalline silicon film 6 of horizontally and vertically adjacent cells, and the distance between each side of the diagonally adjacent cell 2, → It has become 2. Further, the cells are arranged such that the central hexagonal enlarged portion 4B of the vertically adjacent cell is located between the hexagonal enlarged portions 4A and 40 located at opposite ends of the horizontally adjacent cells. Only Ibitchi is placed in a different position.

In order to improve the performance of the vertical field effect transistor of this example, the gate polycrystalline silicon film pattern is modified, the channel width is lengthened, and the current capacity per unit area is increased. . This will be explained by comparing the dimensional relationship with a conventional device.

The same design rule is adopted for the magnification of the conventional example of the plan view in Fig. 9 (a) and the plan view in Fig. 1 (a),
The vertical length YL within the specified area surrounded by the broken line is 120 μ■
Bind and set the horizontal length xL as 160 μl.

In FIG. 9(a), there are 3×4−12 source electrode extraction openings 10a, and the length of one side of one cell is Lo.
+ (=Lo 2 ) is 20μ-, so the channel width of one cell (total perimeter of one cell) is 80μ
-, and the total channel width within this broken line frame is 960μ
He is humble.

In contrast, in FIG. 1(a), the hexagonal ends 4A, 4B
, the length LO3 of the straight side of 4G is 10. czi+.

45° inclined side LO4 (-J2/2Lo 3)
The length of the cell is approximately 7 μm, and the length LOs of one side of the connecting portions 4D and 4E is 20 μm, so the channel width of one cell is approximately 244 μm, and the pattern area within the broken line is The total channel width is approximately 1132 μm. As described above, the channel width of this embodiment is larger than that of the conventional one, and the difference becomes larger as the number of cells increases or as the pattern area becomes larger.

In this way, according to this embodiment, the channel width can be significantly increased. The reason for this is that by effectively using diagonal lines, β in the plan view of Fig. 9(a),
This is because the relationship is set to A + 'p J 2 in FIG. 1(a). Therefore, by arranging the cells so that they are alternately shifted by a pitch, it is possible to integrate the cell pattern arrangement in the center as a whole, despite the same design rule, and the number of cell patterns can be increased by that much more than in the conventional method. cells can be integrated.

Next, when miniaturization progresses, particularly when cell and gate polycrystalline silicon film patterns are downsized, conventional semiconductor devices require source electrode extraction openings at intervals of several microns. In other words, the source electrode extraction opening has the drawback of being constrained by design rules. On the other hand, this embodiment has the advantage that the interval between the source electrode extraction openings can be arbitrarily designed, and the channel width does not decrease.

From the above, in this example, an appropriate gate polycrystalline silicon film pattern is obtained so that the channel width can be increased within a defined chip area, and the cells corresponding to the openings of this gate polycrystalline silicon film pattern are By appropriately arranging g, it is possible to obtain a large drain current, and the mutual conductance g in the large current region.

The optimum pattern is applied to increase the switching speed, reduce the on-resistance, reduce the chip area, and improve productivity.

In the present invention, the edges 4a and 8a of the p-type semiconductor layer 4 forming the channel region formed in the opening of the cell pattern and the n-medium semiconductor layer 8 forming the source region formed inside the epitaxial layer 12 are Since it is regulated by the side walls of the substantially U-shaped groove formed on the surface, even if the p-type semiconductor layer 4 is formed deeply, the channel length determined by the distance between these edges 4a and 8a can be shortened. Since the channel length is shortened in this way, the mutual conductance 9rn becomes large, the on-resistance becomes low, a fast switching speed is obtained, and the p-type semiconductor layer 4 can be formed deeply, which prevents the bunch-through phenomenon. be able to.

In addition, the p-type semiconductor layer 4 serving as a channel region and the source n-type semiconductor layer 8 have a shallow junction (Shallow Jun).
Since the drain current flow path (n-type epitaxial layer 2) between the channel regions is widened, the gate polycrystalline silicon film pattern width can be reduced accordingly.

Therefore, in order to particularly form a long channel width, it is preferable to make the openings (cells) of the gate polycrystalline silicon film pattern narrow and form a long and narrow channel region as a long pattern arrangement. The bunch-through phenomenon can also be effectively prevented.

FIGS. 2(a), (b), and (C) are a plan view and a perspective cross-sectional view of an O8A MOS FET which is still another embodiment of the present invention, and FIG. 2(a) shows an AJ electrode film. In FIG. 2(C), the AJ2 electrode film and the second insulating film are cut out.

In this device, an n-type epitaxial growth layer 2 is provided on an n-type semiconductor substrate 1, a substantially U-shaped groove is formed on the main surface of this epitaxial layer 112, and an insulating oxide film 5a is formed on the surface of this groove. A polycrystalline silicon film pattern 6 is provided, and within the epitaxial layer 2 within the opening of this pattern is a p-type medium semiconductor layer 3 doped with impurities of opposite conductivity type at a high concentration.
is provided. Also, polycrystalline silicon training pattern 6
A p-type semiconductor layer (first semiconductor layer) 4 of an opposite conductivity type is provided in the opening at a position partially overlapping with a part of the polycrystalline silicon film pattern 6 via the first insulator 115a. An n-medium semiconductor layer (second semiconductor layer) is formed on the surface of the p-type semiconductor layer 4 at a position that partially overlaps with a part of the semiconductor layer or conductor film pattern 6 via the first insulating film 5a. An insulating oxide layer 11 (second insulating film) 5 is formed to cover the polycrystalline silicon film pattern 6.
A first source AJ electrode film 9a and a second gate AJ electrode film 9b are formed in a stripe shape on this insulating film. The source Aβ electrode 1119a is connected to the source electrode extraction opening 10 in the cell formed in the insulating film 5d.
The second Aβ electrode 9b is ohmically connected to the p flat type and n0 type semiconductor layers 3 and 8 through the insulating film 5d. It is connected to the crystalline silicon film pattern 6.

The polycrystalline silicon film pattern 6 has a continuous lattice-like portion 6
a and an independent island-like portion 6b, and the planar shape of the cell defined by these portions is the independent portion 6b.
An annular portion 12A surrounding the annular portion, two end portions 12B and 12G formed symmetrically with respect to the annular portion, and connecting portions 12D and 1 that connect the annular portion and these end portions.
It is composed of 2E. End portions 12B and 12G
The contour shape of the annular portion 12A is a polygon that is an integer multiple of 2, in this example a quadrilateral, and the contour shape of the annular portion 12A is also a polygon that is an integer multiple of 2, which is a quadrangle in this example. The shapes of these end portions and the annular portion are not limited to quadrangles, but may be octagonal or circular, for example.

In this example, as shown in FIG. 5(a''), the annular portion 1
An annular portion 12A of a column formed by arranging a plurality of cells so that cells 2A are aligned and an annular portion 12A of an adjacent column.
and the sequential end portions 12B of the rows that are shifted in pitch from each other.
and 1λC, the sequential end portions 12C and 12B of adjacent columns are arranged interdigitally. In this case, when focusing on the end portion 12B, the distances to the adjacent end portion 12G, connecting portion 12E, and annular portion 12A are all approximately equal.

The second AJ2 electrode 11!9b constituting the ρ electrode to the gate is connected to the island-shaped independent portion 6b of the polycrystalline silicon pattern through the gate electrode extraction opening 10b formed in the insulating film 5d, and is connected to the adjacent independent portion. It is connected to the continuous portion 6a of the polycrystalline silicon film pattern through an opening 10c formed in the second insulating film 5d at an intermediate position. That is, the continuous portion 6a of the polycrystalline silicon film pattern
and the independent portion 6b are interconnected via the second A.degree. C. electrode film 9b. In this way, in this example, the 18th λ electrode film 9
a and the second Δp electrode film 9b are alternately arranged in stripes at intervals of ten to twenty microns, and the width of the eighteenth λ electrode g19a constituting the source Aλ electrode is equal to that of the gate A°C electrode. It is wider than the constituent second/l electrode film 9b.

As described above, in this embodiment, the polycrystalline silicon film pattern 6 is configured with a mesh-like continuous portion 6a and an island-like independent portion 6b, so that the channel width is made longer than in the above-mentioned embodiment. be able to. That is, the gate electrode structure has a continuous mesh-like part and a plurality of independent parts surrounded by the mesh-like part, and these parts are covered with the second AJ2 electrode film 9 having excellent conductivity.
The configuration is such that they are connected at b. On the other hand, the source electrode structure includes, at the end portions 12B and 12G inside the cell, a p-type semiconductor layer 3 that is electrically in contact with an n-type semiconductor layer 4 that constitutes a channel region, and an n-medium semiconductor layer that constitutes a source region. The layer 8 is exposed at the surface and connected to the first/l electrode film 9a.

These first and second AJ2 electrode films 9a and 9b are alternately arranged in a comb shape. In this way, the gate polycrystalline silicon pattern has a continuous mesh structure,
The greatest feature of this embodiment is that the source electrode and the gate electrode are made of a metal film such as AJ2 having excellent conductivity in a comb shape by forming an independent multi-structure.

Also in this example, the edges 4a and 8a of the n-type semiconductor layer 4 and the n-medium semiconductor layer 8 are regulated by the side surfaces of the groove in which the gate polycrystalline silicon film 6 is formed, so that the channel length can be shortened. Moreover, since the n-type semiconductor layer 4 can be formed deeply, punch-through can be effectively prevented.

Next, a manufacturing method of the present invention for manufacturing an O8A MOSFET, which is an embodiment of the semiconductor device of the present invention, will be described with reference to FIGS. 3(a) to 3(d).

First, an n-type semiconductor substrate 1 containing a high concentration of n-type impurities
A 0-type semiconductor layer 2 having a lower concentration is formed thereon, and a 0-type oxide film 5e having a thickness of, for example, about 3,000 layers is formed on the main surface of this n-type semiconductor layer, as shown in FIG. 3(a). Next, using this oxide film 5e as a mask, the n-type semiconductor layer 2 is anisotropically etched to a depth of about 1.0 μm using, for example, an alkaline etchant mainly containing hydrazine or KOH to form a groove. After removing the oxide layer 115e, a new gate oxide film 5a is formed to a thickness of about 1000 mm.Next, a non-doped polycrystalline silicon film 6 for the gate electrode is formed to a thickness of about 6000 mm, for example, and a photoresist is formed. Figure 3 shows how the polycrystalline silicon film formed on the grooves was selectively patterned using photoetching technology, leaving only the polycrystalline silicon film formed on the grooves and removing the rough edges.
Shown in b).

Subsequently, after removing the photoresist with oxygen plasma, an n-type semiconductor layer 4 constituting a channel region is formed using the polycrystalline silicon film 6 as a mask, and an n-type semiconductor layer 8 constituting a source region is selectively removed. Figure 3 shows how it is formed (
Shown in C). In this case, the edges 4a and 8a of the n-type semiconductor layer 4 and the n-medium semiconductor layer 8 are regulated by the side surfaces of the U-shaped groove formed on the surface of the n-type semiconductor layer 2, so the n-type semiconductor layer Even if the layer 4 is formed deep, the channel length determined by the distance between the edges 4a and 8a can be shortened.

Thereafter, approximately 1,000 layers of -TCVD-3i 02 m or PSG film 5C are formed using the CVD method, and then heat treatment is performed to form electrode extraction openings 10a and 10b in each region.
After forming A, 1 with a thickness of about 3.5 μm, for example,
FIG. 3(d) shows a completed semiconductor device by selectively forming two metal films 9a and 9b.

In this embodiment, the p medium type semiconductor layer 3 shown in FIGS. 1 and 2 is not formed, but this p+ type semiconductor layer can also be formed. In this case, the p medium semiconductor layer 3 is
It may be formed before forming the grooves.

FIG. 4 shows still another embodiment according to the present invention.
FIG. 4(a) is a plan view, and FIG. 4(b) is a sectional view taken along the line A-A. FIG. 4(a) shows the A1 electrode film completely removed. In order to keep the gate polycrystalline silicon film pattern width constant, the channel width is made longer by using diagonal lines in the cell shape and integrating many cells. Therefore, this structure has the longest channel width in terms of pattern area per unit area. In this embodiment, the same parts as in the previous example are denoted by the same reference numerals. In this example, the planar shape of the cell surrounded by the continuous portion 6a of the polycrystalline silicon film pattern is approximately an octagonal annular portion 12A.
As shown in FIG. 2, it consists of substantially octagonal end portions 128, 120 arranged symmetrically on both sides, and narrow connecting portions 12D, 12E that connect the annular portion with these end portions. This embodiment is only different from the embodiment described above, and the other configurations are the same, so no further explanation will be given.

5 to 7 show the planar shape of a pattern of an n-type semiconductor layer 4 surrounded by a polycrystalline silicon film pattern 6 in still another embodiment of the semiconductor device of the present invention. Fifth
In the embodiment shown in the figure, the hexagonal end portions 4F and 4G are connected by a narrow connecting portion 4H, and the hexagonal end portions 4F and 4G are arranged so as to be shifted by one inch. Further, in the embodiment shown in FIG. 6, the hexagonal end portions 4 and 4J are connected by a narrow connecting portion 4, and the hexagonal end portions 4 and 4 J are arranged at different pitches. Furthermore, in the embodiment shown in FIG.
L and 4M are connected by a narrow connecting portion 4N, which are arranged at different pitches. These, 5th~
In the embodiment shown in FIG. 7 as well, the edges of the n-type semiconductor layer 4 and the n-medium semiconductor layer 8 formed in a self-aligned manner are regulated by the side surfaces of the groove, so the n-type semiconductor layer 4 is formed deeply. It is also possible to shorten the channel length and prevent the punch-through phenomenon.

The present invention is not limited to the embodiments described above, but can be modified and modified in many ways.

For example, in the above embodiment, the n-type semiconductor layer was anisotropically etched with KOH, which is an alkali etchant, to form a substantially U-shaped groove, but the present invention is limited to such a U-shaped groove. For example, V
It may also be a letter-shaped groove. Alternatively, trenches with vertical sidewalls can be formed by reactive ion etching with carbon tetrachloride and oxygen gas, as shown in FIG. The configuration of other parts of the embodiment shown in FIG. 8 is the same as that shown in FIG. 3(d), and the same parts are designated by the same reference numerals. Also in the embodiment shown in FIG. 8, the edges 4a and 8a of the n-type semiconductor layer 4 and the n-medium semiconductor layer 8 are regulated by the side surfaces of the groove, so even if the n-type semiconductor layer 4 is formed deep, the channel length is becomes shorter. Furthermore, since the p-type semiconductor WJ4 is formed deeply, punch-through phenomenon can be effectively prevented.

Furthermore, in the embodiment shown in FIG. 3, the p medium semiconductor layer 3 (FIG. 1) can be formed by doping impurities at a high concentration before or after forming the grooves.

Further, in the above-described embodiment, the gate electrode material was polycrystalline silicon, but it is not limited to this, and MO, Ni
, Ti, Cr, or a high melting point metal such as molybdenum silicide, nickel silicide, platinum silicide, etc., may be used. Further, the conductivity types of the n-type semiconductor layer and the n-type semiconductor layer may be opposite. Furthermore, in the above example, among the vertical field effect transistors, especially the DSA MO8
However, the invention is not limited to this, and the gate polycrystalline silicon film pattern may be used as the emitter and the cell pattern as the base, or vice versa. It can also be applied to bipolar semiconductor devices.

Further, in the embodiments described above, a power transistor is used, but a high frequency transistor or a power switching transistor may also be used. In particular, in high voltage transistors, field limiting rings can be formed according to the present invention, so in addition to DSA-FETs, 5I
It is also applicable to T (static induction transistor).

(Effects of the Invention) As described above, according to the present invention, a groove is formed in a semiconductor substrate, and the edges of the first and second semiconductor layers are regulated by the side surfaces of the groove. Even if it is formed deeply, it does not spread laterally, making it possible to shorten the channel length and prevent the punch-through phenomenon.

Since the channel length can be shortened in this way, the mutual fundductance g. This in turn makes it possible to improve the switching speed, and it is possible to provide a high-power MO8 type transistor that is a high breakdown voltage element, has a high switching speed, and has a low on-resistance using a highly productive manufacturing method.

Furthermore, if the polycrystalline silicon film pattern is configured as described above, the channel width can be increased, and an optimum source electrode extraction opening corresponding to the current capacity can be obtained.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are a plan view and a sectional view showing the structure of an embodiment of a vertical semiconductor device according to the present invention, and FIGS. A plan view sectional view and a perspective sectional view showing the structure of another embodiment of the vertical semiconductor device, and FIGS. 4(a) and 4(b) are plan views and sectional views showing the structure of still other embodiments, and FIGS. 5 to 7
The figure is a plan view showing a modified example of the cell pattern, FIG. 8 is a sectional view showing the configuration of still another embodiment of the vertical semiconductor device according to the present invention, and FIGS. 9 (a) and (b) are the conventional vertical electric field. A plan view and a cross-sectional view showing the structure of an effect transistor, FIG.
11(a) to 11(f) are sectional views showing the structure in the same sequential manufacturing process, and FIGS. 11(a) and 11(b) are a plan view and a sectional view showing the structure of another example of the conventional vertical field effect transistor. It is. 1...n-type semiconductor substrate 2...n-type epitaxial layer 3...p-type semiconductor layer 4...p-type semiconductor layer (first semiconductor layer) 5a...first
Insulating film 5d...Second insulating film 6...Polycrystalline silicon film 6a...Continuous portion 6b...Independent portion 4a, 88.6A-...Edge 8...n-type semiconductor 11 ( second semiconductor layer) 9a...
1st AJ211 electrode film 9b... 2nd AJ211 electrode film 1
0a, 10b, 10C...opening 12A...
・Annular part 128.120...end part 120
, 12E...Connection parts 4A to 4G, 4F, 4G, 4I, 4
J, 4L. 4M...Enlarged parts 4D, 4E, 4H, 4, 4N...Connection part Fig. 2 (C) Fig. 1O (a) Fig. 1O (d) (e) Procedural amendment (method) 1988 November 12, 1985 Patent Application No. 154241 2 Name of the invention Vertical semiconductor device and its manufacturing method 3 Person making the amendment Relationship with the case Patent applicant TDC Co., Ltd.

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type having a groove on its main surface, and a semiconductor film or conductor film pattern formed over the groove on the main surface of this semiconductor substrate with a first insulating film interposed therebetween. In the opening of this pattern, a pattern is formed on the main surface of the semiconductor substrate at a position where it partially overlaps with a part of the semiconductor film or the conductor film pattern via the first insulating film, and the edge thereof is formed in the groove. A first semiconductor layer of the opposite conductivity type with a low impurity concentration regulated by the side surface is formed in this first semiconductor layer so as to partially overlap with a part of the semiconductor film or conductor film pattern, and the edge is a second semiconductor layer of one conductivity type regulated by the side surfaces of the groove; a second insulating film formed to cover the semiconductor film or the conductive film and having an opening; on the second insulating film; A vertical semiconductor device comprising a metal electrode film formed to include the opening. 2. The planar shape of the first semiconductor layer surrounded by the semiconductor film or conductor film pattern is made into a polygonal or circular enlarged portion that is an integral multiple of 2, and a narrow width that connects adjacent enlarged portions. 2. The vertical semiconductor device according to claim 1, further comprising a connecting portion. 3. The vertical semiconductor device according to claim 2, wherein the expanded portion of the first semiconductor layer has an octagonal shape, and opposing sides of two or more adjacent expanded portions are connected by a connecting portion. 4. The semiconductor film or conductor film pattern has a mutually continuous pattern portion and an independent pattern portion located within the pattern opening, and these continuous pattern portions and independent pattern portions are connected via the metal electrode film. Claim 1, 2 or 3 characterized in that the invention is interconnected with each other.
The vertical semiconductor device described above. 5. forming a groove on the main surface of a semiconductor substrate of one conductivity type by anisotropic etching; forming a first insulating film on the main surface of the semiconductor substrate; 1. Forming a semiconductor film or conductive film pattern on the insulating film, and using this semiconductor film or conductive film pattern as a mask, ions of the opposite conductivity type are implanted at a low concentration so that the edges are formed by the side surfaces of the trench. a step of forming a first semiconductor layer of a regulated opposite conductivity type, and implanting ions of one conductivity type into the first semiconductor layer using the semiconductor film or conductor film pattern as a mask so that an edge of the trench is formed in the first semiconductor layer; a step of forming a second semiconductor layer of one conductivity type regulated by the side surface; a step of forming a second insulating film to cover the semiconductor film or conductor film and its opening; forming an opening to partially expose the first and second semiconductor layers; and forming a metal electrode film on the second insulating film to cover the opening. A method for manufacturing a vertical semiconductor device characterized by: