JPS61168263A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce an ON resistance by substantially equalizing the widths of gate polycrystalline silicon patterns at any portion, and forming a pattern to obtain the optimum source electrode leading hole according to the current capacity. CONSTITUTION:An N-type epitaxially grown layer 2 is formed on an N-type semiconductor substrate 1, and a polycrystalline silicon pattern 6 is formed through the first insulating film 5a on the main surface of the layer 2. A P-type semiconductor layer 4 is formed, and an N<+> type semiconductor layer (third semiconductor layer) 8 is formed on the surface of the layer 4. The second insulating film 5d is formed to coat the pattern 6, a hole 11 of the insulating film 5d is formed, and an aluminum electrode film 9 is formed on the film 5d. The plane shape of the layer 4 is continuously formed of octagonal semiconductor patterns 4A, 4B, 4C, and coupling semiconductor layer patterns 4D, 4E formed thinly by connecting the patterns.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and mainly relates to an MIS type semiconductor device for the purpose of switching or amplification.

[Technical background of the invention and its problems] Conventional MOSFETs, especially among MIS semiconductor devices, were considered to be low voltage and low power devices, but with the recent development of semiconductor manufacturing technology or circuit design technology, It has become possible to design high-voltage and high-power devices, and has now secured its place as a power device.

Typical examples of such high-voltage power MO8FETs include: (1) offset gate structure; (2) V-Q r.

ove or U-G root structure, ■DSA (
Diffusion Self-Alignme
Among them, the conventional DSA structure power MO8FET (
Figure 5 (hereinafter referred to as DSA MOS) shows a plan view after electrode formation and a cross-sectional structure diagram taken along line A-A' in this plan view.
The manufacturing process will be explained with reference to FIGS. 6(a) to 6(f).

DSA MOS forms a channel by double diffusion, and the impurity diffusion (n-type semiconductor layer 4) for forming the channel region and the diffusion for forming the source region are performed by the same diffusion window surrounded by the gate polycrystalline silicon electrode 6 in the form of a lattice. The feature is that impurity diffusion (n-type semiconductor layer 8) is performed. Since the channel width is determined by the difference in diffusion depth between the n-type semiconductor layer 4 and the n-type semiconductor layer 8, an extremely short channel region (channel length) of several microns or less can be formed. The source electrode is in ohmic contact with both the source region 8 of the n-type semiconductor layer and the n-type semiconductor layer 4 (or n-type semiconductor layer 3) forming the channel region. The gate electrode is generally shaped in a lattice shape or in a stripe shape, but the lattice shape is shown here. The 0-type semiconductor substrate 1 is a drain region and has an n-on diode structure. A train electrode (not shown) is formed on the back surface of the chip, and when a positive voltage is applied between the gate and source to turn on the channel, current flows vertically from the substrate, passes through the channel region, and flows into the source.

Next, using FIGS. 6(a) to (f), the conventional DSA
The manufacturing process of MOS will be explained. An n-type epitaxial growth layer 2 is formed on an n-type semiconductor substrate 1 with a specific resistance of 10 to 2, for example.
After forming a layer of 5 Ωcm and a thickness of 30 to 60 μm, an n-type semiconductor layer 3 is formed from the surface. After that, the gate oxide film 5a is
FIG. 6(a) shows how 000A was formed.

Next, the polycrystalline silicon film 6 is selectively patterned after being deposited, for example, 6000^, and ions are implanted using this polycrystalline silicon pattern as a mask to form the n-type semiconductor layer 4 in the channel region in a self-aligned manner. This situation is shown in Figure 6 (
Shown in b).

Subsequently, a portion of the source region where the n-type semiconductor layer is to be formed is selectively opened using photoresist using a photoetching technique, as shown in FIG. 6(C).

Next, an n-type semiconductor layer 8 and an oxide film 5b in the source region are formed (as shown in FIG. 6(d)), and a PSG film 5C of approximately 800 OA is deposited thereon by CVD. Shown in e).

Thereafter, after performing various heat treatments, an electrode extraction opening is formed and an aluminum (/l) electrode 9 is formed to increase the source-drain breakdown voltage Vo s s ,2
A DSA MOS of about 00 to 600V is completed. This situation is shown in FIG. 6(f).

[Problems in the background technology] In general, MOS FETs are capable of high-speed switching because there is no accumulation of minority carriers, and have high thermal stability because the drain current has a negative temperature coefficient. However, compared to bipolar transistors, since they are majority carrier elements, there is a significant trade-off between high withstand voltage and high power, and the substrate resistance layer required for high withstand voltage directly increases the saturation voltage. This has the disadvantage that the on-resistance increases with the same chip area. In order to solve this problem, it is necessary to reduce the resistance of the current path of the FET, especially the drain resistance. In other words, the question is how to increase the area efficiency of the drain, and the best pattern design must be made by making full use of microfabrication technology for the first c. DSA M'O8 is generally used as a structure that satisfies these requirements.
has been adopted.

However, the pattern design of the conventional DSA MOS FET is not necessarily the optimal design.

A polycrystalline silicon pattern that allows a long current path, or channel width, within the limited silicon chip area.
Various ideas are required regarding the shape of the channel region. By increasing the channel width, it is possible to obtain a large amount of drain current, and also to obtain a large mutual conductance gm in a large current region. Since these are the biggest factors that make it possible to reduce on-resistance, the biggest goal was how to obtain a long channel width within a limited area.

Therefore, when we examine the gate polycrystalline silicon patterns of high-voltage power MO8FETs conventionally used in switching power supplies and the like, we find that most of them have a square lattice shape.

Incidentally, referring to the plan view of the conventional device shown in FIG. The relationship with the width L2 between the corners is L247L1.

In order to integrate a large number of source n regions and gate polycrystalline silicon patterns within a predetermined area (to increase the channel width), it is desirable that the rings L1 and L2 are equal.

This is because the channel region exists along the edge of the gate polycrystalline silicon pattern, so in order to obtain a large channel width, it is preferable that L1 = 12, and Ll < 1.
2, a gate polycrystalline silicon film with an extra area corresponding to the difference (L2-Ll) is formed. This also increases the gate area and increases the capacitance between the drain and the gate, which impedes the switching speed.

In addition, it is generally well known that each pattern is miniaturized to increase the channel width, and as a result, the gate polycrystalline silicon pattern and source region are reduced, and the channel width can be increased accordingly. . However, in the conventional gate polycrystalline silicon pattern having a rectangular lattice shape, the area of the source electrode opening tends to be too large relative to the drain current capacity. Although many independent channel regions can be formed by miniaturization (the channel width can be increased by miniaturization), 1
The channel width in one cell (the region where the P-type soil conductor layer 4 and the N1-type semiconductor layer 8 are present using the opening of the polycrystalline silicon film as a diffusion mask) is reduced. In other words, when operating as a MoS transistor under the same conditions, although the smaller channel width has smaller current capacity,
There are many electrode lead-out openings in the source region formed within the cell.

As is well known, MOS FETs have less thermal runaway than bipolar transistors, and therefore do not require an unnecessary opening for the source electrode. It is necessary to use this unnecessary portion to form more channel regions and to arrange the pattern so as to obtain a longer channel width.

[Objective of the Invention] The present invention has been made in view of the above circumstances, and aims to reduce on-resistance, improve mutual conductance gm and switching speed, or reduce chip area.
It is an object of the present invention to provide a semiconductor device with an optimal pattern design that enables improved productivity.

[Summary of the Invention] In order to achieve the above object, the present invention makes the width of the gate polycrystalline silicon pattern almost equal in all parts, and even if the pattern is miniaturized, the optimum source can be adjusted according to the current capacity. This is a semiconductor device in which an appropriate pattern shape can be arranged in order to obtain an electrode extraction opening.

[Embodiments of the invention] The present invention will be specifically explained below using Examples.

FIG. 1 shows an embodiment of the present invention, and FIG.
”) is A! DSA after (aluminum) electrode formation
It is a top view of MOS FET (7), and the same figure (b) is the sectional structure diagram on the AA line.

In this device, an n-type epitaxial growth layer (first semiconductor layer) 2 is formed on an n-type semiconductor substrate 1, and a multilayer film is formed on the main surface of the first semiconductor layer 2 with an insulating oxide film (first insulating film) 5a interposed therebetween. A crystalline silicon (or conductor film) pattern 6 is formed,
The first semiconductor layer is located in the first semiconductor layer 2 at a position where a portion of the semiconductor film pattern 6 overlaps via the first insulating film 5a.
A P-type semiconductor layer (second semiconductor layer) 4 having a conductivity type opposite to that of the semiconductor layer 2 is formed, and the conductive film is formed on the surface of the second semiconductor layer 4 via the first insulating film 5a. pattern 6
n1 type semiconductor layer (third semiconductor layer) at a position where a part of
8 is formed, an insulating oxide film (second insulating film) 5d is formed to cover the conductor film pattern 6, an opening 11 is formed by the second insulating film 5d, and a conductor film including the opening 11 is formed. Al electrode film (metal electrode film) on the second insulating film 5d
The planar shape of the second semiconductor layer pattern 4, which is surrounded by the conductor film pattern 6 and formed on the surface of the first semiconductor layer 2, is 8 as shown in FIG. 1(a). Octagonal semiconductor layer patterns 4A, 4 with two sides
B, 4C, and a connecting semiconductor layer pattern 4D that connects adjacent sides of these three octagonal semiconductor layer patterns;
4E, and the connecting semiconductor layer patterns 4D and 4E are formed thinner than the octagonal semiconductor layer patterns. In the figure, 10 is a gate polycrystalline silicon film opening (cell), and 11 is a source electrode extraction opening. Note that the source AN electrode 9 is connected to the source n region 8.
and a P-type semiconductor layer 4 forming a channel region, and a P-type semiconductor layer 4 that is in ohmic contact with this channel P-type semiconductor layer 4.
The semiconductor layer 3 is electrically connected to both sides of the semiconductor layer 3. Here, the distance L1 between the sides between each cell 10 and the distance between the corners! The relationship of IL2 is set to be 11412.

2 to 4 are plan views showing other embodiments of the present invention. The difference between the one in FIG. 2 and the one in FIG. 1 is the two octagonal semiconductor layer patterns 4A.

One connecting semiconductor layer pattern 4D is arranged between adjacent sides of 4B and formed continuously.

FIG. 3 shows two hexagonal semiconductor layer patterns 4F.

Semiconductor layer pattern 4H for connecting adjacent sides of 4G
It is tied with

What is shown in FIG. 4 is two rectangular semiconductor layer patterns 41.
Adjacent sides of 4J are connected by a connecting semiconductor layer pattern 4.

In either case, the edges of the gate polycrystalline silicon pattern can be designed to be long within a defined area by alternating the arrangement, that is, the channel width can be designed to be large.

[Effects of the Invention] In order to improve the performance of semiconductor devices, especially MIS type semiconductor devices, the present invention improves the performance by improving the gate polycrystalline silicon pattern, increasing the channel width, and increasing the current capacity per unit area. We are trying to improve.

This will be explained by comparing the dimensional relationship with the conventional device. The same design rule is adopted for the magnification of the plan view of FIG. 5(a), which is a conventional example, and the plan views of FIGS. 1(a), 2 to 4, which show the embodiment of the present invention. , the vertical length YL within the predetermined area surrounded by the broken line is set to 12CI11, and the horizontal length XL is set to 16 cm.

In FIG. 5(a), there are 3×4=12 source electrode extraction openings 10, and the length of one side of one cell is Lo.
Since t (-LO2) is 2CI11, the channel width of one cell (the entire circumference of the cell) is Bcm, and the total channel width within this broken line frame is 95cm.

On the other hand, in Part 1-(a), the length of the straight side Loa of the octagon is 1 cm, and the oblique 45° side Loa (=JY/2
LO3> is approximately Q, 7cm, and the connecting side Los is 2CI
Il, so the channel width of one cell 10 is approximately 2
4.4 cm, and the channel width in the pattern area within the broken line is approximately 113.2 cm. In addition, the side Los in FIG. 3 is 2 cm, and the side Lo 7 is 1.5 cm.

Hypotenuse Lo e a=, o, 7cn+, connecting side 1-o
s=6 cm, and the channel width of the cell included within the dashed line is approximately 111.80 IIl. Furthermore, the side l−+ in FIG.

=2C111, side L++=2CI11. Edge+z=O,
'5cm, connecting side L13=10CI11, so the channel width of all cells included in the area is 108
0IIl. In any case, the channel width becomes larger than that of the conventional one, and the difference becomes larger as the number of cells increases or as the pattern area becomes larger.

As described above, according to the embodiment of the present invention, the channel width can be greatly increased. The reason for this is that by effectively using the 45° oblique line, Ll and 1 in Fig. 5(a) can be
This is because the relationship with 2 is set to LI LFL2. Therefore, by arranging the cells 10 alternately, it is possible to integrate the cell pattern arrangement in the central area despite the same design rule, and therefore more cells can be integrated than in the conventional method. It has become possible.

Next, when miniaturization is advanced, especially when cell and gate polycrystalline silicon patterns are downsized, in the conventional embodiment, source electrode extraction openings are required at intervals of several microns.

In other words, the source electrode extraction opening has the drawback of being constrained by design rules. In the present invention, the second
Figures and Figure 3.

As shown in FIG. 4, the interval between the source electrode extraction openings can be arbitrarily designed, and the channel width does not decrease.

In general, the smaller the area of the source region, the larger the channel width can be obtained. Therefore, with the same design rule, there are 12 pieces per unit area (within the dotted line) in the conventional example, but with the same design rule,
According to the present invention, the number of channels can be reduced to 7 in FIG. 3 and 6 in FIG. 4, and the channel width is 111.
8cm, and the one in Figure 4 is 108cm.

In view of the above, the present invention provides an appropriate gate polycrystalline silicon pattern so as to obtain a large channel width within a defined chip area, and provides an appropriate gate polycrystalline silicon pattern for cells corresponding to the openings of the gate polycrystalline silicon pattern. By arranging the drain current, it is possible to obtain a large drain current.
In addition, we have created an optimal pattern that increases the mutual conductance (lnl) in the high current region, increases switching speed, reduces on-resistance, and further reduces the chip area and improves productivity. Among the semiconductor layers, the present invention is particularly characterized in that it can provide MIS type semiconductor devices.

Although the embodiment according to the present invention is an MO8 type semiconductor device, the present invention is not limited to this. For example, a polycrystalline silicon pattern may be used as an emitter region and a cell pattern as a base, or vice versa. This is a bipolar semiconductor device with a base region cell pattern as an emitter region, and can also be applied to transistors aimed at high-speed switching.

[Brief explanation of drawings]

FIGS. 1(a) and (b) show a plan view of an MO8 type semiconductor device according to the present invention and a cross-sectional view taken along the line A-A, and FIGS. 2 to 4 show other embodiments. The fifth
Figures (a) and (b) are a plan view and a cross-sectional structural view taken along line A-A' of the conventional embodiment, and Figure 6 (a)
) to (f) show the trial production process diagrams. 1... N-type semiconductor substrate (drain) 2... N-type epitaxial semiconductor layer (drain) 3.
...P" type semiconductor layer 4...P type semiconductor layer (channel region) 5a, 5b,
5c, 5d... Insulating film 6... Polycrystalline silicon (gate electrode film) 7... Photoresist, 8... N-type semiconductor layer (source) 9... A escape electrode material 10... Polycrystalline silicon layer opening (cell) No. 6
figure

Claims (2)

[Claims] (1) A semiconductor film or a conductor film pattern is provided on the main surface of a first semiconductor layer of a first conductivity type with a first insulating film interposed therebetween, A second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer is provided at a position where a part of the semiconductor film or conductor film pattern overlaps, and A third conductive layer of the first conductivity type is provided at a position where the semiconductor film or conductor film pattern partially overlaps.
a semiconductor layer, a second insulating film covering the semiconductor film or the conductive film pattern, an opening formed by the second insulating film, and a second insulating film including the opening; In a semiconductor device having a metal electrode film, the planar shape of the second semiconductor layer surrounded by the conductor film pattern and formed on the surface of the first conductor layer has sides that are an integral multiple of 2. a polygonal semiconductor layer pattern section, and a connecting semiconductor layer pattern section connecting adjacent sides of at least two or more polygonal semiconductor layer pattern sections; A semiconductor device characterized in that the pattern portion is formed thinner than the polygonal semiconductor layer pattern portion. (2) The polygonal semiconductor layer pattern portion has an octagonal shape, and the connecting semiconductor layer pattern portion is one or more connecting semiconductor layer pattern portions that connect two or three adjacent sides of the octagonal semiconductor pattern portion. The semiconductor device according to claim 1, characterized in that there are two pattern portions.