JP3008480B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3008480B2 JP3008480B2 JP2297226A JP29722690A JP3008480B2 JP 3008480 B2 JP3008480 B2 JP 3008480B2 JP 2297226 A JP2297226 A JP 2297226A JP 29722690 A JP29722690 A JP 29722690A JP 3008480 B2 JP3008480 B2 JP 3008480B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- drain
- semiconductor
- substrate
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 41
- 239000000758 substrate Substances 0.000 claims description 41
- 238000000605 extraction Methods 0.000 claims description 21
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 32
- 108091006146 Channels Proteins 0.000 description 19
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 230000001965 increasing effect Effects 0.000 description 4
- 239000008186 active pharmaceutical agent Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） この発明は、半導体装置に関し、特にオン抵抗を低減
するのに好適な構造を有するパワーMOSFETに関するもの
である。The present invention relates to a semiconductor device, and more particularly to a power MOSFET having a structure suitable for reducing on-resistance.
（従来の技術） 従来のパワーMOSFETとしては、例えば第８図（Ａ）に
示すようなものが知られている。この従来例は、VDMOS
と呼ばれる縦型構造のパワーMOSFETを示している。同図
において、112は高濃度のN+基板であり、N+基板112上に
は実質的なドレイン領域を成すＮ形エピタキシャル層
（以下、Ｎエピ層という）102が形成されている。Ｎエ
ピ層102の表面側にはＰ形チャネル領域103が形成され、
さらにＰ形チャネル領域103内にはN+ソース領域104が形
成されている。また、N+ソース領域104とドレイン領域
としてのＮエピ層102との間におけるＰ形チャネル領域1
03上には、Ｐ形チャネル領域103の表面層にチャネルを
誘起させるためのポリSiからなるゲート107がゲートSiO
2108を介して形成されている。110は中間絶縁膜、123は
ソース電極、124はドレイン電極であり、ドレイン電極1
24はN+基板112の裏面に形成されている。Ｐ形チャネル
領域103とN+ソース領域104とは、ポリSiのゲート107を
マスクにしてＮエピ層102中へ、順次、Ｐ形不純物及び
Ｎ形不純物をイオン注入、ドライブインすることによっ
て作られている。(Prior Art) As a conventional power MOSFET, for example, a power MOSFET as shown in FIG. 8A is known. This conventional example uses VDMOS
2 shows a power MOSFET having a vertical structure called a vertical type. In the figure, 112 is a high concentration of N + substrate, N-type epitaxial layer constituting a substantial drain region is formed on the N + substrate 112 (hereinafter, referred to as N epi layer) 102 is formed. A P-type channel region 103 is formed on the surface side of the N-epi layer 102,
Further, an N + source region 104 is formed in the P-type channel region 103. Further, a P-type channel region 1 between the N + source region 104 and the N epi layer 102 as a drain region
A gate 107 made of poly-Si for inducing a channel in the surface layer of the P-type channel region 103 is formed on the gate SiO 3.
2 formed through 108. 110 is an intermediate insulating film, 123 is a source electrode, 124 is a drain electrode, and the drain electrode 1
Reference numeral 24 is formed on the back surface of the N + substrate 112. The P-type channel region 103 and the N + source region 104 are formed by sequentially ion-implanting and driving P-type impurities and N-type impurities into the N-epi layer 102 using the poly-Si gate 107 as a mask. ing.
近年、微細加工技術の進歩によってセル（基本MOSト
ランジスタ）密度が向上し、100V以下の耐圧のVDMOSで
は、1mmΩ・cm2を切る低オン抵抗のものが発表されてい
る（「Blanket LPCVD Tungusten Silicide Technolo
gy for Smart Power Applications」Krishina Shenai
etal.IEEE EDL vol 10,No.6,June 1989,pp270〜27
3）。In recent years, the density of cells (basic MOS transistors) has increased due to advances in microfabrication technology. VDMOS with a withstand voltage of 100 V or less have been announced with low on-resistance of less than 1 mmΩ · cm 2 (“Blanket LPCVD Tungusten Silicide Technolo
gy for Smart Power Applications '' Krishina Shenai
etal.IEEE EDL vol 10, No.6, June 1989, pp270〜27
3).
しかしながら、このように微細化が進むとチャネル抵
抗Rchが減少する半面、チップの厚みの大半を占めるN+
基板112の抵抗が無視できなくなってきた。第８図
（Ｂ）には本発明者等が計算した微細化とオン抵抗の関
係を示す。丸形のセルで、そのセルサイズ（セル直径）
が10μｍを切るようになるとN+基板101の抵抗が50〜60
％を占めるようになることが判る。N+基板112の抵抗を
減らす手段としてその不純物濃度を上げる、或いは厚さ
を薄くする方法は、それぞれＮエピ層102の結晶性の悪
化、機械的強度の低下（ウェーハの割れ）という問題を
招くことから限界にきている。However, as the miniaturization advances, the channel resistance Rch decreases, but N + occupies most of the chip thickness.
The resistance of the substrate 112 cannot be ignored. FIG. 8B shows the relationship between miniaturization and on-resistance calculated by the present inventors. A round cell whose cell size (cell diameter)
Becomes smaller than 10 μm, the resistance of the N + substrate 101 becomes 50 to 60.
It can be seen that the percentage will be occupied. A method of increasing the impurity concentration or reducing the thickness of the N + substrate 112 as a means for reducing the resistance of the N + substrate 112 causes problems such as deterioration of the crystallinity of the N epi layer 102 and reduction of the mechanical strength (wafer cracking). We are reaching our limits.
また、従来のパワーMOSFETとして、第９図に示すよう
に、ドレイン電極も半導体基板の表面から取出すように
したLDMOSと呼ばれる横型構造のものがある。同図にお
いて、125はN+ドレイン領域であり、このN+ドレイン領
域125に接続されたドレイン電極113が、ソース電極116
と同様に、半導体基板の表面側に設けられている。LDMO
Sでは、電流はN+ドレイン領域125からＮエピ層102を経
てＰ形チャネル領域103表面の反転層で形成されたチャ
ネルを通りN+ソース領域104へと主に基板表面を流れる
ため基板抵抗の影響は少ない。しかしドレイン電極113
取出しのために新たにN+ドレイン領域125を設ける必要
があることと、配線数の増加によってセル密度が落ちて
しまうという問題がある。さらに本質的な問題として、
ドレイン・ソース間耐圧BVDSがN+ドレイン領域125とＰ
形チャネル領域103の間の距離Ｌに依存するため、距離
Ｌを不用意に小さくできないことからセルの微細化には
限界があった。As a conventional power MOSFET, as shown in FIG. 9, there is a lateral structure called an LDMOS in which a drain electrode is also taken out from the surface of a semiconductor substrate. In the figure, reference numeral 125 denotes an N + drain region, and a drain electrode 113 connected to the N + drain region 125 is a source electrode 116.
Similarly to the above, it is provided on the front side of the semiconductor substrate. LDMO
In S, current flows mainly from the N + drain region 125 to the N + source region 104 through the channel formed by the inversion layer on the surface of the P-type channel region 103 through the N epi layer 102 to the N + source region 104. The effect is small. However, the drain electrode 113
There is a problem that it is necessary to newly provide an N + drain region 125 for extraction, and that the cell density decreases due to an increase in the number of wirings. More fundamentally,
Drain-source breakdown voltage BV DS is N + drain region 125 and P
Since the distance L cannot be reduced carelessly because it depends on the distance L between the channel regions 103, there is a limit to the miniaturization of cells.
（発明が解決しようとする課題） 従来のVDMOSは、セルサイズを微細化するとチップの
厚みの大半を占めるN+基板部分の抵抗の影響がでてきて
十分に低オン抵抗とすることが困難であるという問題が
あった。(Problems to be Solved by the Invention) In the conventional VDMOS, when the cell size is reduced, the resistance of the N + substrate portion which occupies most of the thickness of the chip appears, and it is difficult to sufficiently reduce the ON resistance. There was a problem.
また、LDMOSは、電流が主に基板表面を流れるため基
板抵抗の影響が減るが、基板表面に、ドレイン電極取出
しのためにN+ドレイン領域を設ける必要があること及び
ドレイン・ソース間耐圧を所定値以上に保持する必要か
らN+ドレイン領域とＰ形チャネル領域間の距離を不用意
に小さくできないこと等のためにセル密度を上げること
ができないという問題があった。In addition, LDMOS reduces the effect of substrate resistance because current mainly flows on the substrate surface.However, it is necessary to provide an N + drain region on the substrate surface for taking out the drain electrode, and the drain-source breakdown voltage is specified. Since the distance between the N + drain region and the P-type channel region cannot be inadvertently reduced due to the necessity of maintaining the value higher than the value, there is a problem that the cell density cannot be increased.
この発明は、このような従来の問題に着目してなされ
たもので、セル密度を向上させることができるととも
に、十分に低オン抵抗とすることのできる半導体装置を
提供することを目的とする。The present invention has been made in view of such a conventional problem, and an object of the present invention is to provide a semiconductor device capable of improving cell density and having sufficiently low on-resistance.
［発明の構成］ （課題を解決するための手段） この発明は上記課題を解決するために、第１導電形の
半導体基体と、半導体基体の一主面の上に形成され、ド
レイン領域を成す第１導電形の半導体領域と、半導体領
域の一主面側に形成された第２導電形のチャネル領域
と、チャネル領域内に形成された第１導電形のソース領
域と、ソース領域と半導体領域との間におけるチャネル
領域の上に形成された絶縁ゲートと、半導体領域の一主
面から所要深さに形成され、周面が絶縁膜により半導体
領域から絶縁されるとともに底面で半導体基体に接続さ
れた第１導電形のドレイン引出し領域と、ソース領域、
絶縁ゲート及びドレイン引出し領域にそれぞれ接続され
半導体基体の一主面側に設けられた各電極とを有し、１
つのソース領域の周りに６つのドレイン引出し領域が等
間隔に配置されたセル構造を有する半導体装置であるこ
とを要旨とする。[Constitution of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention forms a drain region formed on a semiconductor substrate of a first conductivity type and one main surface of the semiconductor substrate. A semiconductor region of the first conductivity type, a channel region of the second conductivity type formed on one main surface side of the semiconductor region, a source region of the first conductivity type formed in the channel region, a source region and the semiconductor region And an insulating gate formed on the channel region between the semiconductor region and the semiconductor region at a required depth from one main surface, and a peripheral surface is insulated from the semiconductor region by the insulating film and connected to the semiconductor base at the bottom surface. A drain extraction region of the first conductivity type, a source region,
Electrodes connected to the insulated gate and drain extraction regions and provided on one main surface side of the semiconductor substrate, respectively.
The gist is to provide a semiconductor device having a cell structure in which six drain extraction regions are arranged at equal intervals around one source region.
（作用） 半導体領域の一主面から所要深さに形成され、周面が
絶縁膜により半導体領域から絶縁されるとともに底面で
半導体基体に接続されたドレイン引出し領域を設けるこ
とにより、ドレイン・ソース間耐圧を所定値以上に保持
しつつセルの微細化が可能となり、セル密度の向上が得
られる。また、ドレイン・ソース間の電流通路に半導体
基体の一部が含まれるが、半導体基体部分によるオン抵
抗への影響は顕著に減少して十分に低オン抵抗化が可能
となる。さらに、１つのソース領域の周りに６つのドレ
イン引出し領域が等間隔に配置されたセル構造を有する
ことにより、チャンネル密度の高いセル配置が可能とな
る。したがって、さらなるセル密度の向上及び低オン抵
抗化が可能となる。(Function) By providing a drain extraction region formed at a required depth from one principal surface of the semiconductor region, the peripheral surface of which is insulated from the semiconductor region by the insulating film and connected to the semiconductor substrate at the bottom surface, The cell can be miniaturized while maintaining the breakdown voltage at or above a predetermined value, and the cell density can be improved. Further, although a part of the semiconductor substrate is included in the current path between the drain and the source, the influence of the semiconductor substrate on the on-resistance is significantly reduced, and the on-resistance can be sufficiently reduced. Further, by having a cell structure in which six drain extraction regions are arranged at equal intervals around one source region, a cell arrangement with a high channel density can be realized. Therefore, it is possible to further improve the cell density and reduce the on-resistance.
（実施例） 以下、この発明の実施例を図面に基づいて説明する。
この実施例の半導体装置はLDMOSのパワーMOSFETとして
構成されている。Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
The semiconductor device of this embodiment is configured as an LDMOS power MOSFET.
第１図ないし第３図は、この発明の一実施例を示す図
である。1 to 3 show an embodiment of the present invention.
なお、第１図ないし第３図及び後述の他の実施例を示
す図において、前記第９図における部材及び部位と同一
ないし均等のものは、前記と同一符号を以って示し、重
複した説明を省略する。In FIGS. 1 to 3 and the drawings showing other embodiments to be described later, members which are the same as or equivalent to those in FIG. 9 are denoted by the same reference numerals as those described above, and are described in duplicate. Is omitted.
まず、第１図を用いて、LDMOSの構造を説明する。同
図（Ａ）において、高濃度のN+基板又はN+埋込層（以
下、主にN+基板という）112の上に形成されたＮエピ層1
02は、LDMOSのドレイン領域の一部として電流通路とな
る他、ドレイン・ソース間耐圧を確保する電界緩和領域
として働く部分であり、その比抵抗、厚みはドレイン・
ソース間耐圧に応じて選ばれている。First, the structure of the LDMOS will be described with reference to FIG. In FIG. 1A, an N epi layer 1 formed on a high-concentration N + substrate or an N + buried layer (hereinafter mainly referred to as an N + substrate) 112 is formed.
02 is a part that functions as a current path as a part of the drain region of the LDMOS and also functions as an electric field relaxation region that secures a withstand voltage between the drain and the source.
It is selected according to the withstand voltage between the sources.
この実施例では、このＮエピ層102の部分に、周面が
絶縁膜106で当該Ｎエピ層102から絶縁され、下面の部分
がN+基板112に接続されたドレイン引出し領域105が形成
されている。ドレイン引出し領域105は抵抗を下げるた
めそれ自体が低抵抗の半導体又は金属材料で構成される
ことが好しい。この実施例では、Ｎ形高不純物濃度のポ
リSiが用いられている。ドレイン引出し領域105の表面
には、ドレイン電極113とのコンタクト抵抗を最小に抑
えるためにN+ドレインコンタクト領域101が形成されて
いる。ドレイン引出し領域105の下方側では、バルク内
での抵抗を下げる目的から低抵抗のN+基板112がドレイ
ン引出し領域105と比較的抵抗の高いＮエピ層102とをつ
ないでいる。In this embodiment, a drain extraction region 105 whose peripheral surface is insulated from the N epi layer 102 by an insulating film 106 and whose lower surface is connected to the N + substrate 112 is formed in the N epi layer 102. I have. It is preferable that the drain extraction region 105 itself is made of a low-resistance semiconductor or metal material in order to reduce the resistance. In this embodiment, N-type high impurity concentration poly-Si is used. On the surface of the drain extraction region 105, an N + drain contact region 101 is formed in order to minimize the contact resistance with the drain electrode 113. Below the drain extraction region 105, a low-resistance N + substrate 112 connects the drain extraction region 105 and the N-epi layer 102 having a relatively high resistance in order to reduce the resistance in the bulk.
なお、ドレイン引出し領域105の下面は、上述のよう
に、N+基板112に達するように形成されているが、これ
はデバイスに要求される耐圧によっては、Ｎエピ層102
の部分で止めてより浅く形成することも考えられる。The lower surface of the drain extraction region 105 is formed so as to reach the N + substrate 112 as described above. However, this depends on the withstand voltage required for the device,
It is also conceivable to stop at the portion and form a shallower portion.
第１図（Ｂ）は、第１図（Ａ）の平面パターンの構成
例を示している。この実施例の目的は、Ｐ形チャネル領
域103とN+ドレインコンタクト領域101との間の距離を短
くしてオン抵抗を下げることであるから、Ｐ形チャネル
領域103とN+ドレインコンタクト領域101はゲート107を
挟んで隣接している必要があり、その配置は同図のよう
な平行ストライプ状となる。したがってチップ表面のド
レイン電極113、ソース電極116の配置は第１図（Ｂ）及
び第３図のようないわゆる櫛歯電極となる。第３図にお
いて、109はAlゲート電極配線、115はゲートボンディン
グパッド、114はドレインボンディングパッド、117はソ
ースボンディングパッドである。FIG. 1 (B) shows an example of the configuration of the plane pattern of FIG. 1 (A). The purpose of this embodiment is to reduce the distance between the P-type channel region 103 and the N + drain contact region 101 to reduce the on-resistance, so that the P-type channel region 103 and the N + drain contact region 101 It is necessary to be adjacent to each other with the gate 107 interposed therebetween, and the arrangement is a parallel stripe shape as shown in FIG. Therefore, the arrangement of the drain electrode 113 and the source electrode 116 on the chip surface is a so-called comb-shaped electrode as shown in FIGS. 1 (B) and 3. In FIG. 3, reference numeral 109 denotes an Al gate electrode wiring, 115 denotes a gate bonding pad, 114 denotes a drain bonding pad, and 117 denotes a source bonding pad.
次に、第２図を用いて、上述のように構成されたLDMO
Sの動作を説明する。Next, referring to FIG. 2, the LDMO constructed as described above will be described.
The operation of S will be described.
まず、ゲート・ソース間電圧VGSが闘値電圧VTHに対し
VGS＜VTHのときはチャネルは遮断状態にあり、ドレイン
・ソース間電圧VDSによってバルク（Ｎエピ層）内部に
空乏層122が広がっている（第２図（Ａ））。これによ
ってＰ形チャネル領域103とＮエピ層102の間のPN接合に
かかる電界は緩和されドレイン・ソース間耐圧BVDS及び
ドレイン・ゲート間耐圧BVDGが確保される。First, the gate-source voltage V GS is higher than the threshold voltage V TH
When V GS <V TH , the channel is in a cutoff state, and the depletion layer 122 is spread inside the bulk (N epi layer) by the drain-source voltage V DS (FIG. 2 (A)). Thus an electric field applied to the PN junction between the P-type channel region 103 and the N epi layer 102 is relaxed breakdown voltage between the drain and source BV DS and drain-gate breakdown voltage BV DG is ensured.
従来問題となっていたコンタクト用のN+ドレイン領域
とＰ形チャネル領域間（第９図の125と103間）の耐圧に
ついては、ドレイン引出し領域105とＰ形チャネル領域1
03の間の絶縁膜106によって仕切ったので面積をとらず
に高い絶縁耐圧を得ている。The withstand voltage between the N + drain region for contact and the P-type channel region (between 125 and 103 in FIG. 9), which has been a problem in the past, is as follows.
Since it is partitioned by the insulating film 106 during the period 03, a high withstand voltage is obtained without taking up an area.
次に、VGS≧VTHのときは第２図（Ｂ）に示すようにＰ
形チャネル領域103の表面が反転してチャネル120が生
じ、導通状態となる。同図中、矢印121は電子の流れを
示している。電子121は、ソース電極116よりN+ソース領
域104、チャネル120、Ｎエピ層102、N+基板112、ドレイ
ン引出し領域105と流れN+ドレインコンタクト領域101よ
りドレイン電極113へと流れる。ドレイン引出し領域105
は金属又は低比抵抗半導体でありN+基板112もたかだか
数μｍ〜10μｍの距離を流れるだけであるから、従来の
VDMOSで問題になった基板抵抗によるオン抵抗増大の問
題が改善される。また、絶縁膜106による分離効果で、
Ｐ形チャネル領域・N+ドレインコンタクト領域間距離Ｌ
を従来のLDMOSよりも小さくすることができる。即ちチ
ャネル密度の向上によるオン抵抗の低減が実現できる。Next, when V GS ≧ V TH , as shown in FIG.
The surface of the shaped channel region 103 is inverted to form a channel 120, which is turned on. In the figure, arrow 121 indicates the flow of electrons. The electrons 121 flow from the source electrode 116 to the N + source region 104, the channel 120, the N epi layer 102, the N + substrate 112, the drain extraction region 105, and the N + drain contact region 101 to the drain electrode 113. Drain extraction area 105
Is a metal or a low-resistivity semiconductor, and the N + substrate 112 only flows at a distance of at most several μm to 10 μm.
The problem of increase in on-resistance due to substrate resistance, which has become a problem in VDMOS, is improved. In addition, due to the separation effect of the insulating film 106,
Distance L between P-type channel region and N + drain contact region
Can be made smaller than the conventional LDMOS. That is, a reduction in on-resistance due to an increase in channel density can be realized.
次いで、第４図ないし第７図には、この発明の他の実
施例を示す。Next, FIGS. 4 to 7 show another embodiment of the present invention.
この実施例は前記一実施例の持つ特徴に加え、基板表
面の電極金属を２層に形成することにより電極抵抗を下
げるとともに、よりチャネル密度の高いセル配置を可能
にしたものである。In this embodiment, in addition to the features of the above-described embodiment, the electrode metal on the substrate surface is formed in two layers, thereby reducing the electrode resistance and enabling a cell arrangement with a higher channel density.
前記一実施例の場合、その表面電極の配置は第３図に
示した櫛歯パターンとなり、ソース電極116、ドレイン
電極113はそれぞれ電流容量に見合った幅が必要とな
る。大電流のパワーMOSFETの場合、この電極幅は数10μ
ｍにも及ぶことがある。即ちＰ形チャネル領域103とN+
ドレインコンタクト領域101がそれだけ離れることにな
る訳であり大電流素子ではセル密度を高めるという効果
が少なくなるおそれがある。In the case of the above-described embodiment, the arrangement of the surface electrodes is the comb pattern shown in FIG. 3, and the source electrode 116 and the drain electrode 113 each need to have a width corresponding to the current capacity. For large current power MOSFETs, this electrode width is several tens of microns.
m. That is, the P-type channel region 103 and N +
This means that the drain contact region 101 is separated by that much, and the effect of increasing the cell density may be reduced in a large current element.
これに対し、この実施例では、第１層目のソース電極
116aがN+ドレインコンタクト領域101の周辺を除いてほ
ぼチップ全面に形成され、さらに、このソース電極116a
上に層間絶縁膜111を介して第２層目のドレイン電極113
aがチップ全面に形成されている。このため、基板表面
の電極中での収集抵抗はVDMOS並に低く抑えられる。On the other hand, in this embodiment, the first-layer source electrode
116a is formed on almost the entire chip except for the periphery of the N + drain contact region 101, and furthermore, the source electrode 116a
A second-layer drain electrode 113 is formed thereon with an interlayer insulating film 111 interposed therebetween.
a is formed on the entire surface of the chip. For this reason, the collection resistance in the electrode on the substrate surface can be suppressed as low as VDMOS.
さらに、重要な特徴として、前記一実施例ではそのN+
ソース領域、Ｐ形チャネル領域及びN+ドレインコンタク
ト領域の配置が平行ストライプ状に限られるのに対し、
この実施例ではこの制約がなくなり自由なセル配置を採
ることができる。セル配置の例を第５図及び第６図に示
す。Further, as an important feature, in one embodiment, the N +
The arrangement of the source region, the P-type channel region and the N + drain contact region is limited to the parallel stripe shape,
In this embodiment, this restriction is eliminated and a free cell arrangement can be adopted. 5 and 6 show examples of the cell arrangement.
第５図はセル輪郭を六角形に、N+ソース領域、N+ドレ
インコンタクト領域の拡散マスクをなすゲートポリSi開
口部を円形にしたものである。このような丸セル六角配
置は最もチャネル密度の高いセル配置であると言われて
おり、特に、この実施例のLDMOSの場合、耐圧確保のた
めにゲートポリSi幅を大きく取る必要がないためにVDMO
Sに比較してチップ面積増は最小限に抑えられる。第６
図ではセル輪郭を正方形に、ゲートポリSi開口部を四角
形にしている。この実施例では配線の自由度が高いので
この他にも六角セルやストライプセルその他各種形状の
セルパターンが考えられる。FIG. 5 shows a hexagonal cell contour and a circular gate poly-Si opening serving as a diffusion mask for the N + source region and the N + drain contact region. It is said that such a hexagonal round cell arrangement is the cell arrangement with the highest channel density.
The increase in chip area compared to S is minimized. Sixth
In the figure, the cell contour is square, and the gate poly-Si opening is square. In this embodiment, since the degree of freedom in wiring is high, hexagonal cells, stripe cells and other various cell patterns can be considered.
以上述べたように、この実施例は、オン抵抗低減の効
果が極めて大きく、表面電極形成工程が複雑になる点を
考慮に入れても大電流形LDMOSの実現に大いに有効であ
る。As described above, this embodiment is extremely effective in realizing a large current type LDMOS even in consideration of the fact that the effect of reducing the on-resistance is extremely large and the process of forming the surface electrode becomes complicated.
次いで、第７図を用いて、この実施例に係るLDMOSの
製造方法の一例を説明する。Next, an example of a method for manufacturing an LDMOS according to this embodiment will be described with reference to FIG.
（ａ、ｂ）N+基板又はN+埋込層112の上にＮエピ層102を
成長したSiウェーハを用意し、Si3N4膜をマスクにした
リアクティブイオンエッチ（RIE）でＮエピ層102の部分
にドレイン引出し領域を形成するための溝126を形成す
る。(A, b) N + substrate or an Si wafer grown an N epitaxial layer 102 was prepared on the N + buried layer 112, Si 3 N 4 N epitaxial layer with reactive ion etch (RIE) that a mask A groove 126 for forming a drain extraction region is formed in the layer 102.
（ｃ、ｄ）溝126の内面を酸化し、N+ドレインコンタク
ト領域とＮエピ層102を分離するための絶縁膜106として
の酸化膜を形成する。エッチングにより溝126の側面の
みに酸化膜を残す。(C, d) The inner surface of the groove 126 is oxidized to form an oxide film as an insulating film 106 for separating the N + drain contact region and the N epi layer 102. The oxide film is left only on the side surface of the groove 126 by etching.
（ｅ）高融点金属又はＮ形高不純物濃度のポリSiを蒸着
法、CVD法などによって溝126に埋込みドレイン引出し領
域105を形成する。最近ではSiの選択エピタキシャル成
長も可能になっているのでこれを使用してもよい。この
工程で微細デバイス形成にとって重要なウェーハ表面の
平坦化も同時に達成される。(E) A high melting point metal or poly-Si having an N-type high impurity concentration is buried in the groove 126 by a vapor deposition method, a CVD method, or the like to form a drain extraction region 105. Recently, selective epitaxial growth of Si has also become possible, and this may be used. In this process, planarization of the wafer surface, which is important for the formation of fine devices, is also achieved at the same time.
（ｆ）表面にゲートSiO2108を形成し、その上にポリSi
を堆積してパターニングすることによりゲート107を形
成する。(F) Gate SiO 2 108 is formed on the surface, and poly-Si
The gate 107 is formed by depositing and patterning.
（ｇ）ゲート107をマスクにしてボロンイオンをイオン
注入、ドライブインすることにより、Ｐ形チャネル領域
103を形成する。(G) By implanting and driving in boron ions using the gate 107 as a mask, a P-type channel region is formed.
Form 103.
（ｈ）図示省略のレジスト及びポリSiのゲート107をマ
スクにしてヒ素イオンをイオン注入、ドライブインする
ことにより、N+ソース領域104及びN+ドレインコンタク
ト領域101を形成する。次いで基板表面に、中間絶縁膜1
10としてPSG又はSi3N4或いはこれらの組合わせ膜を堆積
する。(H) N + source region 104 and N + drain contact region 101 are formed by ion implantation and drive-in of arsenic ions using a resist 107 and a gate 107 of poly-Si not shown as a mask. Then, on the substrate surface, the intermediate insulating film 1
Deposit PSG or Si 3 N 4 or a combination of these as 10.
（ｉ）中間絶縁膜110のコンタクト部分を開口し、１層
目のAl膜を蒸着してパターニングすることにより第１層
配線となるソース電極116aを形成する。(I) A contact portion of the intermediate insulating film 110 is opened, and a first layer Al film is deposited and patterned to form a source electrode 116a to be a first layer wiring.
（ｊ）ソース電極116a上に、層間絶縁膜111を形成す
る。(J) The interlayer insulating film 111 is formed on the source electrode 116a.
（Ｋ）層間絶縁膜111に第２層配線とのコンタクト部を
開口後、２層目のAl膜を蒸着し、パターニングして第２
層配線となるドレイン電極113aを形成する。この２層目
のAl膜は、ドレイン電極113aとして用いられる他、各ボ
ンディングパッドの形成にも用いられる。(K) After opening a contact portion with the second layer wiring in the interlayer insulating film 111, a second layer of Al film is deposited and patterned to form a second layer Al film.
A drain electrode 113a to be a layer wiring is formed. The second Al film is used not only as the drain electrode 113a but also for forming each bonding pad.
なお、上述の各実施例ではＮチャネルのLDMOSについ
て説明したが、ＰチャネルのLDMOSや類似構造の絶縁ゲ
ート形トランジスタ（IGT）などへ適用した場合も本発
明に含まれることは明らかである。In each of the embodiments described above, an N-channel LDMOS is described. However, it is apparent that the present invention includes a case where the present invention is applied to a P-channel LDMOS, an insulated gate transistor (IGT) having a similar structure, and the like.
［発明の効果］ 以上説明したように、この発明によれば、ドレイン領
域を成す第１導電形の半導体基体と、この半導体基体の
一主面側に形成された第２導電形のチャネル領域と、こ
のチャネル領域内に形成された第１導電形のソース領域
と、このソース領域と前記ドレイン領域との間における
前記チャネル領域上に形成された絶縁ゲートと、前記半
導体基体のドレイン領域に当該半導体基体の一主面から
所要深さに形成され周面が絶縁膜により当該ドレイン領
域から絶縁されるとともに底面で当該ドレイン領域に接
続されるドレイン引出し領域と、前記ソース領域、絶縁
ゲート及びドレイン引出し領域にそれぞれ接続され前記
半導体基体の一主面側に設けられた各電極とを具備させ
たため、ドレイン・ソース間耐圧を所定値以上に保持し
つつセルの微細化が可能となってセル密度の向上、ひい
てはチャネル密度を向上させることができ、また基体部
分によるオン抵抗への影響が顕著に減少して十分に低オ
ン抵抗化を実現することができる。[Effects of the Invention] As described above, according to the present invention, a semiconductor substrate of the first conductivity type forming a drain region and a channel region of a second conductivity type formed on one main surface side of the semiconductor substrate are provided. A source region of the first conductivity type formed in the channel region, an insulated gate formed on the channel region between the source region and the drain region, and a semiconductor in the drain region of the semiconductor substrate. A drain extraction region formed at a required depth from one main surface of the base and having a peripheral surface insulated from the drain region by an insulating film and connected to the drain region at a bottom surface; and the source region, the insulated gate, and the drain extraction region. And each electrode provided on one main surface side of the semiconductor substrate, while maintaining the withstand voltage between the drain and the source at a predetermined value or more. It is possible to miniaturize the cell, thereby improving the cell density and, consequently, the channel density. In addition, the influence of the base portion on the on-resistance is remarkably reduced to realize a sufficiently low on-resistance. it can.
第１図ないし第３図はこの発明に係る半導体装置の一実
施例を示すもので、第１図は構造を示す縦断面図及び平
面図、第２図は動作を説明するための縦断面図、第３図
はチップ表面の電極パターンの構成例を示す平面図、第
４図ないし第７図はこの発明の他の実施例を示すもの
で、第４図は構造を示す縦断面図、第５図はセル配置例
を示す平面図、第６図はセル配置の他の例を示す平面
図、第７図は製造方法の一例を示す工程図、第８図は従
来のVDMOSを示す図、第９図は他の従来例であるLDMOSを
示す縦断面図である。 101:N+ドレインコンタクト領域、 102:N+基板とともに第１導電形の半導体基体を構成する
Ｎエピ層、 103:P形チャネル領域、 104:N+ソース領域、 105:ドレイン引出し領域、 106:絶縁膜、107:ゲート、 108:ゲートSiO2、112:N+基板、 113、113a:ドレイン電極、 116、116a:ソース電極。1 to 3 show one embodiment of a semiconductor device according to the present invention. FIG. 1 is a longitudinal sectional view and a plan view showing a structure, and FIG. 2 is a longitudinal sectional view for explaining an operation. FIG. 3 is a plan view showing a configuration example of an electrode pattern on the chip surface, FIGS. 4 to 7 show another embodiment of the present invention, FIG. 4 is a longitudinal sectional view showing the structure, and FIG. 5 is a plan view showing an example of a cell arrangement, FIG. 6 is a plan view showing another example of a cell arrangement, FIG. 7 is a process diagram showing an example of a manufacturing method, FIG. 8 is a diagram showing a conventional VDMOS, FIG. 9 is a longitudinal sectional view showing another conventional LDMOS. 101: N + drain contact region, 102: N-epi layer constituting a semiconductor substrate of the first conductivity type together with the N + substrate, 103: P-type channel region, 104: N + source region, 105: drain extraction region, 106: Insulating film, 107: gate, 108: gate SiO 2 , 112: N + substrate, 113, 113a: drain electrode, 116, 116a: source electrode.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/336 H01L 29/78 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/336 H01L 29/78
Claims (1)
を成す第１導電形の半導体領域と、 前記半導体領域の一主面側に形成された第２導電形のチ
ャネル領域と、 前記チャネル領域内に形成された第１導電形のソース領
域と、 前記ソース領域と前記半導体領域との間における前記チ
ャネル領域の上に形成された絶縁ゲートと、 前記半導体領域の一主面から所要深さに形成され、周面
が絶縁膜により前記半導体領域から絶縁されるとともに
底面で前記半導体基体に接続された第１導電形のドレイ
ン引出し領域と、 前記ソース領域、前記絶縁ゲート及び前記ドレイン引出
し領域にそれぞれ接続され前記半導体基体の一主面側に
設けられた各電極とを有し、 １つの前記ソース領域の周りに６つの前記ドレイン引出
し領域が等間隔に配置されたセル構造を有することを特
徴とする半導体装置。A first conductive type semiconductor substrate; a first conductive type semiconductor region formed on one main surface of the semiconductor substrate to form a drain region; and a first main surface formed on the one main surface side of the semiconductor region. A second conductivity type channel region, a first conductivity type source region formed in the channel region, and an insulated gate formed on the channel region between the source region and the semiconductor region A first conductivity type drain extraction region formed at a required depth from one main surface of the semiconductor region, a peripheral surface of which is insulated from the semiconductor region by an insulating film and connected to the semiconductor base at a bottom surface; Electrodes connected to the source region, the insulated gate, and the drain lead-out region, respectively, and provided on one main surface side of the semiconductor substrate. A semiconductor device having a cell structure in which rain extraction regions are arranged at equal intervals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2297226A JP3008480B2 (en) | 1990-11-05 | 1990-11-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2297226A JP3008480B2 (en) | 1990-11-05 | 1990-11-05 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04171765A JPH04171765A (en) | 1992-06-18 |
| JP3008480B2 true JP3008480B2 (en) | 2000-02-14 |
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ID=17843803
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|---|---|---|---|
| JP2297226A Expired - Fee Related JP3008480B2 (en) | 1990-11-05 | 1990-11-05 | Semiconductor device |
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| Country | Link |
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| JP4153932B2 (en) | 2004-09-24 | 2008-09-24 | 株式会社東芝 | Semiconductor device and manufacturing method of semiconductor device |
| US8097921B2 (en) | 2007-11-09 | 2012-01-17 | Denso Corporation | Semiconductor device with high-breakdown-voltage transistor |
| JP4788749B2 (en) * | 2007-11-09 | 2011-10-05 | 株式会社デンソー | Semiconductor device |
| JP5636827B2 (en) * | 2010-08-31 | 2014-12-10 | 株式会社デンソー | Semiconductor device |
| US9136368B2 (en) * | 2013-10-03 | 2015-09-15 | Texas Instruments Incorporated | Trench gate trench field plate semi-vertical semi-lateral MOSFET |
| JP6317694B2 (en) | 2015-03-16 | 2018-04-25 | 株式会社東芝 | Semiconductor device |
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