JPS61290768A - Vertical type semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the lowering of withstanding voltage by a punch-through phenomenon by equalizing the width of gate polycrystalline silicon patterns as much as possible and forming a P-type semiconductor layer in a channel region in a self-alignment manner at the center of a cell just under a source N<+> type semiconductor layer. CONSTITUTION:An N-type epitaxial growth layer 2 is formed onto an N+ type semiconductor substrate 1, and a polycrystalline silicon film pattern 6 is shaped onto the main surface of the layer 2 through an insulating oxide film 5a. P-type semiconductors 3 to which a reverse conduction type impurity is doped in high concentration are formed into the layer 2, and P-type semiconductor layers 4 to which the reverse conduction type impurity is doped in low concentration are shaped shallowly. P<+> type semiconductor layers 11 are formed at regular intervals along the edge of the pattern to opening sections for the pattern 6, and N<+> type semiconductor layers 8 are shaped. An insulating oxide film 5d is formed so as to coat the pattern 6, and a source Al electrode film 9a is shaped onto the oxide film 5d. The electrode film 9a is ohmic- connected to the semiconductor layers 4 and 8 through source-electrode leading-out opening sections 10a in a cell formed to the insulating film 5d.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a vertical semiconductor device for the purpose of switching or amplification and a method of manufacturing the same, and particularly relates to techniques for miniaturization and high performance.

(Prior art) Among MIS type semiconductor devices, MOS FETs in particular were traditionally thought to be low voltage and low power devices, but with recent developments in semiconductor manufacturing technology and circuit design technology,
It has become possible to design high-voltage and high-power devices, and has now secured its place as a power device.

Typical examples of such high-voltage power MO8FETs include: ■offset gate structure, ■V-G root or U-G root structure, and ■DSA (Diffus
ion Self-Alionment) structure, etc., but among these, the conventional DSA structure power MO8FET (hereinafter referred to as O3
Figure M8 (a
) and (b), and the cross-sectional structure in the sequential manufacturing steps is shown in FIGS. 9(a) to (f). However, the source electrode is omitted in FIG. 8(a).

DSA MOS forms a channel by double diffusion, and the channel region is formed through the same diffusion window surrounded by a lattice-shaped gate polycrystalline silicon film 6 formed through a gate oxide film 5a. Impurity diffusion (p
It is characterized in that a type semiconductor layer 4) and impurity diffusion (n+ type semiconductor layer 8) for forming a source region are performed. Since the channel length is determined by the difference in diffusion depth between the p-type semiconductor layer 4 and the n0-type semiconductor layer 8, it can be formed extremely short, several microns or less. The source electrode 9 formed on the insulator 11a5d is an n-medium semiconductor lI forming a source region.
It is in ohmic contact with both the p-type semiconductor layer 4 (or the p-type semiconductor layer 3) forming the channel region. The gate electrode is generally shaped in a lattice shape or in a stripe shape, but the lattice shape is shown here.

The n-type semiconductor substrate 1 is a drain region, and the
It has an n-on-n-ten structure in which a molded pitaxial growth layer 2 is deposited. Although the drain electrode is not shown, it is formed on the back surface of the chip, and when a positive voltage is applied between the gate and source to turn on the channel, current flows vertically from the substrate 1, passes through the drain region 4, and reaches the source region. Flows into 8. Incidentally, the broken lines in FIG. 8(a) indicate the contours of the openings in the polycrystalline silicon film pattern 6 constituting each cell.

Next, using FIGS. 9(a) to <r>, the conventional DSA
The manufacturing process of MOS will be explained. n medium-sized semiconductor substrate 1
An n-type epitaxial growth layer 2 is formed on top with a specific resistance of 10, for example.
After forming to ~25ΩG and 30 to 60μm thickness, ρ from the surface
A ten-type semiconductor Ji13 is formed. After that, the gate oxide film 5a is formed to a thickness of about 1000 mm in FIG. 9(a).
).

Next, a polycrystalline silicon film 6 is deposited to a thickness of, for example, 5 mm, and then selectively buttered, and ions are implanted using this polycrystalline silicon film pattern as a mask to form an n-type semiconductor layer 4 that will become a channel region. is formed in a self-consistent manner. This situation is shown in FIG. 9(b).

Next, using photo-etching technology, a photoresist is used to selectively form an opening in the area where the n-type semiconductor WI8, which will become the source region, is to be formed, as shown in FIG. 9(C).
Shown below.

Next, the n-type semiconductor layer 8 and oxide film 5b, which will become the source region.
(as shown in FIG. 9(d)), and then PSG (ophospho 5ilicat
FIG. 9(e) shows how the eQ IaSS) film 5C is deposited to a thickness of about 8000 nm. In FIG. 8(b), the oxide film 5b and the PSG film 5C are shown together as a second insulating film 5d.

Next, after various heat treatments, oxidation 115b and PS
By forming an electrode extraction opening 10a in the GJIM5c and forming an aluminum (/l) electrode 9, a D with a source-drain breakdown voltage V of about 200 to 600V can be obtained.
SA MOS FET is completed.

This situation is shown in FIG. 9(f).

In general, MOS FETs have the advantage of high-speed switching because they do not accumulate minority carriers, and have high thermal stability because their train current has a negative temperature coefficient. Compared to this, since it is a majority carrier element, there is a significant trade-off between high withstand voltage and high power, and the substrate resistance layer required for high withstand voltage directly leads to an increase in saturation voltage, resulting in a large on-resistance for the same chip area. There was a drawback. In order to solve this problem, it is necessary to reduce the resistance of the power path of the FET, especially the drain resistance. In other words, the question is how to increase the area efficiency of the drain, and for this purpose, it is necessary to design the best pattern by making full use of microfabrication technology. A DSA MOS FET is generally employed as a structure that satisfies these requirements.

However, the pattern design of conventional DSA MOS FETs is not necessarily an optimal design. Various ideas are needed for the polycrystalline silicon film pattern and the shape of the channel region so that the width of the current path, that is, the channel width, which is the peripheral length of the channel, can be increased or the channel length can be shortened within the limited silicon chip area. It is. By increasing the channel width, it is possible to increase the drain current, and in addition, a large mutual conductance signal can be obtained in the large current region.

Since these are the biggest factors that make it possible to reduce on-resistance, the biggest goal was how to increase the channel width within a limited area.

Therefore, when we examine the gate polycrystalline silicon patterns of high-voltage power MO8FETs conventionally used in switching power supplies, etc., we find that most of them exhibit a square lattice shape as shown in Figure 8(a). There is.

In the plan view of FIG. 8(a), the length of the gate polycrystalline silicon film from the edge of the open pattern of the polycrystalline silicon film 6 of the cell to the edge of the open pattern of the cell adjacent vertically and horizontally. , and let p2 be the length between diagonally adjacent cells, then β2 is four times longer than β. In order to integrate a large number of R+ type source regions 8 and gate polycrystalline silicon films 6 within a predetermined area, it is desirable that the lengths β and β2 are equal. That is, since the channel region 4 exists along the pattern edge of the gate polycrystalline silicon film 6, in order to obtain a large channel width, J2. = J22, and λ2>1. Then, β2-J2. The polycrystalline silicon film 6 occupies an extra area corresponding to . This increases the gate area and increases the drain-to-gate capacitance, which impedes switching speed.

In addition, it is well known that each pattern is generally miniaturized to increase the channel width, and as a result, the gate polycrystalline silicon film pattern and source region are reduced, and the channel width increases accordingly. I can figure it out. However, in the conventional gate polycrystalline silicon pattern having a rectangular lattice shape, the number of source electrode openings tends to be too large relative to the ratio of drain current capacity. Miniaturization allows the formation of many independent channel regions, which results in an overall increase in channel width.
The channel width within one cell becomes smaller. In other words,
When operating as a MOS transistor under the same conditions, there are many electrode extraction openings in the source region formed in the cell, even though the smaller the channel width, the smaller the current capacity ω. become.

As is well known, a MOS FET has less thermal runaway than a bipolar transistor, and the current density obtained from one cell area is small, so there is no need for an unnecessary opening for the source electrode.

It is necessary to use this unnecessary portion to form more channel regions and to arrange patterns to increase the channel width. Therefore, it is important to devise a pattern to reduce the area of the source electrode extraction opening and effectively increase the channel width accordingly.

In terms of performance, especially with regard to improving switching speed, it is important to reduce the capacitance between the gate and drain. Typical methods for achieving this are increasing the thickness of the gate oxide film and reducing the area occupied by the gate polycrystalline silicon film pattern. However, the threshold voltage Vth, which is one of the MOS operating characteristics, and the mutual conductance m
For these reasons, there is a limit to increasing the thickness of the gate oxide film. Therefore, another typical method is to reduce the area occupied by the gate polycrystalline silicon film pattern on the gate oxide film. The easiest way to implement this method is to make the gate polycrystalline silicon film pattern thin.

However, making it thinner has the drawback of increasing resistance and slowing down switching speed.

Most conventional gate electrode materials are polycrystalline silicon films or high melting point metal films such as molybdenum films, and these materials are used as multilayer wiring material films because they are resistant to high-temperature processes.

For this reason, in a high-power DSA MOS FET, a polycrystalline silicon film is used as a typical gate electrode material, and has a two-layer electrode structure with an insulating film interposed between it and the source electrode AJ2Ill. Moreover, in order to increase the channel width, the gate polycrystalline silicon film pattern is designed to be thin and extremely long. Within a limited silicon chip, the length of the channel width and 1. Regarding the wiring resistance of the gate polycrystalline silicon film pattern, if the channel width is designed to be long in order to lower the on-resistance, the gate resistance increases and the switching speed becomes slower. Therefore, in the past, efforts were made to sacrifice the channel area within the chip, provide several 8β stripe patterns with excellent conductivity, and connect these to the gate polycrystalline silicon film in an effort to reduce gate resistance. . However, since the gate between the eight β electrodes is a polycrystalline silicon gate with a length of several hundred to several thousand microns,
Gate resistance remains high.

On the other hand, as another method of lowering the gate resistance, see Figure 10 (
As shown in a) and (b), there is an insulating film on the gate polycrystalline silicon film pattern to the gate! There is a comb-shaped electrode structure in which the patterns and source patterns are arranged at different angles.

In FIG. 10, the same parts as those shown in FIG. 8 are designated by the same reference numerals. This semiconductor device having a comb-shaped electrode structure has an n-type epitaxial layer 2 grown on an n-type semiconductor substrate 1, and has openings in a lattice shape on its main surface through a first insulating film 5a. Polycrystalline silicon 116 is patterned in this manner, and a p-type first semiconductor layer 3 is formed within the opening of this polycrystalline silicon 116.

A portion of the main surface of the epitaxial layer 2 is covered with the first insulating film 5a.
A p-type second semiconductor layer 4 is formed so as to overlap with the polycrystalline silicon film 6 through the first insulating film 5a, and a p-type second semiconductor layer 4 is formed so as to partially overlap with the polycrystalline silicon film 6 through the first insulating film 5a. An n medium-sized third semiconductor layer 8 is formed, and a second insulating film 5d is formed to cover the polycrystalline silicon [16] and its opening. Striped source and gate/l electrodes 9a and 9b are formed on the second insulating film, and the source and gate electrodes 9a are formed in the opening 10a in the second insulating film 5d and in the polycrystalline silicon film 6. The gate/l electrode 9b is ohmically connected to the first and third semiconductor layers 3 and 8 through the openings formed in the second insulating film 5d.
It is connected to the polycrystalline silicon film 6 through an opening 10b formed in the opening 10b.

(Problems to be Solved by the Invention) The semiconductor device having the conventional comb-shaped electrode structure shown in FIG.
In consideration of pattern recession due to isotropic etching of the film thickness of the J2 electrodes 9a and 9b, the source 8β electrode 9a and the gate/l electrode 9b must be separated by a certain distance.

Therefore, unless the pattern width of the gate polycrystalline silicon 1116 is increased or the cell area is increased, the source/l
Electrode separation between the electrode 9a and the gate/l electrode 9b becomes extremely difficult due to photolithography, which limits miniaturization and increases the capacitance between the gate and source, which in turn becomes a factor that hinders the improvement of switching speed. there were. On the other hand, the easiest way to lower the gate resistance is to increase the thickness of the gate polycrystalline silicon film 6, which has a slight effect, but it is possible to reduce the gate resistance by increasing the thickness of the gate polycrystalline silicon film 6. There is a drawback that one electrode 9b is easily cut off at the edge of the opening formed in the polycrystalline silicon m6.

Another factor for improving switching speed is to narrow the channel length. This channel length is determined by the difference in diffusion depth between the p-type semiconductor layer 4 and the semiconductor layer 8 in the channel region.

However, when considering switching speed, the following conditions must be met. In general, the drain current flows from the medium-size 10-type semiconductor layer 8 through the p-type semiconductor layer 4 in the channel region, from the n-type epitaxial layer 2 in the vertical direction to the drain region of the n0-type semiconductor substrate 1, and then flows from the n-type epitaxial layer 2 to the drain region of the n0-type semiconductor substrate 1 on the back surface of the substrate. taken out from the drain electrode. Therefore, the drain current flows between the p-type semiconductor layers 4 forming the channel region. Therefore, the p-type semiconductor layer 4 has a gate polycrystalline silicon g! If the p-type semiconductor layer is formed deeply, the flow path for the drain current becomes narrower, and the current path has a resistance valve, which in turn increases the on-resistance. It can also cause

In addition, by forming the p-type semiconductor layer 4 forming the channel region deeply, the region overlapping with the gate polycrystalline silicon film 6 increases. As is well known, the gate insulating film 5a has conventionally been formed extremely thin, with a thickness of 500 to 1200. Therefore, as a matter of course, the capacitance between the gate and the source increases, which may impede the switching speed. it is obvious. Therefore, by forming the p-type semiconductor layer 4 forming the channel region as shallow as possible, and also forming the medium-sized ten-type semiconductor layer 8 as shallow as possible, it is possible to create a DSA MOS FET with a narrow channel length and high switching speed. Realization becomes possible.

However, by forming the p-type semiconductor layer 4 forming the channel region shallowly and narrowing the channel length, the following new problem arises.

First, during MO8 operation, a depletion layer spreads from the p-type semiconductor layer 4 forming the channel region to the n-type epitaxial layer 2 side of the drain region. At the same time, a depletion layer also spreads within the p-type semiconductor layer 4.

This depletion layer spreads more easily when the concentration of the semiconductor layer or diffusion layer is low, and also spreads as the drain voltage becomes higher. Therefore, as a matter of course, a large amount of the depletion layer spreads toward the n-type epitaxial layer 2 side of the drain region where the concentration is low. However, in the case of an MO8 type FET having a DSA structure, since the channel regions 4 are formed to face each other in the cell portion, the depletion layers of both regions are spread close to each other, and the channel regions 4 are formed to face each other in the cell portion, so that the depletion layers of both regions are spread close to each other, and the channel regions 4 are formed to face each other in the cell portion. Since they collide in the nearby drain region, there is no obstacle to obtaining a large source-drain breakdown voltage. On the other hand, on the p-type semiconductor layer 4 side, by increasing the drain voltage higher and higher, the depletion layer in the p-type semiconductor layer 4 forming the channel region expands more and more and reaches the source n-medium semiconductor layer 8. . This is the so-called bunch-through phenomenon. At this point already source 10
The voltage between 42 will break down. In other words, since the channel length is narrow, the depletion layer quickly reaches the n0 type semiconductor layer 8, resulting in breakdown at a value smaller than the breakdown voltage determined by the bulk characteristics. In particular, in order to obtain a long channel width, the gate polycrystalline silicon film pattern must be miniaturized, and accordingly, the p-type semiconductor layer 4 constituting the channel must be formed by shallow diffusion. Naturally, thin and long patterns are formed between the gate polycrystalline silicon film patterns, so the bunch-through phenomenon is likely to occur in such portions.

In addition, as a method to make the bunch-through phenomenon less likely to occur,
In a conventional DSA MOS FET, a p-type medium semiconductor layer 3 is formed within the cell by photoetching technology. However, this method has the following drawbacks. First, with photolithography technology,
In order to form the pattern of the gate polycrystalline silicon film 6 by aligning with the p-type semiconductor layer 3, the p-type semiconductor layer in the channel region is formed in a self-aligned manner by the pattern of the gate polycrystalline silicon film 6. 4 and the p-type semiconductor layer 3 which is not formed in a self-aligned manner becomes inaccurate, and the long and short portions of the p-type semiconductor layer (channel region) 4 narrowed by the n0-type semiconductor layer 8 are as described above. It is formed under the n-medium semiconductor layer 8. In this case, bunch-through is likely to occur in the long narrow p-type semiconductor layer 4, and conversely, in the short part, a part of the high concentration p-type semiconductor layer 3 extends up to the channel p-type semiconductor layer 4.
This is a characteristic of O8 type transistors that affects the threshold voltage value. Furthermore, when performing the alignment, it is necessary to form a pattern taking into account alignment errors, resulting in an increase in cell area and a corresponding decrease in channel width.

Furthermore, since the p-type medium semiconductor layer 3 is formed by alignment using photolithography, the number of photo-etching steps is increased, which in turn impedes productivity improvement.

Furthermore, in order to improve the area utilization efficiency of the chip and obtain a long channel width, the opening pattern of the gate polycrystalline silicon film is connected to two or more enlarged portions with a large area and a narrow connection connecting the adjacent enlarged portions. The present inventor proposes a structure having a section. In such a semiconductor device, since an elongated channel region is formed along the edge of the connecting portion, the channel width can be increased, but there is a drawback that bunch-through is particularly likely to occur in this elongated channel region.

The present invention has been made in view of the above-mentioned points, and even if the width of the gate polycrystalline silicon pattern is made as equal as possible, and the overall pattern is made finer, the source electrode extraction opening can be optimized according to the current capacity. so that you can get
Furthermore, the p medium semiconductor layer 3 and the n+ type semiconductor layer 8 are formed particularly in a self-aligned manner in the source electrode extraction opening.
are electrically connected by the metal electrode film 9,
The purpose is to miniaturize the opening, and to achieve this purpose, it is possible to arrange an appropriate pattern, and to effectively form a channel region in the extra area obtained by these effects, especially in a long and narrow channel region. It is possible to prevent the bunch-through phenomenon, narrow the channel length, reduce the photo-etching process, lower the on-resistance, improve device performance such as mutual conductance, switching speed, and reduce the depth area. The purpose of the present invention is to provide a vertical semiconductor device and a method for manufacturing the same, which can reduce the number of semiconductor devices and improve productivity.

(Means for Solving the Problems) A vertical semiconductor device according to the present invention includes a semiconductor substrate of one conductivity type, and a semiconductor film or a conductive film formed on the main surface of the semiconductor substrate via a first insulating film. a first semiconductor layer formed with a high impurity concentration on the main surface of the semiconductor substrate within the opening of the pattern; and a part of the semiconductor film or conductor film pattern via the first insulating film. A second semiconductor layer of the opposite conductivity type with a low impurity concentration formed at the overlapped position, and a second semiconductor layer of the opposite conductivity type with a low impurity concentration, maintained at equal intervals along the edge or at the same position as the edge, within the opening of the semiconductor film or conductor film pattern. A third semiconductor layer of an opposite conductivity type formed at a higher impurity concentration and deeper than the second semiconductor layer, and a portion of the semiconductor film or conductive film pattern within the second semiconductor layer. a fourth semiconductor layer of one conductivity type formed so as to overlap with each other; a second insulating film formed to cover the semiconductor film or the conductor film and having an opening;
A metal electrode film is provided on the second insulating film so as to include the opening.

Further, in the manufacturing method of the present invention, ions of an opposite conductivity type are implanted at a high concentration into the main surface of a first semiconductor substrate of one conductivity type.
forming a first insulating film on the main surface of the semiconductor substrate; forming a semiconductor film or a conductive film on the first insulating film;
forming a mask thereon and then under-etching the semiconductor film or conductor film through the mask to form a semiconductor film or conductor film pattern and simultaneously forming an overhang-shaped mask; Ions of the opposite conductivity type are deeply implanted at a high concentration into the semiconductor substrate through a mask, and then, after removing the mask, ions of the opposite conductivity type are implanted at a low concentration using the semiconductor film or conductor film pattern as a mask. A step of shallowly implanting a second semiconductor layer of an opposite conductivity type and shallowly forming a third semiconductor layer of an opposite conductivity type, and implanting ions of one conductivity type using the semiconductor film or conductor film pattern as a mask. a step of forming a fourth semiconductor layer of one conductivity type in the third semiconductor layer by implanting a second semiconductor layer; a step of forming a second insulating film to cover the semiconductor film or the conductor film and the opening thereof; selectively forming an opening in a second insulating film to partially expose the first semiconductor layer and the fourth semiconductor layer; and forming a metal electrode film on the second insulating film to cover the opening. The method is characterized by comprising a step of forming.

(Function) In the semiconductor device of the present invention, since the third semiconductor layer of the opposite conductivity type has a higher impurity concentration and is formed deeper than the second semiconductor layer, miniaturization and high integration of cells are possible. At the same time, the bunch-through phenomenon can also be effectively prevented. Furthermore, by forming the second semiconductor layer and the fourth semiconductor layer shallowly, it is possible to reduce the capacitance between the gate and the source, and also to increase the mutual fundacitance m, thereby improving the switching speed. can. Further, in the semiconductor device of the present invention, the channel width can be increased within a predetermined chip area, and the gate-drain capacitance can be reduced by reducing the area occupied by the polycrystalline silicon film. Therefore, a large train current can be obtained and at the same time a high switching speed can be obtained.In particular, as in the embodiment described later, the opening of the polycrystalline silicon film pattern is formed by forming an annular portion surrounding the independent pattern portion. The annular portion has end portions located symmetrically on both sides, and a narrow connecting portion that connects these annular portions and the end portions. By arranging the parts so that they are arranged interdigitally, the utilization efficiency of the chip area is significantly increased, and the above-mentioned effects can be exhibited even more effectively.

(Example) The present invention will be specifically explained below using examples.

FIGS. 1(a) and (b) are a plan view and a cross-sectional view of an O8A MOS FET, which is an embodiment of the present invention. In FIG. 1(a), a part of the /l electrode film and insulating film are cut away. It is.

In this device, an n-type epitaxial growth layer 2 is provided on an n-type semiconductor substrate 1, and a polycrystalline silicon film (semiconductor film or A conductor film) pattern 6 is provided, and a p-type semiconductor layer (first semiconductor layer) 3 doped with impurities of opposite conductivity type at a high concentration is provided in the epitaxial layer 2 within the opening of this pattern. Further, in the epitaxial layer 2, a p-type semiconductor layer doped with impurities of the opposite conductivity type at a low concentration is located at a position partially overlapping with a part of the polycrystalline silicon film pattern 6 via the first insulating film 5a. (Second semiconductor layer) 4 is provided shallowly, and the opening of the polycrystalline silicon film pattern 6 is doped with an impurity concentration higher than that of the p-type second semiconductor layer 4 while maintaining equal intervals along the edge of this pattern. A p-type semiconductor layer (third semiconductor layer) 11 with a high
An n0 type semiconductor layer (fourth semiconductor layer) 8 is formed on the surface of the polycrystalline silicon at a position partially overlapping with a part of the conductor film pattern 6 via the first insulating film 5a. An insulating oxide film (second insulating film) 5d is formed to cover the film pattern 6, and a source/l electrode film (eleventh metal electrode film) 9a is formed on this insulating film. The source/l electrode film 9a passes through the semiconductor layers 4 and 8 through the source electrode extraction opening 110a in the cell formed in the insulating film 5d.
Ohmically connected to.

The planar shape of the open pattern of the p-con film 6 surrounded by the polycrystalline silicon film pattern 6 and formed on the surface of the n-type epitaxial layer 2 is a hexagonal enlarged portion 4A, as shown in FIG. 4B.

4C and narrow connecting portions 4D and 4E connecting adjacent sides of these three hexagonal patterns. Here, the distance β between each side of horizontally and vertically adjacent cells and the distance λ2 between each side of diagonally adjacent cells are 1, *β2. Further, the cells are arranged such that the central hexagonal enlarged portion 4B of the vertically adjacent cell is located between the hexagonal enlarged portions 4A and 4C located at opposite ends of the horizontally adjacent cells. This is a staggered delivery. In order to improve the performance of the vertical field effect transistor of this example, the gate polycrystalline silicon film pattern is modified, the channel width is lengthened, and the current capacity per unit area is increased. . This will be explained by comparing the dimensional relationship with a conventional device.

The plan view of FIG. 8(a), which is a conventional example, and the plan view of FIG. 1<8)
The same design rule is used for the magnification of the plan view, and the vertical length YL within the specified area surrounded by the broken line is 120μ
m, and the horizontal length XL is set as 160μ.

In FIG. 8(a), there are 3×4=12 source electrode extraction openings 10a, and the length of one side of one cell is Lo.
Since I (-LO2) is 20 μm, the channel width of one cell (the entire circumference of one cell) is 80 μm, and the total channel width within this broken line frame is 960 μm.

On the other hand, in FIG. 1(a), the hexagonal ends 4A, 4
The length of the straight side of B and 4C is Lo 3 C 10 μm.

45° inclined side LO4 (=J2 / 2L'0
3) The length is approximately 7 μm, and the length LOs of one side of the connecting portions 4D and 4E is 20 μm, so the channel width of one cell is approximately 244 μm, and the total channel width in the pattern area within the broken line is The width is approximately 1132 μm. As described above, the channel width of this embodiment is larger than that of the conventional one, and the difference becomes larger as the number of cells increases or as the pattern area becomes larger. .

In this way, according to this embodiment, the channel width can be significantly increased. The reason for this is that by effectively using diagonal lines,
This is because the relationship is changed to ΦJ22, which is shown in Fig. 1(a). Therefore, by arranging the cells so that they are alternately shifted by bits, it is possible to integrate the cell pattern arrangement in the center as a whole despite the same design rule, which allows for more cells than in the conventional method. It becomes possible to accumulate

Next, when miniaturization progresses, particularly when cell and gate polycrystalline silicon film patterns are downsized, conventional semiconductor devices require source electrode extraction openings at intervals of several microns. In other words, the source electrode extraction opening has the drawback of being constrained by design rules. On the other hand, this embodiment has the advantage that the interval between the source electrode extraction openings can be arbitrarily designed, and the channel width does not decrease.

From the above, in this example, an appropriate gate polycrystalline silicon film pattern is obtained so that the channel width can be increased within a defined chip area, and the cells corresponding to the openings of this gate polycrystalline silicon film pattern are It is possible to obtain a large drain current by appropriately arranging the
The optimum pattern is applied to increase the switching speed, reduce the on-resistance, reduce the chip area, and improve productivity.

Next, configure the channel region in the center of the cell pattern.
Since the p-type semiconductor layer 11, which is deeper than the p-type semiconductor layer 4, is formed in a self-aligned manner, accurate and fine cells can be formed. In order to improve switching speed and on-resistance performance, even if the channel length is narrowed as much as possible, the p-type semiconductor layer 11 is deep and close to the gate polycrystalline silicon film 6 (or channel region). Since it is formed in the center of the cell in a self-aligned manner with respect to the p-type semiconductor layer 11, the p-type semiconductor layer 11 in the channel region
14 will be formed. Therefore, p medium semiconductor 71
It is possible to prevent non-uniformity in the threshold l [pressure] due to a change in concentration in the channel region due to misalignment of the threshold voltage 11. Therefore, the bunch-through phenomenon can also be prevented, and since the p-type semiconductor layer 4 can be formed shallowly, the p-type semiconductor layer 4 partially overlaps with the gate polycrystalline silicon layer 16 formed on the extremely thin gate oxide film 5a. Since the area of the semiconductor layer 4 is small, the capacitance between the gate and the source can be reduced, and by making the Sormelo-type semiconductor layer 8 shallower along with the p-type semiconductor layer 4, the mutual fundance 9m can also be increased. It is possible. Then, the p-type semiconductor layer 4, which becomes the channel region, and the Soumero-decade semiconductor layer 8 form a shallow junction (Shal low Jun-ction).
Because of this structure, the drain current flow path (n-type epitaxial layer 2) between the channel regions is widened, and the width of the gate polycrystalline silicon film pattern can be reduced accordingly.

Therefore, in order to particularly form a long channel width, it is preferable to make the openings (cells) of the gate polycrystalline silicon film pattern narrow and form a long and narrow channel region as a long pattern arrangement. The bunch-through phenomenon can also be effectively prevented by the p-sized semiconductor layer 11 formed deeper than the p-type semiconductor layer 4.

According to the present invention, p
The type semiconductor R4 is formed in a self-aligned manner at the center of the cell directly under the Sormelo-type semiconductor layer 8 even in the elongated pattern connecting portions 4D and 4E, and prevents a decrease in breakdown voltage due to the bunch-through phenomenon. Therefore, the depletion layer is less likely to spread than in the channel region, forming a highly doped and deep p-type small semiconductor layer 11. Since this p-type semiconductor [11] is formed in a self-aligned manner, the number of photo-etching steps is reduced by one compared to the conventional one.

This is very effective for increasing productivity.

FIGS. 2(a), (b) and (C) are plan views of an O8A MOS FET which is still another embodiment of the present invention,
and a perspective cross-sectional view, in which the Aβ electrode film is cut away in FIG. 2(a), and the A1 electrode film and the second insulating film are cut away in FIG. 2(C).

In this device, an n-type epitaxy cell growth layer 2 is provided on an n-type semiconductor substrate 1, and a polycrystalline silicon film ( A semiconductor film or conductor film) pattern 6 is provided in the epitaxial layer 2 within the opening of this pattern.
A semiconductor layer) 3 is provided. Further, in the opening of the polycrystalline silicon film pattern 6, a p-type film of the opposite conductivity type is placed at a position partially overlapping with a part of the polycrystalline silicon film pattern 6 through the first insulating film 5a. A semiconductor layer (second semiconductor layer) 4 is provided in the opening of the polycrystalline silicon film pattern 6 with impurity concentration higher than that of the p-type semiconductor layer 4, with equal intervals maintained along the edge of the pattern. A high p-type semiconductor layer (third semiconductor layer) 11 is formed deeper than the ρ-type semiconductor layer 4, and is located on the surface of the second semiconductor layer 4 and
An n medium semiconductor layer (fourth half layer) 8 is formed at a position partially overlapping with a part of the semiconductor film or conductive film pattern 6 via the insulating film 5a, and the polycrystalline silicon film pattern 6 is An insulating oxide film (second insulating film>5
6 is formed, and on this insulating film, a source An electrode film (first metal electrode film) 9a and a gate Δb electrode film (second metal electrode film>9b) are formed in a stripe shape.
The J electrode film 9a is ohmically connected to the first and fourth semiconductor layers 3 and 8 through a source electrode extraction opening 10a in the cell formed in the insulating film 5d, and is connected to the second/first electrode film 9.
b is connected to the polycrystalline silicon film pattern 6 as described later through a gate metal electrode extraction opening formed in the insulator 1115d. The polycrystalline silicon film pattern 6 has a continuous lattice-like portion 6a and an independent island-like portion 6b.
The planar shape of the cell defined by these parts is an annular part 12A surrounding the independent part 6b, and two end parts 12B formed symmetrically with respect to this annular part.
and 12G, and connecting portions 12[) and 12E that connect the annular portion and these end portions.

The contour shape of the end portions 12B and 12C is a polygon that is an integral multiple of 2, in this example a quadrilateral, and the contour shape of the annular portion 12A is also a polygon that is an integral multiple of 2, which is a quadrilateral in this example. The shapes of these end portions and the annular portion are not limited to quadrangles, but may be octagonal or circular, for example.

In this example, as shown in FIG. 2(a), the annular portion 12
A plurality of cells are arranged so that the cells A are aligned, and the annular portions 12A of one row and the annular portion 12A of the adjacent row are shifted in pitch from each other, and adjacent between the sequential end portions 12B and 12C of the row. The sequential end portions 12C and 12B of the columns are arranged interdigitally to interleave. In this case, when focusing on the end portion 12B, the distances from the adjacent end portion 12C1 to the connecting portion 12E and the annular portion 12A are all approximately equal.

The second A°C electrode It! constituting the gate metal electrode! 9 b
is the gate electrode extraction opening 1 made in the second insulating film 5d.
Island-shaped independent portion 6 of polycrystalline silicon pattern via 0b
An opening 10c is connected to the second insulating JII5d at an intermediate position between the adjacent independent part and the opening 10c.
It is connected to the continuous portion 6a of the polycrystalline silicon film pattern through. That is, the continuous portion 6a and the independent portion 6b of the polycrystalline silicon film pattern are interconnected via the second AJ2 electrode film 9b. In this way, in this example, the first
The 8th β electrode film 9a and the 2nd 8th β electrode film 9b are alternately arranged in stripes with intervals of ten to twenty microns, and the first A7 electrode film 9a constituting the source Ab electrode
The width is wider than that of the second AA electrode film 9b constituting the gate metal electrode.

As described above, in this embodiment, the polycrystalline silicon film pattern 6 is configured with a mesh-like continuous portion 6a and an island-like independent portion 6b, so that the channel width is made longer than in the above-mentioned embodiment. be able to. In other words, the gate bridge structure has a continuous mesh-like part and a plurality of independent parts surrounded by this, and these parts are connected to the second AI2 electrode with excellent conductivity. !
9b is connected. On the other hand, the source electrode structure includes, at an end portion 128.12C inside the cell, a p-type semiconductor layer 3 electrically in contact with a p-type semiconductor layer 4 constituting a channel region, and an n-medium semiconductor layer constituting a source region. The layer 8 is exposed at the surface and connected to the first Aβ electrode film 9a.

These first and second A-shaped electrode films 9a and 9bG are arranged alternately in a comb shape. in this way,
In this example, the gate polycrystalline silicon pattern has a continuous mesh structure and an independent multi-structure, and the source electrode and gate electrode are formed in a comb-shape using a metal film such as AJ2 with excellent conductivity. This is its biggest feature.

Next, referring to FIGS. 3(a) to 3('), the DSAMO8FET which is an embodiment of the semiconductor device of the present invention shown in FIG.
The manufacturing method of the present invention will be explained.

First, an n-type semiconductor substrate 1 containing a high concentration of n-type impurities
An n-type epitaxial layer 2 with a concentration lower than that is formed above, and a p-type semiconductor layer 3 is formed on the main surface of this epitaxial layer.
is selectively formed, and the surface is further coated with a thickness of, for example, 500 mm.
Figure 3 (a) shows how the gate oxide film 5a is formed by polishing.
). Next, a non-doped polycrystalline silicon film 6 is formed.
is selectively patterned to a thickness of, for example, about 1,000 dolls by photo-etching technology using photoresist. At this time, the polycrystalline silicon film 6 is subjected to Freon-based isotropic dry etching using the photoresist as a mask, and the polycrystalline silicon film is under-etched to the inside of the edges of the photoresist. Form into an overhang shape.

After that, using the overhang-shaped photoresist 7 as a mask, a high concentration p-type impurity 11a is applied at a temperature of 200 to 300K.
Deep ion implantation is performed with acceleration energy of eV. This situation is shown in FIG. 3(b).

Subsequently, after removing the photoresist with oxygen plasma, heat treatment is performed at, for example, 1200°C to form a low concentration p-type impurity 4.
A is shallowly ion-implanted with an acceleration energy of 40 KeV to 70 KeV. This situation is shown in FIG. 3(C).

In this case, heat treatment is performed to form the second p-type semiconductor layer 4 and the third p-type semiconductor layer 4.
FIG. 3(d) shows how the p-type semiconductor layer 11 is formed. The p-type semiconductor layer 11 formed in this way uses the overhang of the photoresist as an implant mask, and the p-type semiconductor layer 4 uses the polycrystalline silicon film 6 as an implant mask. Compared to the vertical diffusion length, the lateral diffusion length does not spread and is short, so it does not reach the edge of polycrystalline silicon II6, but
Since the p-type semiconductor layer 4 is formed slightly beyond the edge, the narrow p-type semiconductor layer 4 is precisely formed along this edge.

Thereafter, heat treatment is performed to form a very thin oxide film 5b, and then about 5,000 layers of PSGl 15c are formed by the CVD method.
FIG. 3(e) shows the state of diffusion formation by heat treatment at .degree. In addition, in FIG. 2(b), the oxide film 5b and the PSG film 5C
These are collectively shown as an insulating film 5d. Thereafter, after forming electrode extraction openings 10a and 10b in each region, A°C metal films 9a and 9b having a thickness of, for example, approximately 4 μm are formed to complete the semiconductor device, as shown in FIG. 3(f).
”).

In this embodiment, the depth of the p-type first semiconductor layer 3 is set to 1
0 μm, and the depth of the p-type 2 semiconductor layer 4 is 0.5 to 1 μm.
m, and the depth of the p-type third semiconductor layer 11 is set to 1 to 2 μm.

In this embodiment, as shown in FIG. 3(b), after the p+ type ions 3a are implanted, the polycrystalline silicon film 6 may be etched to set back the pattern edge of the polycrystalline silicon film.

FIG. 4 shows still another embodiment according to the present invention.
FIG. 4(a) is a plan view, and FIG. 4(b) is a cross-sectional view taken along the line A--A. FIG. 4(a) shows the A.degree. C. electrode film completely removed. In order to keep the gate polycrystalline silicon film pattern width constant, the channel width is made longer by using diagonal lines in the cell shape and integrating many cells. Therefore, this structure has the longest channel width in terms of pattern area per unit area. In this embodiment, the same parts as in the previous example are denoted by the same reference numerals. In this example, the planar shape of the cell surrounded by the continuous portion 6a of the polycrystalline silicon film pattern is an approximately hexagonal annular portion 12A, and end portions 12A, which are also approximately hexagonal, and are arranged symmetrically on both sides of the annular portion 12A.
B, 12C, and a narrow connecting portion 12D that connects the annular portion and these end portions.

The only difference from the embodiment shown in FIG. 2 is that it is constructed from 12E, and the other constructions are the same, so no further explanation will be given.

5 to 7 show the planar shape of a pattern of an n-type semiconductor layer 4 surrounded by a polycrystalline silicon film pattern 6 in still another embodiment of the semiconductor device of the present invention. In the embodiment shown in FIG. 5, hexagonal end portions 4F and 4G
The connecting parts are connected by 4 narrow connecting parts, which are arranged at different pitches. Further, in the embodiment shown in FIG. 6, the hexagonal end portions 4I and 4J are connected to each other by a narrow connecting portion 4, and the hexagonal end portions 4I and 4J are arranged in a staggered manner. Further, in the embodiment shown in FIG. 7, the rectangular end portions 4L and 4M are connected by a narrow connecting portion 4N, and are arranged at different pitches. These, the fifth
In the embodiments shown in FIGS. 7 to 7 as well, the p-type third semiconductor layer 11 with a high impurity concentration forms the p-type second semiconductor layer 4 in a self-aligned manner.
It is formed deeper than the Furthermore, since the spacing between adjacent cells is approximately equal to each other, a long channel width can be obtained within a limited area.

The present invention is not limited to the embodiments described above, but can be modified and modified in many ways.

For example, in the above-described embodiment, the gate electrode material was polycrystalline silicon, but it is not limited to this, and may include Mo, Ni, etc.
, Ti, Cr, etc., or high melting point metals such as -E 1,1 butene silicide, nickel silicide, and platinum silicide. Further, the conductivity types of the n-type semiconductor layer and the n-type semiconductor layer may be opposite. Furthermore, in the above example, among the vertical field effect transistors, especially the DSA MO
Although an 8-type semiconductor device is used, the present invention is not limited to this, and the gate polycrystalline silicon film pattern may be used as the emitter and the cell pattern as the base, or vice versa, the gate polycrystalline silicon film pattern may be used as the base and the cell pattern may be used as the emitter. It can also be applied to bipolar semiconductor devices. Furthermore, in the above embodiment, DSA-MOS F
ET, but for example, V-groove or U-groove MO8FET
It can also be applied to In this case, the channel region can be formed by forming a V-groove or a groove in the polycrystalline silicon film pattern itself or its edge portion. Further, in the embodiments described above, a power transistor is used, but a high frequency transistor or a power switching transistor may also be used. Particularly in high voltage transistors, field limiting rings can be formed according to the present invention.
It is also applicable to IT (static induction transistor).

(Effects of the Invention) As described above, the effects of the present invention can be summarized as follows: Not only can the channel width be made longer and the on-resistance lower (but also the punch resistance can be reduced even if the channel length is narrowed).
A high breakdown voltage between the source and drain can be obtained without reducing throughput, and the capacitance between the source and gate can be reduced by forming the channel n-type semiconductor layer and the source n-type semiconductor layer shallowly. As a result, the pattern width of the gate polycrystalline silicon film can be reduced.
Along with this, since the area of the gate polycrystalline silicon film is reduced, the capacitance between the gate and the drain can also be reduced.

Therefore, since the channel area is narrow, the transconductance m is large, which in turn makes it possible to improve the switching speed.
type transistors can be provided by a highly productive manufacturing method.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are a plan view and a sectional view showing the structure of an embodiment of a vertical semiconductor device according to the present invention, and FIGS. 2(a) and (c) are vertical semiconductor devices according to the present invention. A plan view, a cross-sectional view, and a perspective cross-sectional view showing the structure of another embodiment of the semiconductor device, and FIGS. 4(a) and 4(b) are plan views and sectional views showing the structure of still other embodiments, and FIGS. 5 to 7 show modified examples of the cell pattern. 8(a) and 8(b) are a plan view and a sectional view showing the structure of a conventional vertical field effect transistor, and FIG. 9(a)
) to (f) are sectional views showing the structure in the same sequential manufacturing process, and FIGS. 10(a) and 10(b) are a plan view and a sectional view showing the structure of other examples of conventional vertical field effect transistors. be. 1... Mouth + type semiconductor substrate 2... N type epitaxial layer 3... P skew type semiconductor layer (first semiconductor layer) 4... P type semiconductor layer (second semiconductor layer) 5a... First insulating film
5d...Second insulating film 6...Polycrystalline silicon film 6
a...Continuous portion 6b...Independent portion 8...N native semiconductor layer (fourth semiconductor layer) 9a...First Affi electrode film 9b...Second A° C. electrode film 10a
, 10b, 10c -=-opening 11...p
Skewer-shaped semiconductor layer (third semiconductor M) 12A... annular portion
12B, 12C... end portions 12D, 12E
...Connection parts 4A to 40.4F, 4G, 41.4J, 41°4M...
- Enlarged portions 4D, 4E, 41-1. 4, 4N...
・Connection part Fig. 9(a) Fig. 9(d) (e)

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, a semiconductor film or conductive film pattern formed on the main surface of the semiconductor substrate via a first insulating film, and within an opening of this pattern, A first semiconductor layer formed with a high impurity concentration on the main surface of the semiconductor substrate, and a low impurity concentration layer formed at a position where a portion of the semiconductor film or conductor film pattern partially overlaps with the first insulating film interposed therebetween. a second semiconductor layer of opposite conductivity type and the opening of the semiconductor film or conductor film pattern, maintaining equal intervals along the edge thereof or until reaching the same position as the edge;
A third semiconductor layer of an opposite conductivity type formed with a higher impurity concentration and deeper than the second semiconductor layer, and a third semiconductor layer formed in the second semiconductor layer so as to partially overlap with a part of the semiconductor film or conductor film pattern. a fourth semiconductor layer of one conductivity type; a second insulating film formed to cover the semiconductor film or the conductor film and having an opening; 1. A vertical semiconductor device comprising: a metal electrode film formed on a metal electrode film; 2. The planar shape of the fourth semiconductor layer surrounded by the semiconductor film or the conductor film pattern is formed into a polygonal or circular enlarged portion that is an integral multiple of 2 and a narrow width that connects adjacent enlarged portions. 2. The vertical semiconductor device according to claim 1, further comprising a connecting portion. 3. The vertical semiconductor device according to claim 2, wherein the expanded portion of the fourth semiconductor layer has an octagonal shape, and opposing sides of two or more adjacent expanded portions are connected by a connecting portion. 4. The semiconductor film or conductor film pattern has a mutually continuous pattern portion and an independent pattern portion located within the pattern opening, and these continuous pattern portions and independent pattern portions are connected via the metal electrode film. Claim 1, 2 or 3 characterized in that the invention is interconnected with each other.
The vertical semiconductor device described above. 5. Forming a first semiconductor layer by implanting ions of the opposite conductivity type at a high concentration into the main surface of a first semiconductor substrate of one conductivity type; and forming a first insulating film on the main surface of the semiconductor substrate. A step of forming a semiconductor film or a conductor film on the first insulating film, forming a mask thereon, and then under-etching the semiconductor film or conductor film through this mask to form a semiconductor film or a conductor film. A process of forming an overhang-like mask at the same time as forming a conductor film pattern, and deeply implanting ions of the opposite conductivity type into the semiconductor substrate at a high concentration through the overhang-like mask.
Next, after removing the mask, ions of the opposite conductivity type are shallowly implanted at a low concentration using the semiconductor film or conductor film pattern as a mask to form a deep second semiconductor layer of the opposite conductivity type, and a second semiconductor layer of the opposite conductivity type is implanted deeply. a step of forming a shallow third semiconductor layer; and a step of implanting ions of one conductivity type using the semiconductor film or conductor film pattern as a mask to form a fourth semiconductor layer of one conductivity type in the third semiconductor layer. , a step of forming a second insulating film to cover the semiconductor film or conductor film and the opening thereof;
selectively forming an opening in an insulating film to partially expose the first semiconductor layer and the fourth semiconductor layer; and forming a metal electrode film on the second insulating film to cover the opening. A method for manufacturing a vertical semiconductor device, comprising the steps of: