JP4894097B2

JP4894097B2 - Semiconductor device

Info

Publication number: JP4894097B2
Application number: JP2001194631A
Authority: JP
Inventors: 信一神保
Original assignee: Fuji Electric Co Ltd
Current assignee: Fuji Electric Co Ltd
Priority date: 2001-06-27
Filing date: 2001-06-27
Publication date: 2012-03-07
Anticipated expiration: 2021-06-27
Also published as: JP2003008009A

Description

【０００１】
【発明の属する技術分野】
この発明はプレーナ型の横型および縦型の半導体装置に関し、特にその半導体装置の耐圧構造に関する。
【０００２】
【従来の技術】
バイポーラトランジスタ、パワーＭＯＳＦＥＴおよびＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）に代表されるパワーデバイスにおいては、数十から数千Ｖの耐圧構造（耐圧をもつ箇所の構造）が必要とされる。また、これらのパワーデバイスを駆動するために、近年、高耐圧ＩＣの開発が盛んに行われ、この高耐圧ＩＣもまたパワーデバイスと同等の耐圧が要求される。
【０００３】
図１５は、ＤｏｕｂｌｅＲＥＳＵＲＦ構造と抵抗性フィールドプレート構造を組み合わせた構造の要部断面図である。この耐圧構造は、高耐圧ＩＣの代表的な構造である。
図１５において、ｐ基板１０１の表面層にＮｗｅｌｌ領域１０２が設けられている。このＮｗｅｌｌ領域１０２の表面層にｎ型の高電位領域１０３、ｐ型の低電位領域１０４、およびＰｏｆｆｓｅｔ領域１０５がそれぞれ形成されている。高電位領域１０３上と、低電位領域１０４上には、高電位側電極１０６と低電位側電極１０７がそれぞれ形成され、ｐ基板１０１上に形成される絶縁酸化膜１０８上に高比抵抗の抵抗性フィールドプレートである薄膜抵抗層１０９が形成され、この薄膜抵抗層１０９により高電位側電極１０６と低電位側電極１０７とが電気的に接続されている。また、低電位側電極１０７と裏面側電極１１０は、ｐ基板１０１の終端部で電気的に接続している。
【０００４】
図１６は、半導体内部の空乏層の拡がりを示した図である。図１６の空乏層の拡がりを示した半導体装置の要部断面図は、図１５（ａ）の要部断面図と同一である。従って、図中の符号は図１５（ａ）と同じである。
図１６において、低電位側電極１０７と裏面側電極１１０を基準にして、高電位側電極１０６に正電位ＶＳが印加されると、逆バイアスが印加される２つのｐｎ接合から空乏層１１１、１１２が拡張していく。
【０００５】
１つのｐｎ接合は、Ｎｗｅｌｌ領域１０２とＰｏｆｆｓｅｔ領域１０５、低電位領域１０４のｐｎ接合であり、もう一つのｐｎ接合は、Ｎｗｅｌｌ領域１０２とｐ基板１０１のｐｎ接合である。
一般的に、絶縁酸化膜１０８と半導体界面の固定電荷の影響で、半導体表面の空乏層内部には電界の集中が起き易く、これがデバイスの破壊につながる。
【０００６】
抵抗性フィールドプレート構造では、高電位側電極１０６に電位Ｖｓを印加すると、薄膜抵抗層１０９にも電位Ｖｓが印加され、薄膜抵抗層１０９には電位Ｖｓと薄膜抵抗層１０９の抵抗値に応じた電流が流れる。これによって、薄膜抵抗層１０９に、均一な電位分布が生じれば、この電位分布による電界が、絶縁酸化膜１０８を介し、半導体層に影響を及ぼし、半導体層表面の空乏層の中の電界集中を緩和することができる。その結果、高い耐圧を安定して確保することができる。
【０００７】
従来の構造においては、高電位領域１０３と低電位領域１０４との間に大きな漏れ電流が発生しないように、フィールドプレートである薄膜抵抗層１０９には、数ＭΩｃｍの高比抵抗の層、例えば、ノンドープアモルファスシリコンやＳＩＰＯＳ（Ｓｅｍｉ−ＩｎｓｕｌａｔｉｎｇＰｏｌｙｃｒｙｓｔａｌｌｉｎｅＳｉｌｉｃｏｎ）が使用されてきた。
【０００８】
しかしながら、数ＭΩｃｍの高比抵抗の層を安定して形成することは、この層に入り込む不純物を極めて小さく抑制しなければならず、製造は極めて困難である。また、場所による比抵抗の値にばらつきが発生しやすい。
この薄膜抵抗層１０９の抵抗値が低い場合には、抵抗値のばらつきは小さくなるが、大きな漏れ電流が流れるため、発生損失が大きくなり、デバイスが破壊しやすくなる。また、抵抗値が高すぎる場合は、抵抗値のばらつきが発生して、漏れ電流は不均一に流れ易くなり、高電位領域１０３と低電位領域１０４の間に、均一な電位分布を形成することが困難となり、半導体層の空乏層中に電界集中箇所が生じて、耐圧が低下する可能性がある。
【０００９】
これらの問題点を解決するために、前記の薄膜抵抗層１０９の抵抗値を低くして、ばらつきを抑えた、図１７のような構造が、特許第３１１７０２３号に開示されている。この構造では、前記の薄膜抵抗層を島状のベース電極１１３（高電位側電極）とそれを取り囲む外周電極１１４（低電位側電極）との間に、渦巻き状に形成し、長い薄膜抵抗層（渦巻き状の薄膜抵抗層１１５）でベース電極１１３と外周電極１１４を接続することで、抵抗値を増大させている。
【００１０】
この構造では、渦巻き状の薄膜抵抗層１１５の比抵抗を小さくして、ばらつきを抑制し、渦巻き状の薄膜抵抗層１１５の端から端の間の抵抗値を大きくして漏れ電流を抑制している。また、ベース電極１１３と外周電極１１４とを直線で結ぶ線上の電位分布は、渦巻き状の薄膜抵抗層１１５の渦巻きの回数分だけ、階段状に変化するが、回数を多くすれば、階段の落差は小さくなり、平均的な電位勾配は一定となる。
【００１１】
この構造によれば、ベース電極１１３と外周電極１１４を電気的に接続する渦巻き状の薄膜抵抗層１１５の比抵抗の値を従来構造の抵抗性フィールドプレートに比べ、低い値として実現できるというものである。これによって、抵抗性フィールドプレートよりも抵抗値の制御が容易になる利点を有する。
【００１２】
【発明が解決しようとする課題】
しかし、図１７のような構造に対し、この渦巻き状の薄膜抵抗層１１５を、ＵＳＰ６１２４６２８に開示される高耐圧ＩＣの耐圧構造部に適用すると、この耐圧構造は、図１８に示すように、形状が複雑で、１周分の周囲長が４〜１０ｍｍ程度と長くなる。周囲長さが長くなると、高電位側電極に高電圧を印加したとき、耐圧が不安定に成りやすく、安定した耐圧を得るには、渦巻き状の薄膜抵抗層を複数本巻くなどのレイアウト上の困難さがある。
【００１３】
これは、耐圧構造部の平面的形状が複雑なため、電界が集中しないように渦巻き状の薄膜抵抗層を、ベース電極から外周電極まで、ベース電極と渦巻き状薄膜抵抗層の距離を少しづづ変えながら配置するのが難しいことが原因である。
また、チップサイズが異なると、周囲長が異なるため同じ耐圧を持つデバイスでも耐圧構造部に巻く、渦巻き状の薄膜抵抗層の形状もしくは抵抗値を調整する必要があり、これは、縦型デバイスで同一耐圧系列を持つシリーズで、異なる電流容量を持つデバイスを設計する場合に、耐圧構造をその都度設計しなければならず、不都合である。
【００１４】
この発明の目的は、前記の課題を解決して、電界集中が発生しにくく、複雑な平面パターンにも容易に対応できる耐圧構造を有する半導体装置を提供することにある。
【００１５】
【課題を解決するための手段】
前記の目的を達成するために、半導体基板上に形成された絶縁膜上に、互いに離して形成された第１電極と第２電極とを有する半導体装置であって、該第１電極を取り囲むように、該第１電極と前記第２電極の間の前記絶縁膜上に、複数本形成される金属膜からなるループ状導電膜層と、前記第１電極と該ループ状導電膜層の間、該ループ状導電膜層の相互間、該ループ状導電膜層と前記第２電極の間とをそれぞれ互いに電気的に接続する薄膜抵抗層と、を有し、
前記ループ状導電膜層と前記薄膜抵抗層とによりフィールドプレートを構成しており、
前記薄膜抵抗層のシート抵抗値が、１×１０ ^４ Ω／□以上５×１０ ^４ Ω／□以下であり、
所定の幅を有する前記薄膜抵抗層を、前記ループ状導電膜層の長手方向に対して、垂直でなく、斜めに配置して、前記接続を行う構成とする。
【００１６】
また、前記半導体基板上に形成された第１絶縁膜と、該第１絶縁膜上に形成される第２絶縁膜と、該第２絶縁膜上に、互いに離して形成された前記第１電極と前記第２電極と、該第１電極を取り囲むように、該第１電極と前記第２電極の間の前記第２絶縁膜上に、複数本形成される金属膜からなるループ状導電膜層と、前記第１電極と該ループ状導電膜層の間、該ループ状導電膜層の相互間、該ループ状導電膜層と前記第２電極の間とをそれぞれ互いに電気的に接続し、前記第１絶縁膜に接して前記第１絶縁膜上に形成される薄膜抵抗層と、を有し、
前記ループ状導電膜層と前記薄膜抵抗層とによりフィールドプレートを構成しており、
前記薄膜抵抗層のシート抵抗値が、１×１０ ^４ Ω／□以上５×１０ ^４ Ω／□以下であり、
所定の幅を有する前記薄膜抵抗層を、前記ループ状導電膜層の長手方向に対して、垂直でなく、斜めに配置して、前記接続を行う構成とする。
【００１７】
また、前記ループ状導電膜層下の前記第２絶縁膜に開口が形成され、前記開口が形成された領域において、前記ループ状導電膜層の底部が、前記薄膜抵抗層と離して、前記第１絶縁膜と接するとよい。
また、前記薄膜抵抗層が、ポリシリコンで形成されるとよい。
【００１８】
また、前記半導体基板が第１導電型であって、該半導体基板の表面層に第１導電型の第１領域と第２導電型の第２領域が離して形成され、前記第１領域と前記第２領域の間の前記半導体基板の表面層に、前記第１領域から離し、且つ、前記第２領域に接するように第２導電型のオフセット領域が形成され、前記第１領域と前記第１電極とが接続し、前記第２領域と前記第２電極とが接続する構成とする。
【００１９】
また、前記半導体基板が第１導電型であって、該半導体基板の表面層に第２導電型の第１領域と第２領域が離してそれぞれ形成され、前記第１領域と前記第２領域の間の前記半導体基板の表面層に前記第１領域と前記第２領域から離して、第２導電型のガードリング領域が、前記第１領域を取り囲むようにループ状に形成され、前記第１領域と前記第１電極とが接続し、前記第２領域と前記第２電極とが接続する構成とする。
【００２０】
前記したように、第１電極と第２電極との間に第１電極を取り囲むように、ループ状導電膜層を複数本形成し、第１電極と最内周のループ状導電膜層、ループ状導電膜層同士、最外周の導電膜層と第２電極をそれぞれ薄膜抵抗層で電気的に接続することにより、各ループ状導電膜層には、第１電極の電位と第２電極の電位の中間の電位が段階的に存在することになり、上記各ループ状導電膜層の段階的な電位分布の影響で、その下に絶縁膜を介して存在する半導体基板の電位も均一にすることができる。
【００２１】
これによって、これまで複雑な形状ではレイアウトが困難であった、渦巻き状の薄膜抵抗層のみの構造に比べ、半導体装置の高耐圧化が容易に実現できる。
また、同一耐圧を持つデバイスで、チップサイズが異なる場合でも、ループ状の導電膜層の形状およびシート抵抗値は変更しなくても良いことが多く、設計が容易になる。
【００２２】
【発明の実施の形態】
図１から図５は、この発明の第１実施例の半導体装置であり、図１（ａ）は要部平面図、図１（ｂ）は、図１（ａ）のＡ部の拡大平面図、図２は、図１（ｂ）のＸ−Ｘ線で切断した要部断面図、図３は、図１（ｂ）のＹ−Ｙ線で切断した要部断面図、図４は、図１（ｂ）のＺ−Ｚ線で切断した要部断面図、図５は、図１（ｂ）のＭ−Ｍ線で切断した要部断面図である。この半導体装置はＤｏｕｂｌｅＲＥＳＵＲＦ構造の高耐圧ＩＣを例として挙げた。
【００２３】
図１から図５において、高電位側領域７１を囲むように低電位側領域７３が形成されており、その間の耐圧構造部７２にメタル層３、４、５、６がそれぞれループ状に形成されている。７４、７５は高耐圧ＭＯＳＦＥＴのゲート・ソース電極とドレイン電極である。高電位側領域７１とメタル層３、メタル層３とメタル層４、メタル層４とメタル層５、メタル層５とメタル層６およびメタル層６と低電位側領域は、薄膜抵抗層７、８、９、１０、１１によりそれぞれ電気的に接続されている（図１（ａ））。つぎに、薄膜抵抗層７、８、９、１０、１１の構成について説明する。
【００２４】
ｐ基板２１の表面層にＮｗｅｌｌ領域２２が設けられ、Ｎｗｅｌｌ領域２２の表面層にｎ型の高電位領域７１（ｎ領域２３）、ｐ型の低電位側領域７３（ｐ領域２４）、およびＰｏｆｆｓｅｔ領域２６がそれぞれ形成され、高電位側領域７１上と、低電位側領域７３上には、高電位側電極１と低電位側電極２がそれぞれ形成され、ｐ基板２１上に選択酸化膜２７が形成されている。この選択酸化膜２７上に薄膜抵抗層７、８、９、１０、１１が形成され、この上に層間絶縁膜１３を介してループ状のメタル層３、４、５、６が形成され、高電位側電極１と最内周のメタル層３、メタル層３とメタル層４、メタル層４とメタル層５、メタル層５とメタル層６、および最外周のメタル層６と低電位側電極２は、薄膜抵抗層７、８、９、１０、１１によってそれぞれ電気的に接続され（図２、図４）、低電位側電極２と裏面側電極３８は、図示しないｐ基板２１の終端部で電気的に接続している。
【００２５】
尚、図中の２３はｎ領域、２４、２５はｐ領域、２８は選択酸化膜、２９はコンタクトをとるためのｎ⁺領域、３１〜３７はコンタクトをとるためのｐ⁺領域、１２はメタル層と薄膜抵抗層とを接続するコンタクトホールである。
図６は、図１の半導体装置の要部断面図と電位分布を示し、同図（ａ）は図２の要部断面図で、同図（ｂ）は同図（ａ）のループ状のメタル層の電位分布を示す図である。
【００２６】
図６（ｂ）は、高電位側電極１、メタル層３、４、５、６、および低電位側電極２の電位分布を、横軸を高電位側電極１からの変位量としてグラフにしたものである。
図のように、メタル層が４本の場合の電位分布では、各メタル層の電位差が大きい。しかし、実際には、この高電位側電極１と低電位側電極２の間隔は、１４００Ｖクラスの高耐圧ＩＣでは、１５０〜２００μｍ程度あり、例えば、メタル層３、４、５、６の幅を８μｍ、メタル層の間隔を４μｍとすれば、１２〜１６本程度のメタル層を形成することができ、このメタル層の数を多くするほど、高電位側電極１から低電位側電極２までの階段状の電位差（ステップ）を小さくすることができ、それによって電界の集中を小さくし、耐圧を高めることができる。このメタル層の数はメタル層の幅と間隔を小さくすることで、増やすことができる。
【００２７】
つぎに薄膜抵抗層７、８、９、１０、１１のシート抵抗値について説明する。前記薄膜抵抗層７、８、９、１０、１１は、たとえば膜厚０．４〜１μｍ程度のポリシリコンで形成できる。薄膜抵抗層７、８、９、１０、１１の幅を２μｍ程度に細くし、ループ状のメタル層３、４、５、６の長手方向に対して、垂直でなく、斜めに配置することで、薄膜抵抗層７、８、９、１０、１１の長さを長くすることができる。薄膜抵抗層７、８、９、１０、１１の長さを長くすることによって、薄膜抵抗層７、８、９、１０、１１のシート抵抗値を制御し易いレベルまで下げることが可能である。
【００２８】
例として、図１の構造において、１４００Ｖを高電位側電極に印加した場合について説明する。薄膜抵抗層７、８、９、１０、１１を通じて１０μＡ程度の漏れ電流にする場合、抵抗値は、１４００Ｖ／１０μＡ＝１．４×１０⁸ Ω＝１４０ＭΩである。薄膜抵抗層７、８、９、１０、１１は５本直列に接続しているので、薄膜抵抗層１本あたりでは、１４０ＭΩ÷５＝２８ＭΩである。
【００２９】
薄膜抵抗層１本の長さを１．５ｍｍ、幅を２μｍとして、薄膜抵抗層のシート抵抗値は、２８ＭΩ×２÷１５００＝３．７３×１０⁴ Ω／□＝３７．３ｋΩ／□
また、メタル層の本数が１３本で、薄膜抵抗層の本数が１４とすると、薄膜抵抗層１本あたりの抵抗値は、１４０ＭΩ÷１４＝１０ＭΩである。
【００３０】
薄膜抵抗層１本の長さを１．５ｍｍ、幅を２μｍと仮定すると、薄膜抵抗層のシート抵抗値は、１０ＭΩ×２÷１５００＝１．３３×１０⁴Ω／□＝１３．３ｋΩ／□となる。
このように、本発明の耐圧構造では、電圧を保持するポリシリコンのシート抵抗値は、メタル層の本数を増やすことで、実現が容易なレベルに低下させることができる。
【００３１】
しかし、メタル層の本数を増加させると、メタル層と接続する薄膜抵抗層の幅が狭くなり、薄膜抵抗層の加工が困難となり、また、シート抵抗値を大幅に低下させることが必要となる。そのため、実用的な薄膜抵抗層のシート抵抗値としては、１０ｋΩ／□以上で、５０ｋΩ／□以下である。５０ｋΩ／□を超えると、薄膜抵抗層内でのシート抵抗値のばらつきが大きくなり、実用的でない。
【００３２】
このシート抵抗値の範囲は、イオン注入法などで、十分に不純物濃度を確保できる範囲である。
このように、メタル層３、４、５、６と薄膜抵抗層７、８、９、１０、１１を組み合わせた第１実施例の耐圧構造を採用すると、数ＭΩ／□の高いシート抵抗値を必要とせず、また、高耐圧ＩＣのように複雑かつ周囲長の長い半導体装置においても、レイアウトと抵抗値設定を容易にし、半導体装置の高耐圧化を達成できる。
【００３３】
また、耐圧クラスが同一で、電流容量が異なる場合は、薄膜抵抗層のシート抵抗値を変更する必要がないために、耐圧構造の設計が容易になる。
図７から図１２は、第１実施例の半導体装置の製造方法であり、工程順に示した要部製造工程図である。この要部製造工程図は、図２の要部断面図に相当した図である。
【００３４】
まず、ｐ基板２１に、ｎ領域２２、２３、ｐ領域２４、２５、Ｐｏｆｆｓｅｔ領域２６、をイオン注入と熱拡散により形成し、次に、選択酸化膜２７、２８を形成する（図７）。
次に、図示しない箇所にゲート酸化膜を形成する。このゲート酸化膜は、ゲート形成箇所以外の箇所にも酸化膜４１が形成される。この酸化膜４１上と選択酸化膜２７上にポリシリコン４２を成膜し、前記薄膜抵抗層７、８、９、１０、１１になるの部分のポリシリコン４２の抵抗値を制御するために、ＢもしくはＢの化合物（ＢＦ₂など）のイオンを注入４３を行う。このドーズ量は、先ほど述べたようにポリシリコン４２のシート抵抗値が約１０から５０ｋΩ／□程度になるように決める（図８）。
【００３５】
次に、ポリシリコン４２を通常の露光、エッチング技術により、パターニングして、薄膜抵抗層７、８、９、１０、１１を形成する（図９）。
次に、フォトレジスト４４を被覆し、露光、エッチング技術による、選択的なＡｓのイオン注入４５を行うことにより、ｎ領域２３の表面層に、後述のメタル層とのコンタクトをとるためのｎ⁺領域２９を形成する（図１０）。
【００３６】
次に、前記のフォトレジスト４４を除去し、新たにフォトレジスト４６を被覆し、露光、エッチング技術による、選択的なＢＦ₂イオンのイオン注入４７を行うことにより、ポリシリコンで形成された薄膜抵抗層７、８、９、１０、１１の表面層に、後述のメタル層とのコンタクトをとるためのｐ⁺領域３１、３２、３３、３４、３５を形成し、ｐ領域２４、２５の表面層に、後述のメタル層とのコンタクトをとるためのｐ⁺領域３６、３７を形成する（図１１）。これらの領域は酸化膜４１をスクリーン酸化膜として利用して形成しているが、これらの領域を形成する前に酸化膜４１を除去し、熱酸化膜を形成し直すこともできる。
【００３７】
次に、ＰＳＧ（リンガラス膜）などの層間絶縁膜１３、１４を、形成したのち、露光、エッチング技術により、高電位側電極１、メタル層３、４、５、６および低電位側電極２とのコンタクトをとるためのコンタクトホールを形成し、Ａｌなどのメタルを全面にスパッタし、露光、エッチング技術により、パターニングを行ない、高電位側電極１、メタル層３、４、５、６および低電位側電極２を形成する（図１２）。
【００３８】
さらに、図示しない、表面のパッシベーション膜を形成、パターニングして完了する。
前記の第１実施例は、横型のプレーナ型半導体装置の耐圧構造について説明したが、つぎの実施例で説明する縦型の半導体装置の場合で、チップの活性領域から横方向に空乏層が拡張していくタイプでは、第１実施例で使用した薄膜抵抗層とループ状のメタル層（導電膜層）で、高電位側電極と低電位側電極を接続する方法は非常に有効である。
【００３９】
図１３は、この発明の第２実施例の半導体装置であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＭ−Ｍ線で切断した要部断面図である。第１実施例との違いは、図５のループ状のメタル層３、４、５、６下の層間絶縁膜１３を開口して、選択酸化膜２７上に達するように、メタル層に凸部４８を設けた点である。こうすることで、ループ状のメタル層３、４、５、６の電位を、層間絶縁膜１３を介すことなく、選択酸化膜２７下の半導体面に有効に伝えることができる。メタル層３、４、５、６の電位が半導体面に有効に反映されることで、第１実施例の半導体装置より、局部的な電界集中が起こり難くくなり、安定して高耐圧を確保することができる。
【００４０】
図１４は、この発明の第３実施例の半導体装置の要部断面図である。この半導体装置の耐圧構造は、プレーナ構造で、縦型デバイスおよび横型デバイスの周辺耐圧構造によく使用されるガードリング構造と組み合わせた例である。この図は耐圧構造部の要部断面図を示す。
ｎ層５１の裏面側にｎ⁺層５２を形成し、表面側に低電位領域５３となるｐウェル領域、この低電位領域５３を取り囲むようにガードリングとなるｐ領域５４、５５、５６、５７をそれぞれ形成し、チップの終端部には、高電位領域５８となるｐ領域を形成する。低電位領域５３となるｐウェル領域には、図示しない活性領域（例えば、ＭＯＳＦＥＴでいうとゲート部やソース部が占めている領域のこと）が形成される。低電位領域５３上に低電位側電極５９、高電位領域５８上に電極膜６０が形成される。高電位電極となる裏面側電極６１と電極膜６０はダイシング面６２で電気的に接続されている。
【００４１】
酸化膜６３上に薄膜抵抗層７、８、９、１０、１１が形成され、この上に層間絶縁膜１３を介してループ状のメタル層３、４、５、６が形成され、電極膜６０と最内周のメタル層３、メタル層３とメタル層４、メタル層４とメタル層５、メタル層５とメタル層６、および最外周のメタル層６と低電位側電極５９は、薄膜抵抗層７、８、９、１０、１１によってそれぞれ電気的に接続される。
【００４２】
ここで、高電位側電極である裏面側電極６１に電位Ｖｓを印加すると、低電位側電極５９と電極膜６０の間に電位Ｖｓがかかり、薄膜抵抗層７、８、９、１０、１１には、漏れ電流が流れて、ループ状のメタル層３、４、５、６には、均一な電位分布が形成され、この電位分布による電界が、半導体中の空乏層における電界集中を緩和し、耐圧を保持させる。図では、ガードリング上にループ状のメタル層３、４、５、６が配置されているが、必ずしも、ガードリング上に配置する必要はない。
【００４３】
【発明の効果】
この発明によれば、半導体基板上の高電位領域と低電位領域に電気的に接続する第１電極と第２電極を設けて、第１電極の周囲の第１電極と第２電極の間に、複数本のループ状導電膜層を形成し、薄膜抵抗層で第１電極とループ状導電膜層の間、ループ状導電膜層の相互間、ループ状導電膜層と第２電極の間を電気的に接続することによって、
第１電極と第２電極の間に、電圧を印加すると、ループ状導電膜層には、第１電極と第２電極の間の電位分布を、高い電位から低い電位へ、細かい階段状で直線的低下させることができるため、半導体基板内部にも均一な電位分布が形成され、電界集中が起きにくく、耐圧の高い半導体装置とすることができる。
【００４４】
また、薄膜抵抗層の形状を、１本あたりの長さを長く、また細くして抵抗値を高めることによって、薄膜抵抗層自体のシート抵抗値を制御し易い低抵抗レベルにすることが可能である。
また、高耐圧ＩＣのように耐圧構造の形状が複雑で、周囲長の長い半導体装置においても、薄膜抵抗層とループ状導電膜層を組み合わせることで、耐圧構造を容易に設計することができる。
【００４５】
また同一耐圧で周囲長が異なる素子を設計する場合にも、薄膜抵抗層の幅や長さを変更することなしに耐圧構造の設計ができる。
【図面の簡単な説明】
【図１】この発明の第１実施例の半導体装置であり、（ａ）は要部平面図、（ｂ）は、（ａ）のＡ部の拡大平面図
【図２】この発明の第１実施例の半導体装置であり、図１（ｂ）のＸ−Ｘ線で切断した要部断面図
【図３】この発明の第１実施例の半導体装置であり、図１（ｂ）のＹ−Ｙ線で切断した要部断面図
【図４】この発明の第１実施例の半導体装置であり、図１（ｂ）のＺ−Ｚ線で切断した要部断面図
【図５】この発明の第１実施例の半導体装置であり、図１（ｂ）のＭ−Ｍ線で切断した要部断面図
【図６】図１の半導体装置の要部断面図と電位分布を示し、（ａ）は図２の要部断面図、（ｂ）は（ａ）のループ状のメタル層の電位分布を示す図
【図７】第１実施例の半導体装置の要部製造工程図
【図８】図７に続く、第１実施例の半導体装置の要部製造工程図
【図９】図８に続く、第１実施例の半導体装置の要部製造工程図
【図１０】図９に続く、第１実施例の半導体装置の要部製造工程図
【図１１】図１０に続く、第１実施例の半導体装置の要部製造工程図
【図１２】図１１に続く、第１実施例の半導体装置の要部製造工程図
【図１３】この発明の第２実施例の半導体装置であり、（ａ）は要部平面図、（ｂ）は、（ａ）のＭ−Ｍ線で切断した要部断面図
【図１４】この発明の第３実施例の半導体装置の要部断面図
【図１５】ＤｏｕｂｌｅＲＥＳＵＲＦ構造と抵抗性フィールドプレート構造を組み合わせた構造の要部断面図
【図１６】半導体内部の空乏層の拡がりを示した図
【図１７】特許第３１１７０２３号に開示されている渦巻き状の薄膜抵抗層を有する半導体装置
【図１８】複雑な平面パターンの耐圧構造を有する高耐圧ＩＣの要部平面図
【符号の説明】
１高電位側電極
２低電位側電極
３〜６メタル層
７〜１１薄膜抵抗層
１２コンタクトホール
１３、１４層間絶縁膜
２１ｐ基板
２２Ｎｗｅｌｌ領域
２３ｎ領域
２４、２５ｐ領域
２６Ｐｏｆｆｓｅｔ領域
２７、２８選択酸化膜
２９ｎ⁺領域
３１〜３７ｐ⁺領域
３８裏面側電極
４１酸化膜
４２ポリシリコン
４３、４７イオン注入（ＢＦ₂）
４４、４６フォトレジスト
４５イオン注入（Ａｓ）
４８凸部
５１ｎ領域
５２ｎ⁺領域
５３低電位領域
５４〜５７ガードリング（ｐ領域）
５８高電位領域
５９低電位側電極
６０電極膜
６１裏面側電極
６２ダイシング面
６３酸化膜
７１高電位側領域
７２耐圧構造部
７３低電位側領域
７４ゲート・ソース電極
７５ドレイン電極[0001]
BACKGROUND OF THE INVENTION
The present invention relates to planar lateral and vertical semiconductor devices, and more particularly to a breakdown voltage structure of the semiconductor device.
[0002]
[Prior art]
A power device represented by a bipolar transistor, a power MOSFET, and an IGBT (insulated gate bipolar transistor) requires a withstand voltage structure (a structure having a withstand voltage) of several tens to several thousand volts. In addition, in order to drive these power devices, in recent years, development of high voltage ICs has been actively carried out, and this high voltage IC is also required to have a breakdown voltage equivalent to that of the power device.
[0003]
FIG. 15 is a cross-sectional view of an essential part of a structure in which a double RESURF structure and a resistive field plate structure are combined. This breakdown voltage structure is a typical structure of a high breakdown voltage IC.
In FIG. 15, an Nwell region 102 is provided on the surface layer of the p substrate 101. An n-type high potential region 103, a p-type low potential region 104, and a Poffset region 105 are formed on the surface layer of the Nwell region 102, respectively. A high potential side electrode 106 and a low potential side electrode 107 are formed on the high potential region 103 and the low potential region 104, respectively, and a high resistivity resistance is formed on the insulating oxide film 108 formed on the p substrate 101. A thin film resistive layer 109 which is a conductive field plate is formed, and the high potential side electrode 106 and the low potential side electrode 107 are electrically connected by the thin film resistive layer 109. Further, the low potential side electrode 107 and the back side electrode 110 are electrically connected at the terminal portion of the p substrate 101.
[0004]
FIG. 16 is a diagram showing the expansion of the depletion layer inside the semiconductor. The cross-sectional view of the main part of the semiconductor device showing the expansion of the depletion layer in FIG. 16 is the same as the cross-sectional view of the main part in FIG. Therefore, the reference numerals in the figure are the same as those in FIG.
In FIG. 16, when a positive potential VS is applied to the high potential side electrode 106 with reference to the low potential side electrode 107 and the back surface side electrode 110, the depletion layers 111 and 112 from two pn junctions to which a reverse bias is applied. Will expand.
[0005]
One pn junction is a pn junction between the Nwell region 102, the Poffset region 105, and the low potential region 104, and the other pn junction is a pn junction between the Nwell region 102 and the p substrate 101.
In general, due to the influence of the fixed charges at the interface between the insulating oxide film 108 and the semiconductor, the electric field tends to concentrate inside the depletion layer on the semiconductor surface, which leads to the destruction of the device.
[0006]
In the resistive field plate structure, when the potential Vs is applied to the high potential side electrode 106, the potential Vs is also applied to the thin film resistance layer 109, and the thin film resistance layer 109 corresponds to the potential Vs and the resistance value of the thin film resistance layer 109. Current flows. Accordingly, if a uniform potential distribution is generated in the thin-film resistance layer 109, the electric field due to this potential distribution affects the semiconductor layer through the insulating oxide film 108, and the electric field concentration in the depletion layer on the surface of the semiconductor layer. Can be relaxed. As a result, a high breakdown voltage can be stably secured.
[0007]
In the conventional structure, in order to prevent a large leakage current between the high potential region 103 and the low potential region 104, the thin film resistor layer 109, which is a field plate, has a high resistivity layer of several MΩcm, for example, Non-doped amorphous silicon and SIPOS (Semi-Insulating Polycrystalline Silicon) have been used.
[0008]
However, to stably form a layer with a high specific resistance of several MΩcm, impurities entering this layer must be suppressed to be extremely small, and manufacturing is extremely difficult. Also, the specific resistance value varies easily depending on the location.
When the resistance value of the thin-film resistance layer 109 is low, the variation in the resistance value becomes small, but since a large leakage current flows, the generated loss increases and the device is easily destroyed. In addition, when the resistance value is too high, the resistance value varies and the leakage current tends to flow unevenly, and a uniform potential distribution is formed between the high potential region 103 and the low potential region 104. There is a possibility that the electric field concentration portion is generated in the depletion layer of the semiconductor layer and the breakdown voltage is lowered.
[0009]
In order to solve these problems, Japanese Patent No. 3117023 discloses a structure as shown in FIG. 17 in which the resistance value of the thin film resistor layer 109 is lowered to suppress variations. In this structure, the thin film resistance layer is formed in a spiral shape between the island-shaped base electrode 113 (high potential side electrode) and the outer peripheral electrode 114 (low potential side electrode) surrounding the base electrode 113 (high potential side electrode). The resistance value is increased by connecting the base electrode 113 and the outer peripheral electrode 114 with (a spiral thin film resistance layer 115).
[0010]
In this structure, the specific resistance of the spiral thin film resistance layer 115 is reduced to suppress variation, and the resistance value between the ends of the spiral thin film resistance layer 115 is increased to suppress leakage current. Yes. In addition, the potential distribution on the line connecting the base electrode 113 and the outer peripheral electrode 114 in a straight line changes in a staircase pattern by the number of spirals of the spiral thin film resistance layer 115. Becomes smaller, and the average potential gradient becomes constant.
[0011]
According to this structure, the specific resistance value of the spiral thin film resistive layer 115 that electrically connects the base electrode 113 and the outer peripheral electrode 114 can be realized as a lower value than that of the resistive field plate of the conventional structure. is there. As a result, the resistance value can be controlled more easily than the resistive field plate.
[0012]
[Problems to be solved by the invention]
However, when this spiral thin film resistance layer 115 is applied to the breakdown voltage structure portion of the high breakdown voltage IC disclosed in US Pat. No. 6,124,628 with respect to the structure as shown in FIG. 17, this breakdown voltage structure has a shape as shown in FIG. Is complicated, and the perimeter of one round becomes as long as about 4 to 10 mm. When the perimeter lengthens, the breakdown voltage tends to become unstable when a high voltage is applied to the high-potential side electrode. To obtain a stable breakdown voltage, a plurality of spiral thin film resistance layers are wound on the layout. There are difficulties.
[0013]
This is because the planar shape of the pressure-resistant structure is complex, so that the spiral thin film resistance layer is gradually changed from the base electrode to the outer peripheral electrode so that the electric field does not concentrate. This is because it is difficult to arrange.
Also, if the chip size is different, the peripheral length will be different, so it is necessary to adjust the shape or resistance value of the spiral thin film resistor layer that winds around the pressure-resistant structure even for devices with the same breakdown voltage. When designing devices with different current capacities in series with the same withstand voltage series, the withstand voltage structure must be designed each time, which is inconvenient.
[0014]
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problems and provide a semiconductor device having a breakdown voltage structure that is less likely to cause electric field concentration and can easily cope with a complicated plane pattern.
[0015]
[Means for Solving the Problems]
  In order to achieve the above object, a semiconductor device having a first electrode and a second electrode formed on an insulating film formed on a semiconductor substrate so as to be separated from each other so as to surround the first electrode. In addition, a plurality of films are formed on the insulating film between the first electrode and the second electrode.Made of metal filmThe loop-shaped conductive film layer, the first electrode and the loop-shaped conductive film layer, the loop-shaped conductive film layer, and the loop-shaped conductive film layer and the second electrode are electrically connected to each other. A thin film resistor layer connected toAnd
The loop-like conductive film layer and the thin film resistance layer constitute a field plate,
The sheet resistance value of the thin film resistive layer is 1 × 10 ⁴ Ω / □ or more 5 × 10 ⁴ Ω / □ or less,
The thin-film resistance layer having a predetermined width is disposed not obliquely to the longitudinal direction of the loop-like conductive film layer, and is obliquely connected.The configuration.
[0016]
A first insulating film formed on the semiconductor substrate; a second insulating film formed on the first insulating film; and the first electrode formed on the second insulating film so as to be separated from each other. And the second electrode and a plurality of the second electrode and the second electrode are formed on the second insulating film between the first electrode and the second electrode so as to surround the first electrode.Made of metal filmThe loop-shaped conductive film layer, the first electrode and the loop-shaped conductive film layer, the loop-shaped conductive film layer, and the loop-shaped conductive film layer and the second electrode are electrically connected to each other. Connected toIn contact with the first insulating filmA thin film resistor layer formed on the first insulating film.And
The loop-like conductive film layer and the thin film resistance layer constitute a field plate,
The sheet resistance value of the thin film resistive layer is 1 × 10 ⁴ Ω / □ or more 5 × 10 ⁴ Ω / □ or less,
The thin-film resistance layer having a predetermined width is disposed not obliquely to the longitudinal direction of the loop-like conductive film layer, and is obliquely connected.The configuration.
[0017]
  Also,An opening is formed in the second insulating film under the loop-like conductive film layer, and in the region where the opening is formed,The bottom of the loop-like conductive film layer may be in contact with the first insulating film apart from the thin film resistance layer.
  Also,The thin film resistance layer may be formed of polysilicon.
[0018]
  Also,The semiconductor substrate is of a first conductivity type, and a first conductivity type first region and a second conductivity type second region are formed separately on a surface layer of the semiconductor substrate, and the first region and the second region are formed. A surface layer of the semiconductor substrate between the regions, separated from the first region and in contact with the second region;offsetA region is formed, the first region and the first electrode are connected, and the second region and the second electrode are connected.
[0019]
  Further, the semiconductor substrate is of a first conductivity type, and a first region and a second region of a second conductivity type are formed separately on the surface layer of the semiconductor substrate, respectively, and the first region and the second region are formed. In the surface layer of the semiconductor substrate between the first region and the second region, the second conductivity typeGuard ringThe region is formed in a loop shape so as to surround the first region, the first region and the first electrode are connected, and the second region and the second electrode are connected.
[0020]
As described above, a plurality of loop-like conductive film layers are formed between the first electrode and the second electrode so as to surround the first electrode, and the first electrode, the innermost loop-like conductive film layer, and the loop are formed. The conductive film layers, the outermost conductive film layer, and the second electrode are electrically connected to each other by a thin film resistance layer, whereby each loop-shaped conductive film layer has a potential of the first electrode and a potential of the second electrode. The potential of the semiconductor substrate existing under the insulating film is made uniform by the influence of the stepwise potential distribution of each loop-like conductive film layer. Can do.
[0021]
As a result, the breakdown voltage of the semiconductor device can be easily increased as compared with a structure having only a spiral thin film resistance layer, which has been difficult to layout with a complicated shape.
In addition, even if the devices have the same breakdown voltage, even when the chip sizes are different, the shape of the loop-like conductive film layer and the sheet resistance value do not often need to be changed, and the design becomes easy.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
1 to 5 show a semiconductor device according to a first embodiment of the present invention. FIG. 1 (a) is a plan view of an essential part, and FIG. 1 (b) is an enlarged plan view of a part A in FIG. 1 (a). 2 is a cross-sectional view of main parts cut along line XX in FIG. 1B, FIG. 3 is a cross-sectional view of main parts cut along line Y-Y in FIG. 1B, and FIG. FIG. 5 is a cross-sectional view of main parts cut along line ZZ in FIG. 1B, and FIG. 5 is a cross-sectional view of main parts cut in line MM in FIG. This semiconductor device is exemplified by a high voltage IC having a double RESURF structure.
[0023]
1 to 5, a low potential side region 73 is formed so as to surround a high potential side region 71, and metal layers 3, 4, 5, and 6 are formed in a loop shape in the breakdown voltage structure portion 72 therebetween. ing. Reference numerals 74 and 75 denote a gate / source electrode and a drain electrode of the high voltage MOSFET. The high potential side region 71 and the metal layer 3, the metal layer 3 and the metal layer 4, the metal layer 4 and the metal layer 5, the metal layer 5 and the metal layer 6, and the metal layer 6 and the low potential side region are the thin film resistance layers 7 and 8. , 9, 10 and 11 (FIG. 1A). Next, the configuration of the thin-film resistance layers 7, 8, 9, 10, and 11 will be described.
[0024]
An Nwell region 22 is provided on the surface layer of the p substrate 21. An n-type high potential region 71 (n region 23), a p-type low potential side region 73 (p region 24), and Poffset are formed on the surface layer of the Nwell region 22. Each of the regions 26 is formed, the high potential side electrode 1 and the low potential side electrode 2 are formed on the high potential side region 71 and the low potential side region 73, respectively, and the selective oxide film 27 is formed on the p substrate 21. Is formed. Thin film resistance layers 7, 8, 9, 10, 11 are formed on the selective oxide film 27, and loop-shaped metal layers 3, 4, 5, 6 are formed thereon via an interlayer insulating film 13. Potential side electrode 1 and innermost metal layer 3, metal layer 3 and metal layer 4, metal layer 4 and metal layer 5, metal layer 5 and metal layer 6, and outermost metal layer 6 and low potential side electrode 2 Are electrically connected to each other by the thin-film resistance layers 7, 8, 9, 10, and 11 (FIGS. 2 and 4), and the low-potential side electrode 2 and the back-side electrode 38 are at the end of the p substrate 21 (not shown). Electrically connected.
[0025]
In the figure, 23 is an n region, 24 and 25 are p regions, 28 is a selective oxide film, and 29 is an n for contact.⁺Regions 31-37 are p for contact⁺A region 12 is a contact hole for connecting the metal layer and the thin film resistance layer.
6 shows a cross-sectional view of the main part and the potential distribution of the semiconductor device of FIG. 1, FIG. 6A is a cross-sectional view of the main part of FIG. 2, and FIG. 6B is a loop shape of FIG. It is a figure which shows the electric potential distribution of a metal layer.
[0026]
FIG. 6B is a graph showing the potential distribution of the high potential side electrode 1, the metal layers 3, 4, 5, 6, and the low potential side electrode 2, with the horizontal axis representing the amount of displacement from the high potential side electrode 1. Is.
As shown in the figure, in the potential distribution when there are four metal layers, the potential difference between the metal layers is large. However, in practice, the interval between the high potential side electrode 1 and the low potential side electrode 2 is about 150 to 200 μm in the high voltage IC of 1400 V class. For example, the width of the metal layers 3, 4, 5, 6 is If the distance between the metal layers is 8 μm and the distance between the metal layers is 4 μm, about 12 to 16 metal layers can be formed. As the number of the metal layers is increased, the distance from the high potential side electrode 1 to the low potential side electrode 2 is increased. The stepped potential difference (step) can be reduced, thereby reducing the concentration of the electric field and increasing the breakdown voltage. The number of metal layers can be increased by reducing the width and interval of the metal layers.
[0027]
Next, the sheet resistance values of the thin-film resistance layers 7, 8, 9, 10, and 11 will be described. The thin film resistor layers 7, 8, 9, 10, and 11 can be formed of polysilicon having a film thickness of about 0.4 to 1 μm, for example. By thinning the thin-film resistance layers 7, 8, 9, 10, 11 to about 2 μm and arranging them in an oblique manner rather than perpendicular to the longitudinal direction of the loop-shaped metal layers 3, 4, 5, 6 The lengths of the thin-film resistance layers 7, 8, 9, 10, and 11 can be increased. By increasing the length of the thin-film resistance layers 7, 8, 9, 10, and 11, the sheet resistance values of the thin-film resistance layers 7, 8, 9, 10, and 11 can be lowered to a level that can be easily controlled.
[0028]
As an example, a case where 1400 V is applied to the high potential side electrode in the structure of FIG. 1 will be described. When the leakage current is about 10 μA through the thin-film resistance layers 7, 8, 9, 10, and 11, the resistance value is 1400 V / 10 μA = 1.4 × 10⁸ Ω = 140 MΩ. Since five thin-film resistance layers 7, 8, 9, 10, and 11 are connected in series, 140 MΩ ÷ 5 = 28 MΩ per one thin-film resistance layer.
[0029]
The length of one thin film resistive layer is 1.5 mm, the width is 2 μm, and the sheet resistance value of the thin film resistive layer is 28 MΩ × 2 ÷ 1500 = 3.73 × 10.^Four Ω / □ = 37.3kΩ / □
When the number of metal layers is 13 and the number of thin film resistance layers is 14, the resistance value per thin film resistance layer is 140 MΩ ÷ 14 = 10 MΩ.
[0030]
Assuming that the length of one thin film resistive layer is 1.5 mm and the width is 2 μm, the sheet resistance value of the thin film resistive layer is 10 MΩ × 2 ÷ 1500 = 1.33 × 10.^FourΩ / □ = 13.3 kΩ / □.
As described above, in the breakdown voltage structure of the present invention, the sheet resistance value of the polysilicon holding the voltage can be lowered to a level that can be easily realized by increasing the number of metal layers.
[0031]
However, when the number of metal layers is increased, the width of the thin film resistor layer connected to the metal layer becomes narrow, making it difficult to process the thin film resistor layer, and it is necessary to significantly reduce the sheet resistance value. Therefore, the sheet resistance value of a practical thin film resistance layer is 10 kΩ / □ or more and 50 kΩ / □ or less. If it exceeds 50 kΩ / □, the variation of the sheet resistance value in the thin film resistance layer becomes large, which is not practical.
[0032]
The range of the sheet resistance value is a range in which a sufficient impurity concentration can be secured by an ion implantation method or the like.
As described above, when the withstand voltage structure of the first embodiment in which the metal layers 3, 4, 5, 6 and the thin film resistor layers 7, 8, 9, 10, 11 are combined is adopted, a high sheet resistance value of several MΩ / □ is obtained. In addition, even in a complicated semiconductor device having a long peripheral length such as a high breakdown voltage IC, layout and resistance value setting can be facilitated, and a high breakdown voltage of the semiconductor device can be achieved.
[0033]
Further, when the withstand voltage class is the same and the current capacities are different, it is not necessary to change the sheet resistance value of the thin-film resistance layer, so that the withstand voltage structure can be easily designed.
FIGS. 7 to 12 show a manufacturing method of the semiconductor device according to the first embodiment, and are main part manufacturing process diagrams shown in the order of processes. This principal part manufacturing process diagram corresponds to the sectional view of the principal part of FIG.
[0034]
First, n regions 22 and 23, p regions 24 and 25, and a Poffset region 26 are formed on the p substrate 21 by ion implantation and thermal diffusion, and then selective oxide films 27 and 28 are formed (FIG. 7).
Next, a gate oxide film is formed at a location not shown. As for this gate oxide film, the oxide film 41 is formed also in places other than the gate formation place. In order to control the resistance value of the polysilicon 42 in the portions to be the thin film resistance layers 7, 8, 9, 10, 11 by forming the polysilicon 42 on the oxide film 41 and the selective oxide film 27, B or B compound (BF₂Etc.) is implanted 43. As described above, the dose is determined so that the sheet resistance value of the polysilicon 42 is about 10 to 50 kΩ / □ (FIG. 8).
[0035]
Next, the polysilicon 42 is patterned by ordinary exposure and etching techniques to form the thin-film resistance layers 7, 8, 9, 10, and 11 (FIG. 9).
Next, the photoresist 44 is coated, and selective As ion implantation 45 is performed by exposure and etching techniques, whereby the surface layer of the n region 23 is contacted with a metal layer to be described later.⁺Region 29 is formed (FIG. 10).
[0036]
Next, the photoresist 44 is removed, a new photoresist 46 is coated, and selective BF is applied by exposure and etching techniques.₂By performing ion implantation 47 of ions, p for making contact with a metal layer to be described later on the surface layer of the thin-film resistance layers 7, 8, 9, 10, 11 formed of polysilicon.⁺The regions 31, 32, 33, 34, and 35 are formed, and p for making contact with a metal layer to be described later is formed on the surface layer of the p regions 24 and 25.⁺Regions 36 and 37 are formed (FIG. 11). These regions are formed using the oxide film 41 as a screen oxide film. However, the oxide film 41 can be removed and the thermal oxide film can be formed again before forming these regions.
[0037]
Next, after forming interlayer insulating films 13 and 14 such as PSG (phosphorus glass film), the high potential side electrode 1, the metal layers 3, 4, 5, 6 and the low potential side electrode 2 are formed by exposure and etching techniques. A contact hole is formed for contact with the substrate, a metal such as Al is sputtered on the entire surface, and patterning is performed by exposure and etching techniques, and the high potential side electrode 1, metal layers 3, 4, 5, 6 and low The potential side electrode 2 is formed (FIG. 12).
[0038]
Further, a passivation film on the surface (not shown) is formed and patterned to complete the process.
In the first embodiment, the breakdown voltage structure of the horizontal planar semiconductor device has been described. However, in the case of the vertical semiconductor device described in the next embodiment, the depletion layer extends in the horizontal direction from the active region of the chip. In this type, the method of connecting the high potential side electrode and the low potential side electrode with the thin film resistor layer and the loop-shaped metal layer (conductive film layer) used in the first embodiment is very effective.
[0039]
13A and 13B show a semiconductor device according to a second embodiment of the present invention. FIG. 13A is a plan view of the main part, and FIG. 13B is a cross-sectional view of the main part taken along line MM in FIG. FIG. The difference from the first embodiment is that the metal layer has a convex portion so that the interlayer insulating film 13 under the loop-shaped metal layers 3, 4, 5, 6 in FIG. 5 is opened and reaches the selective oxide film 27. 48 is provided. By doing so, the potential of the loop-shaped metal layers 3, 4, 5, 6 can be effectively transmitted to the semiconductor surface under the selective oxide film 27 without passing through the interlayer insulating film 13. By effectively reflecting the potential of the metal layers 3, 4, 5, 6 on the semiconductor surface, local electric field concentration is less likely to occur than in the semiconductor device of the first embodiment, and stable high breakdown voltage is secured. can do.
[0040]
FIG. 14 is a cross-sectional view of the main part of the semiconductor device according to the third embodiment of the present invention. The breakdown voltage structure of this semiconductor device is a planar structure and is an example combined with a guard ring structure often used for peripheral breakdown voltage structures of vertical devices and horizontal devices. This figure shows a cross-sectional view of the main part of the pressure-resistant structure.
n on the back side of the n layer 51⁺A layer 52 is formed, and a p-well region to be a low potential region 53 is formed on the surface side, and p regions 54, 55, 56, and 57 to be guard rings are formed so as to surround the low potential region 53, respectively. For this, a p region to be the high potential region 58 is formed. In the p-well region to be the low potential region 53, an active region (not shown) (for example, a region occupied by a gate portion or a source portion in the case of MOSFET) is formed. A low potential side electrode 59 is formed on the low potential region 53, and an electrode film 60 is formed on the high potential region 58. The back surface side electrode 61 and the electrode film 60, which are high potential electrodes, are electrically connected by a dicing surface 62.
[0041]
Thin film resistance layers 7, 8, 9, 10, 11 are formed on the oxide film 63, and loop-shaped metal layers 3, 4, 5, 6 are formed thereon via the interlayer insulating film 13, and the electrode film 60 The innermost metal layer 3, the metal layer 3 and the metal layer 4, the metal layer 4 and the metal layer 5, the metal layer 5 and the metal layer 6, and the outermost metal layer 6 and the low potential side electrode 59 are thin film resistors Electrically connected by layers 7, 8, 9, 10, 11 respectively.
[0042]
Here, when the potential Vs is applied to the back surface side electrode 61 that is the high potential side electrode, the potential Vs is applied between the low potential side electrode 59 and the electrode film 60, and the thin film resistance layers 7, 8, 9, 10, 11 are applied. Leak current flows, a uniform potential distribution is formed in the loop-shaped metal layers 3, 4, 5, 6 and the electric field due to this potential distribution relaxes the electric field concentration in the depletion layer in the semiconductor, Keep pressure resistance. In the figure, the loop-shaped metal layers 3, 4, 5, 6 are arranged on the guard ring, but it is not always necessary to arrange them on the guard ring.
[0043]
【The invention's effect】
According to the present invention, the first electrode and the second electrode that are electrically connected to the high potential region and the low potential region on the semiconductor substrate are provided, and the first electrode and the second electrode around the first electrode are provided between the first electrode and the second electrode. Forming a plurality of loop-like conductive film layers, and forming a thin film resistance layer between the first electrode and the loop-like conductive film layer, between the loop-like conductive film layers, and between the loop-like conductive film layer and the second electrode. By electrically connecting
When a voltage is applied between the first electrode and the second electrode, the potential distribution between the first electrode and the second electrode in the loop-like conductive film layer is linear in a fine step from a high potential to a low potential. Therefore, a uniform potential distribution is formed also inside the semiconductor substrate, electric field concentration hardly occurs, and a semiconductor device with high breakdown voltage can be obtained.
[0044]
In addition, the sheet resistance value of the thin film resistance layer itself can be controlled to a low resistance level by increasing the resistance value by increasing the length of each thin film resistance layer and making it thin. is there.
Further, even in a semiconductor device having a complicated withstand voltage structure such as a high withstand voltage IC and a long peripheral length, the withstand voltage structure can be easily designed by combining a thin film resistance layer and a loop-like conductive film layer.
[0045]
Also, when designing elements with the same breakdown voltage and different peripheral lengths, the breakdown voltage structure can be designed without changing the width and length of the thin film resistance layer.
[Brief description of the drawings]
1A and 1B show a semiconductor device according to a first embodiment of the present invention, in which FIG. 1A is a plan view of an essential part, and FIG. 1B is an enlarged plan view of a part A of FIG.
2 is a cross-sectional view of the principal part taken along line XX in FIG. 1B, showing the semiconductor device according to the first embodiment of the present invention;
3 is a semiconductor device according to the first embodiment of the present invention, and is a cross-sectional view of the principal part taken along line YY in FIG. 1B;
4 is a cross-sectional view of the principal part taken along the line ZZ in FIG. 1B, showing the semiconductor device according to the first embodiment of the present invention;
FIG. 5 is a cross-sectional view of the principal part taken along line MM in FIG. 1B, showing the semiconductor device according to the first embodiment of the present invention;
6 shows a cross-sectional view and a potential distribution of a main part of the semiconductor device of FIG. 1, (a) shows a cross-sectional view of a main part of FIG. 2, and (b) shows a potential distribution of the loop-shaped metal layer of (a). Figure
FIG. 7 is a main part manufacturing process diagram of the semiconductor device according to the first embodiment;
8 is a main part manufacturing process diagram of the semiconductor device of the first embodiment, following FIG. 7;
FIG. 9 is a manufacturing process diagram of main parts of the semiconductor device of the first embodiment, following FIG. 8;
FIG. 10 is a manufacturing process diagram for the main part of the semiconductor device in the first embodiment, following FIG. 9;
FIG. 11 is a manufacturing process diagram for the main part of the semiconductor device of the first embodiment, following FIG. 10;
12 is a main part manufacturing process diagram of the semiconductor device of the first embodiment, following FIG. 11;
13A and 13B show a semiconductor device according to a second embodiment of the present invention, in which FIG. 13A is a plan view of relevant parts, and FIG. 13B is a cross-sectional view of relevant parts cut along line MM in FIG.
FIG. 14 is a fragmentary cross-sectional view of a semiconductor device according to a third embodiment of the present invention;
FIG. 15 is a cross-sectional view of an essential part of a structure in which a double RESURF structure and a resistive field plate structure are combined.
FIG. 16 shows the expansion of a depletion layer inside a semiconductor.
FIG. 17 is a semiconductor device having a spiral thin film resistance layer disclosed in Japanese Patent No. 3117023;
FIG. 18 is a plan view of an essential part of a high voltage IC having a voltage structure with a complicated planar pattern.
[Explanation of symbols]
1 High potential side electrode
2 Low potential side electrode
3-6 metal layer
7-11 Thin film resistive layer
12 Contact hole
13, 14 Interlayer insulation film
21p substrate
22 Nwell region
23 n region
24, 25 p region
26 Poffset area
27, 28 Selective oxide film
29 n⁺region
31-37 p⁺region
38 Back side electrode
41 Oxide film
42 Polysilicon
43, 47 Ion implantation (BF₂)
44, 46 photoresist
45 Ion implantation (As)
48 Convex
51 n region
52 n⁺region
53 Low potential region
54-57 Guard ring (p region)
58 High potential region
59 Low potential side electrode
60 Electrode membrane
61 Back side electrode
62 Dicing surface
63 Oxide film
71 High potential side region
72 Pressure resistant structure
73 Low potential area
74 Gate / source electrode
75 Drain electrode

Claims

A semiconductor device having a first electrode and a second electrode formed on an insulating film formed on a semiconductor substrate and spaced apart from each other, the first electrode and the first electrode surrounding the first electrode. A loop-like conductive film layer made of a plurality of metal films formed on the insulating film between two electrodes, and between the first electrode and the loop-like conductive film layer, between the loop-like conductive film layers A thin film resistance layer electrically connecting the loop-like conductive film layer and the second electrode to each other,
The loop-like conductive film layer and the thin film resistance layer constitute a field plate,
The sheet resistance value of the thin film resistance layer is 1 × 10 ⁴ Ω / □ or more and 5 × 10 ⁴ Ω / □ or less,
The semiconductor device is characterized in that the connection is made by arranging the thin film resistance layer having a predetermined width obliquely rather than perpendicular to the longitudinal direction of the loop-like conductive film layer.

A first insulating film formed on a semiconductor substrate; a second insulating film formed on the first insulating film; the first electrode formed on the second insulating film and spaced apart from each other; A loop-like conductive film layer made of a plurality of metal films formed on the second insulating film between the first electrode and the second electrode so as to surround the first electrode and the second electrode; The first insulation is electrically connected between the first electrode and the loop-like conductive film layer, between the loop-like conductive film layers, and between the loop-like conductive film layer and the second electrode. A thin film resistance layer formed on the first insulating film in contact with the film,
The loop-like conductive film layer and the thin film resistance layer constitute a field plate,
The sheet resistance value of the thin film resistance layer is 1 × 10 ⁴ Ω / □ or more and 5 × 10 ⁴ Ω / □ or less,
The semiconductor device is characterized in that the connection is made by arranging the thin film resistance layer having a predetermined width obliquely rather than perpendicular to the longitudinal direction of the loop-like conductive film layer.

An opening is formed in the second insulating film below the loop-shaped conductive film layer, and a bottom portion of the loop-shaped conductive film layer is separated from the thin film resistance layer in the region where the opening is formed, and the first insulating film is formed. The semiconductor device according to claim 2, wherein the semiconductor device is in contact with the film.

4. The semiconductor device according to claim 1, wherein the thin film resistance layer is made of polysilicon.

The semiconductor substrate is of a first conductivity type, and a first conductivity type first region and a second conductivity type second region are formed separately on a surface layer of the semiconductor substrate, and the first region and the second region are formed. An offset region of a second conductivity type is formed in a surface layer of the semiconductor substrate between regions so as to be separated from the first region and in contact with the second region, and the first region, the first electrode, The semiconductor device according to claim 1, wherein the second region and the second electrode are connected to each other.

The semiconductor substrate is of a first conductivity type, and a first region and a second region of a second conductivity type are formed on the surface layer of the semiconductor substrate so as to be separated from each other, and between the first region and the second region. A second conductivity type guard ring region is formed in a loop shape so as to surround the first region apart from the first region and the second region on the surface layer of the semiconductor substrate, The semiconductor device according to claim 1, wherein the first electrode is connected, and the second region and the second electrode are connected.