JP2003008009A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a withstand voltage structure that hardly causes electric field concentration and can easily cope with a complicated planar pattern. SOLUTION: In this semiconductor device, thin resistance layers 7, 8, 9, 10 and 11 are formed on a selectively oxidized film 27, and loop-like metallic layers 3, 4, 5 and 6 are respectively formed on the resistance layers 7, 8, 9, 10 and 11 through interlayer insulating films 13. In addition, the electric connection between a high-potential electrode 1 and the innermost metallic layer 3, among the metallic layers 3, 4, 5 and 6, and between the outermost metallic layer 6 and a low-potential side electrode 2 are respectively made through the resistance layers 7, 8, 9, 10 and 11. In addition, the low-potential side electrode 2 is electrically connected to a rear-surface side electrode 38 at the end section of a p-type substrate 21 not shown in the figure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planar type horizontal and vertical semiconductor device, and more particularly to a breakdown voltage structure of the semiconductor device.

[0002]

2. Description of the Related Art Bipolar transistor, power MOS
A power device represented by an FET and an IGBT (insulated gate bipolar transistor) requires a withstand voltage structure (a structure having a withstand voltage) of several tens to several thousands V. Further, in order to drive these power devices, a high breakdown voltage IC has been actively developed in recent years, and this high breakdown voltage IC is also required to have a breakdown voltage equivalent to that of the power device.

FIG. 15 is a cross-sectional view of an essential part of a structure in which the Double RESURF structure and the resistive field plate structure are combined. This breakdown voltage structure is a typical structure of a high breakdown voltage IC. In FIG. 15, an Nwell region 102 is provided on the surface layer of the p substrate 101. This N
The n-type high potential region 10 is formed on the surface layer of the well region 102.
3, a p-type low potential region 104, and a Poffset region 105 are formed. High potential region 103
A high-potential-side electrode 106 and a low-potential-side electrode 107 are formed on the top and the low-potential region 104, respectively.
A thin-film resistance layer 109, which is a resistive field plate having a high specific resistance, is formed on the insulating oxide film 108 formed above, and the thin-film resistance layer 109 electrically connects the high-potential side electrode 106 and the low-potential side electrode 107. It is connected to the. Further, the low potential side electrode 107 and the back surface side electrode 110 are electrically connected at the terminal end portion of the p substrate 101.

FIG. 16 is a diagram showing the expansion of the depletion layer inside the semiconductor. The cross-sectional view of the main part of the semiconductor device showing the expansion of the depletion layer in FIG. 16 is the same as the cross-sectional view of the main part in FIG. Therefore, the reference numerals in the figure are the same as those in FIG. In FIG. 16, a positive potential V is applied to the high potential side electrode 106 with reference to the low potential side electrode 107 and the back surface side electrode 110.
Two pns with reverse bias applied when S is applied
The depletion layers 111 and 112 expand from the junction.

One pn junction is formed in the Nwell region 102.
And Poffset region 105, pn of low potential region 104
Another pn junction is the Nwell region 1
02 and the p substrate 101 are pn junctions. Generally, due to the effect of fixed charges at the interface between the insulating oxide film 108 and the semiconductor, electric field concentration is likely to occur inside the depletion layer on the semiconductor surface, which leads to device breakdown.

In the resistive field plate structure, when the potential Vs is applied to the high potential side electrode 106, the thin film resistance layer 1
The potential Vs is also applied to 09, and a current corresponding to the potential Vs and the resistance value of the thin film resistance layer 109 flows through the thin film resistance layer 109. As a result, if a uniform potential distribution is generated in the thin film resistance layer 109, the electric field due to this potential distribution affects the semiconductor layer through the insulating oxide film 108, and the electric field is concentrated in the depletion layer on the surface of the semiconductor layer. Can be relaxed. As a result, a high breakdown voltage can be stably ensured.

In the conventional structure, the high potential region 103
The thin film resistance layer 109, which is a field plate, prevents a large leakage current from occurring between the low potential region 104 and the low potential region 104.
Is a layer having a high resistivity of several MΩcm, such as non-doped amorphous silicon or SIPOS (Semi-Ins).
ulating PolycrystallineSi
licon) has been used.

However, in order to stably form a layer having a high specific resistance of several MΩcm, it is necessary to suppress impurities entering the layer to a very small level, and it is extremely difficult to manufacture the layer. Moreover, the value of the specific resistance tends to vary depending on the location. When the resistance value of the thin-film resistance layer 109 is low, the fluctuation of the resistance value is small, but a large leakage current flows, the generated loss becomes large, and the device is easily broken. If the resistance value is too high, the resistance value varies, and the leakage current easily flows unevenly, and a uniform potential distribution is formed between the high potential region 103 and the low potential region 104. However, there is a possibility that the electric field is concentrated in the depletion layer of the semiconductor layer and the breakdown voltage is lowered.

In order to solve these problems, a structure as shown in FIG. 17 in which the resistance value of the thin film resistance layer 109 is lowered to suppress the variation is disclosed in Japanese Patent No. 3117023. In this structure, the thin-film resistance layer is formed in a spiral shape between the island-shaped base electrode 113 (high-potential side electrode) and the peripheral electrode 114 (low-potential side electrode) surrounding the island-shaped base electrode 113 to form a long thin-film resistance layer. (Swirl-shaped thin film resistance layer 11
The resistance value is increased by connecting the base electrode 113 and the outer peripheral electrode 114 in 5).

In this structure, the spiral thin film resistance layer 11 is formed.
The specific resistance of No. 5 is reduced to suppress the variation, and the resistance value between the ends of the spiral thin-film resistance layer 115 is increased to suppress the leakage current. Further, the potential distribution on the line connecting the base electrode 113 and the outer peripheral electrode 114 with a straight line changes stepwise by the number of times of the spiral of the spiral thin-film resistance layer 115, but if the number of times is increased, the stairs drop Becomes smaller and the average potential gradient becomes constant.

According to this structure, the specific resistance value of the spiral thin film resistance layer 115 for electrically connecting the base electrode 113 and the outer peripheral electrode 114 can be realized as a lower value than that of the resistive field plate of the conventional structure. That is. This has the advantage that the resistance value is easier to control than the resistive field plate.

[0012]

However, in contrast to the structure shown in FIG. 17, the spiral thin film resistance layer 115 is
When applied to the withstand voltage structure portion of the high withstand voltage IC disclosed in SP6124628, this withstand voltage structure has a complicated shape as shown in FIG. 18, and the perimeter for one round becomes as long as about 4 to 10 mm. When the peripheral length becomes long, the withstand voltage tends to become unstable when a high voltage is applied to the high-potential side electrode, and in order to obtain a stable withstand voltage, it is necessary to arrange multiple spiral thin film resistance layers on the layout. There is difficulty.

This is because the withstand voltage structure has a complicated planar shape, so that the spiral thin film resistance layer is provided so that the electric field is not concentrated, and the distance between the base electrode and the spiral thin film resistance layer is increased from the base electrode to the peripheral electrode. The reason is that it is difficult to place them while changing them little by little. In addition, if the chip size is different, the peripheral length is different, so even for devices with the same breakdown voltage, it is necessary to adjust the shape or resistance value of the spiral thin film resistance layer that is wound around the breakdown voltage structure part. When designing devices having different current capacities in series having the same withstand voltage series, the withstand voltage structure must be designed each time, which is inconvenient.

An object of the present invention is to solve the above problems and to provide a semiconductor device having a breakdown voltage structure in which electric field concentration is unlikely to occur and which can easily cope with a complicated planar pattern.

[0015]

To achieve the above object, there is provided a semiconductor device having a first electrode and a second electrode formed on an insulating film formed on a semiconductor substrate and separated from each other. A plurality of loop-shaped conductive film layers are formed on the insulating film between the first electrode and the second electrode so as to surround the first electrode, the first electrode and the loop-shaped conductive layer. Between the film layers, between the loop-shaped conductive film layers, and between the loop-shaped conductive film layer and the second electrode, a thin film resistance layer is electrically connected to each other.

The first substrate formed on the semiconductor substrate
An insulating film, and a second insulating film formed on the first insulating film,
The first electrode and the second electrode formed on the second insulating film and separated from each other, and the second insulation between the first electrode and the second electrode so as to surround the first electrode. A plurality of loop-shaped conductive film layers formed on the film, between the first electrode and the loop-shaped conductive film layer, between the loop-shaped conductive film layers,
The loop-shaped conductive film layer and the second electrode are electrically connected to each other, and a thin film resistance layer formed on the first insulating film is provided.

The bottom of the loop-shaped conductive film layer may be separated from the thin-film resistance layer and contact the first insulating film. Further, it is preferable that the loop conductive film layer is formed of a material having a low resistance value such as a metal film. Further, the thin film resistance layer may be formed of polysilicon.

The sheet resistance value of the thin film resistance layer is
It is good that it is 1 × 10 ⁴ Ω / □ or more. Further, the sheet resistance value of the thin film resistance layer is preferably 5 × 10 ⁴ Ω / □ or less. Further, the semiconductor substrate is of the first conductivity type, and a first region of the first conductivity type and a second region of the second conductivity type are formed separately on a surface layer of the semiconductor substrate. A third region of the second conductivity type is formed on the surface layer of the semiconductor substrate between the second regions so as to be separated from the first region and contact the second region. One electrode is connected, and the second region and the second electrode are connected.

Further, the semiconductor substrate is of the first conductivity type, and the first region and the second region of the second conductivity type are formed separately on the surface layer of the semiconductor substrate, and the first region and the second region are formed. A fourth region of the second conductivity type is provided on the surface layer of the semiconductor substrate between the two regions, apart from the first region and the second region,
The first region is formed in a loop shape so as to surround the first region, the first region and the first electrode are connected, and the second region and the second electrode are connected.

As described above, a plurality of loop-shaped conductive film layers are formed between the first electrode and the second electrode so as to surround the first electrode, and the first electrode and the innermost loop-shaped conductive film are formed. Layer, the loop-shaped conductive film layers, and the outermost conductive film layer and the second electrode are electrically connected to each other by a thin-film resistance layer, whereby each loop-shaped conductive film layer has a potential of the first electrode and a second electrode. The intermediate potential between the potentials of the electrodes exists in a stepwise manner, and the potential of the semiconductor substrate existing thereunder via the insulating film is also uniform due to the effect of the stepwise potential distribution of each of the loop-shaped conductive film layers. Can be

As a result, a higher breakdown voltage of the semiconductor device can be easily realized as compared with the structure having only the spiral thin film resistance layer, which has been difficult to lay out with a complicated shape. Further, even in the case of devices having the same breakdown voltage, even if the chip sizes are different, it is often unnecessary to change the shape of the loop-shaped conductive film layer and the sheet resistance value, which facilitates the design.

[0022]

1 to 5 show a first embodiment of the present invention.
FIG. 1A is a plan view of a main part of the semiconductor device according to the embodiment.
1B is an enlarged plan view of a portion A of FIG.
3 is a sectional view of a main part taken along line XX in FIG.
4 is a sectional view of a main part taken along line YY of FIG.
5 is a sectional view of a main part taken along line ZZ in FIG.
[Fig. 2] is a main-portion cross-sectional view taken along line MM in Fig. 1 (b). This semiconductor device is exemplified by a high-voltage IC having a Double RESURF structure.

In FIG. 1 to FIG. 5, the high potential side region 71
A low-potential side region 73 is formed so as to surround the, and metal layers 3, 4, 5, and 6 are formed in a loop shape in the breakdown voltage structure portion 72 therebetween. 74 and 75 are high-voltage MO
These are the gate / source electrode and the drain electrode of the SFET.
High potential side region 71 and metal layer 3, metal layer 3 and metal layer 4, metal layer 4 and metal layer 5, metal layer 5 and metal layer 6
And the metal layer 6 and the low potential side region are the thin film resistance layer 7,
They are electrically connected by 8, 9, 10 and 11 (FIG. 1 (a)). Next, the thin film resistance layers 7, 8, 9,
The configurations of 10 and 11 will be described.

The Nwell region 22 is formed on the surface layer of the p substrate 21.
Are provided, and the n-type high potential region 71 (n region 23) and the p-type low potential side region 73 are provided on the surface layer of the Nwell region 22.
(P region 24) and Poffset region 26 are formed, respectively, on the high potential side region 71 and the low potential side region 7.
A high potential side electrode 1 and a low potential side electrode 2 are formed on the substrate 3, and a selective oxide film 27 is formed on the p substrate 21. On the selective oxide film 27, the thin film resistance layers 7, 8, 9,
10 and 11 are formed, and loop-shaped metal layers 3, 4, 5, and 6 are formed on the inter-layer insulating film 13, and the high-potential side electrode 1, the innermost metal layer 3, and the metal layer 3 are formed. The metal layer 4 and the metal layer 4, the metal layer 4 and the metal layer 5, the metal layer 5 and the metal layer 6, and the outermost metal layer 6 and the low-potential-side electrode 2 are respectively formed by thin-film resistance layers 7, 8, 9, 10, and 11. It is electrically connected (FIGS. 2 and 4), and the low potential side electrode 2 and the back surface side electrode 38 are electrically connected at the terminal end portion of the p substrate 21 (not shown).

In the figure, 23 is an n region and 24 and 25 are p regions.
Region, 28 is a selective oxide film, 29 is an n ⁺ region for making contact, 31 to 37 are p ⁺ for making contact
A region, 12 is a contact hole for connecting the metal layer and the thin film resistance layer. 6A and 6B show a cross-sectional view and a potential distribution of the main part of the semiconductor device of FIG. 1, FIG. 6A is a cross-sectional view of the main part of FIG. 2, and FIG. 6B is a loop-shaped view of FIG. It is a figure which shows the electric potential distribution of a metal layer.

FIG. 6B shows the potential distribution of the high potential side electrode 1, the metal layers 3, 4, 5, 6 and the low potential side electrode 2,
The horizontal axis is a graph showing the amount of displacement from the high potential side electrode 1. As shown in the figure, in the potential distribution when there are four metal layers, the potential difference between the metal layers is large. However, in reality, the distance between the high potential side electrode 1 and the low potential side electrode 2 is
150 to 200μ for 1400V class high voltage IC
m, for example, the width of the metal layers 3, 4, 5, 6 is 8
If the gap between the metal layers is 4 μm, and about 12 to 16 metal layers can be formed, the higher the number of metal layers, the higher the potential side electrode 1 to the lower potential side electrode 2 becomes.
It is possible to reduce the stepwise potential difference (step) up to, thereby reducing the concentration of the electric field and increasing the breakdown voltage. The number of metal layers can be increased by reducing the width and spacing of the metal layers.

Next, the thin film resistance layers 7, 8, 9, 10, 11
The sheet resistance value of is explained. The thin film resistance layer 7,
8, 9, 10, and 11 can be formed of, for example, polysilicon having a film thickness of 0.4 to 1 μm. Thin film resistance layers 7, 8,
By thinning the widths of 9, 10, 11 to about 2 μm and arranging the metal layers 3, 4, 5, 6 in a loop shape not obliquely to the longitudinal direction but obliquely, the thin film resistance layers 7, 8 , 9, 1
The length of 0 and 11 can be increased. By increasing the length of the thin film resistance layers 7, 8, 9, 10, 11, it is possible to reduce the sheet resistance value of the thin film resistance layers 7, 8, 9, 10, 11 to a level at which it can be easily controlled.

As an example, in the structure of FIG.
A case where V is applied to the high potential side electrode will be described. When the leakage current is about 10 μA through the thin film resistance layers 7, 8, 9, 10 and 11, the resistance value is 1400 V / 10 μ.
A = 1.4 × 10 ⁸ Ω = 140 MΩ. Since five thin film resistance layers 7, 8, 9, 10, and 11 are connected in series, one thin film resistance layer is 140 MΩ / 5 = 28.
It is MΩ.

If the length of one thin film resistance layer is 1.5 mm and the width is 2 μm, the sheet resistance value of the thin film resistance layer is 28 MΩ.
× 2 ÷ 1500 = 3.73 × 10 ⁴ Ω / □ = 37.3k
Ω / □ Further, when the number of metal layers is 13 and the number of thin film resistance layers is 14, the resistance value per thin film resistance layer is 140 MΩ ÷ 14 = 10 MΩ.

Assuming that one thin film resistance layer has a length of 1.5 mm and a width of 2 μm, the sheet resistance value of the thin film resistance layer is 1
0MΩ × 2 ÷ 1500 = 1.33 × 10 ⁴ Ω / □ = 1
It becomes 3.3 kΩ / □. Thus, in the withstand voltage structure of the present invention, the sheet resistance value of the voltage-holding polysilicon is
By increasing the number of metal layers, it is possible to reduce the level to an easily realizable level.

However, if the number of metal layers is increased,
The width of the thin-film resistance layer connected to the metal layer becomes narrower, processing of the thin-film resistance layer becomes difficult, and the sheet resistance value needs to be significantly reduced. Therefore, the sheet resistance value of a practical thin film resistance layer is 10 kΩ / □ or more,
It is 50 kΩ / □ or less. If it exceeds 50 kΩ / □, the variation of the sheet resistance value in the thin film resistance layer becomes large,
Not practical.

The range of the sheet resistance value is a range in which the impurity concentration can be sufficiently secured by the ion implantation method or the like. In this way, the metal layers 3, 4, 5, 6 and the thin film resistance layer 7,
When the withstand voltage structure of the first embodiment in which 8, 9, 10, 11 are combined is adopted, a high sheet resistance value of several MΩ / □ is not required, and a semiconductor having a complicated and long peripheral length such as a high withstand voltage IC. Also in the device, the layout and the resistance value setting can be facilitated, and the high breakdown voltage of the semiconductor device can be achieved.

When the withstand voltage classes are the same and the current capacities are different, it is not necessary to change the sheet resistance value of the thin film resistance layer, so that the withstand voltage structure can be easily designed. 7 to 12 show a semiconductor device manufacturing method according to the first embodiment,
It is a principal part manufacturing process drawing shown in process order. This main part manufacturing process diagram is a view corresponding to the main part sectional view of FIG. 2.

First, on the p substrate 21, n regions 22, 23,
The p regions 24 and 25 and the Poffset region 26 are formed by ion implantation and thermal diffusion, and then the selective oxide films 27 and 2 are formed.
8 is formed (FIG. 7). Next, a gate oxide film is formed at a location not shown. In this gate oxide film, the oxide film 41 is also formed in a place other than the place where the gate is formed. Polysilicon 42 is formed on the oxide film 41 and the selective oxide film 27, and in order to control the resistance value of the polysilicon 42 in the portions to be the thin film resistance layers 7, 8, 9, 10, 11. Ions 43 of B or a compound of B (BF ₂ etc.) are implanted. This dose amount is determined so that the sheet resistance value of the polysilicon 42 is about 10 to 50 kΩ / □ as described above (FIG. 8).

Next, the polysilicon 42 is patterned by ordinary exposure and etching techniques to form thin film resistance layers 7, 8, 9, 10, 11 (FIG. 9). Next, by coating the photoresist 44 and performing selective As ion implantation 45 by exposure and etching techniques,
On the surface layer of the n region 23, an n ⁺ region 29 for making contact with a metal layer described later is formed (FIG. 10).

Next, the photoresist 44 is removed, a new photoresist 46 is coated, and selective BF ₂ ion implantation 4 is performed by exposure and etching techniques.
By carrying out step 7, p ⁺ regions 31, 32, 3 for making contact with a metal layer described later are formed on the surface layers of the thin film resistance layers 7, 8, 9, 10, 11 made of polysilicon.
3, 34 and 35 are formed, and p ⁺ regions 36 and 37 for making contact with a metal layer described later are formed on the surface layers of the p regions 24 and 25 (FIG. 11). Although these regions are formed by using the oxide film 41 as a screen oxide film, the oxide film 41 can be removed and the thermal oxide film can be formed again before forming these regions.

Next, after forming interlayer insulating films 13 and 14 such as PSG (phosphorus glass film), the high potential side electrode 1 and the metal layers 3, 4, 5 and 6 are formed by exposure and etching techniques.
Then, a contact hole for making contact with the low potential side electrode 2 is formed, a metal such as Al is sputtered on the entire surface, and patterning is performed by an exposure and etching technique to form the high potential side electrode 1, the metal layers 3, 4 5, 6 and the low potential side electrode 2 are formed (FIG. 12).

Further, a passivation film (not shown) on the surface is formed and patterned to complete the process. First of the above
Although the embodiments have described the breakdown voltage structure of the horizontal planar semiconductor device, in the case of the vertical semiconductor device described in the next embodiment, the depletion layer expands laterally from the active region of the chip. Then, the method of connecting the high potential side electrode and the low potential side electrode by the thin film resistance layer and the loop-shaped metal layer (conductive film layer) used in the first embodiment is very effective.

FIG. 13 shows a semiconductor device according to a second embodiment of the present invention, in which FIG. 13A is a plan view of an essential part and FIG. 13B is a sectional view taken along line MM in FIG. FIG. First
The difference from the embodiment is that the loop-shaped metal layers 3, 4,
The interlayer insulating film 13 under 5 and 6 is opened, and the selective oxide film 27 is formed.
The point is that the convex portion 48 is provided on the metal layer so as to reach the top. By doing this, the loop-shaped metal layers 3, 4, 5,
The potential of 6 can be effectively transmitted to the semiconductor surface below the selective oxide film 27 without passing through the interlayer insulating film 13. Since the potentials of the metal layers 3, 4, 5, and 6 are effectively reflected on the semiconductor surface, local electric field concentration is less likely to occur than in the semiconductor device of the first embodiment, and a stable high withstand voltage is secured. can do.

FIG. 14 is a sectional view showing the principal part of a semiconductor device according to the third embodiment of the present invention. The breakdown voltage structure of this semiconductor device is a planar structure, and is an example in which it is combined with a guard ring structure which is often used as a peripheral breakdown voltage structure for vertical devices and horizontal devices. This figure shows a cross-sectional view of the main part of the breakdown voltage structure portion. An n ⁺ layer 52 is formed on the back surface side of the n layer 51, and a p well region serving as a low potential region 53 is formed on the front surface side, and a p region 5 serving as a guard ring surrounding the low potential region 53.
4, 55, 56 and 57 are formed respectively, and a p region serving as a high potential region 58 is formed at the end portion of the chip. An active region (not shown) (for example, a region occupied by a gate portion and a source portion in MOSFET) is formed in the p-well region which becomes the low potential region 53. Low potential area 5
3 on the low potential side, and the electrode film 6 on the high potential region 58.
0 is formed. The back surface side electrode 61, which serves as a high potential electrode, and the electrode film 60 are electrically connected to each other at the dicing surface 62.

Thin-film resistance layers 7, 8, 9, 1 are formed on the oxide film 63.
0, 11 are formed, and the loop-shaped metal layers 3, 4, 5, 6 are formed on the inter-layer insulating film 13, and the electrode film 60 and the innermost metal layer 3, the metal layer 3 and the metal are formed. Layer 4,
The metal layer 4 and the metal layer 5, the metal layer 5 and the metal layer 6, and the outermost metal layer 6 and the low potential side electrode 59 are electrically connected by the thin film resistance layers 7, 8, 9, 10 and 11, respectively. It

Here, the back surface side electrode 6 which is the high potential side electrode
When the potential Vs is applied to 1, the potential Vs is applied between the low potential side electrode 59 and the electrode film 60, and the thin film resistance layers 7, 8, 9,
Leakage current flows in 10 and 11, and a uniform potential distribution is formed in the loop-shaped metal layers 3, 4, 5, and 6, and the electric field due to this potential distribution concentrates in the depletion layer in the semiconductor. To maintain the breakdown voltage. In the figure, the loop-shaped metal layers 3, 4, 5, and 6 are arranged on the guard ring, but they are not necessarily arranged on the guard ring.

[0043]

According to the present invention, the first electrode and the second electrode which are electrically connected to the high potential region and the low potential region on the semiconductor substrate.
An electrode is provided, a plurality of loop-shaped conductive film layers are formed between the first electrode and the second electrode around the first electrode, and a thin film resistance layer is formed between the first electrode and the loop-shaped conductive film layer. When a voltage is applied between the first electrode and the second electrode by electrically connecting the loop-shaped conductive film layers to each other and between the loop-shaped conductive film layer and the second electrode, the loop-shaped conductive film layer is formed. Since the potential distribution between the first electrode and the second electrode can be linearly reduced from a high potential to a low potential in fine steps, a uniform potential distribution is formed inside the semiconductor substrate. It is possible to obtain a semiconductor device in which electric field concentration hardly occurs and the breakdown voltage is high.

Further, the shape of each thin film resistance layer is made long and thin to increase the resistance value, so that the sheet resistance value of the thin film resistance layer itself is controlled to a low resistance level. Is possible. Further, even in a semiconductor device having a long peripheral length such as a high withstand voltage IC having a complicated withstand voltage structure, the withstand voltage structure can be easily designed by combining the thin film resistance layer and the loop-shaped conductive film layer.

Also, when designing elements having the same breakdown voltage but different peripheral lengths, the breakdown voltage structure can be designed without changing the width or length of the thin film resistance layer.

[Brief description of drawings]

FIG. 1 is a semiconductor device according to a first embodiment of the present invention,
(A) is a main part plan view, (b) is an enlarged plan view of part A of (a)

FIG. 2 is a cross-sectional view of a main part of the semiconductor device according to the first embodiment of the present invention, taken along line XX in FIG.

FIG. 3 is a cross-sectional view of a main part of the semiconductor device according to the first embodiment of the present invention, taken along the line YY in FIG.

FIG. 4 is a cross-sectional view of a main part of the semiconductor device according to the first embodiment of the present invention, taken along the line ZZ in FIG.

FIG. 5 is a cross-sectional view of a main part of the semiconductor device according to the first embodiment of the present invention, taken along line MM in FIG.

6A and 6B show a cross-sectional view and a potential distribution of the main part of the semiconductor device of FIG. 1, FIG. 6A shows a cross-sectional view of the main part of FIG. 2, and FIG. 6B shows a potential distribution of the loop-shaped metal layer of FIG. Figure

FIG. 7 is a manufacturing process diagram of main parts of the semiconductor device according to the first embodiment.

FIG. 8 is a manufacturing step diagram of the main part of the semiconductor device of the first embodiment, following FIG. 7;

FIG. 9 is a manufacturing step diagram of the essential part of the semiconductor device of the first embodiment, following FIG. 8;

FIG. 10 is a manufacturing step diagram of a main part of the semiconductor device of the first embodiment, which is subsequent to FIG. 9;

FIG. 11 is a manufacturing step diagram of the essential part of the semiconductor device of the first embodiment, following FIG. 10;

FIG. 12 is a manufacturing step diagram of the essential part of the semiconductor device of the first embodiment, which is subsequent to FIG. 11;

FIG. 13 is a semiconductor device of a second embodiment of the present invention,
(A) is a plan view of a main part, (b) is a cross-sectional view of the main part taken along line MM of (a)

FIG. 14 is a sectional view showing the principal part of a semiconductor device according to a third embodiment of the present invention.

FIG. 15 is a cross-sectional view of an essential part of a structure in which a Double RESURF structure and a resistive field plate structure are combined.

FIG. 16 is a diagram showing the spread of a depletion layer inside a semiconductor.

FIG. 17 is a semiconductor device having a spiral thin film resistance layer disclosed in Japanese Patent No. 3117023.

FIG. 18 is a plan view of an essential part of a high breakdown voltage IC having a complicated breakdown voltage structure of a planar pattern.

[Explanation of symbols]

1 High-potential side electrode 2 Low-potential side electrode 3-6 Metal layers 7-11 Thin film resistance layer 12 Contact hole 13, 14 Interlayer insulating film 21 p Substrate 22 Nwell region 23 n region 24, 25 p region 26 Poffset region 27, 28 Selective oxide film 29 n ⁺ regions 31 to 37 p ⁺ region 38 back surface side electrode 41 oxide film 42 polysilicon 43, 47 ion implantation (BF ₂ ) 44, 46 photoresist 45 ion implantation (As) 48 convex portion 51 n region 52 n ⁺ region 53 low potential region 54 to 57 guard ring (p region) 58 high potential region 59 low potential side electrode 60 electrode film 61 back side electrode 62 dicing surface 63 oxide film 71 high potential side region 72 breakdown structure 73 low potential Side region 74 Gate / source electrode 75 Drain electrode

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F038 AR09 AV06 BH02 BH09 BH15                       EZ20                 5F140 AA00 AA25 AB10 AC23 BA01                       BD05 BF01 BF04 BG32 BH18                       BH30 BJ01 BJ05 BJ25 BK13                       BK29 CA03 CB01 CB07 CB08                       CC05 CD09 DA08

Claims (9)

[Claims] 1. A semiconductor device having a first electrode and a second electrode formed separately from each other on an insulating film formed on a semiconductor substrate, wherein the first electrode and the second electrode are formed so as to surround the first electrode. A plurality of loop-shaped conductive film layers are formed on the insulating film between the first electrode and the second electrode, and between the first electrode and the loop-shaped conductive film layer, the loop-shaped conductive film layers are mutually connected. And a thin film resistance layer electrically connecting the loop-shaped conductive film layer and the second electrode to each other, respectively. 2. A first insulating film formed on a semiconductor substrate,
A second insulating film formed on the first insulating film, the first electrode and the second electrode formed on the second insulating film, separated from each other, and surrounding the first electrode, A plurality of loop-shaped conductive film layers formed on the second insulating film between the first electrode and the second electrode, and the loop-shaped conductive film between the first electrode and the loop-shaped conductive film layer. A thin film resistance layer formed on the first insulating film, electrically connecting the loop-shaped conductive film layers and the second electrode to each other. Semiconductor device. 3. The semiconductor device according to claim 2, wherein a bottom portion of the loop conductive film layer is separated from the thin film resistance layer and is in contact with the first insulating film. 4. The semiconductor device according to claim 1, wherein the loop conductive film layer is formed of a metal film. 5. The semiconductor device according to claim 1, wherein the thin film resistance layer is made of polysilicon. 6. The sheet resistance value of the thin film resistance layer is 1 × 1.
^4. The semiconductor device according to claim 1, wherein the semiconductor device has a resistance of 0 ⁴ Ω / □ or more. 7. The sheet resistance value of the thin film resistance layer is 5 × 1.
0 ⁴ Ω / □ or less, Claims 1 and 2,
7. The semiconductor device according to any one of 3 and 6. 8. The semiconductor substrate is of the first conductivity type, and a first region of the first conductivity type and a second region of the second conductivity type are formed separately on a surface layer of the semiconductor substrate. A third region of the second conductivity type is formed on the surface layer of the semiconductor substrate between the region and the second region so as to be separated from the first region and contact the second region. 4. The semiconductor device according to claim 1, wherein the first region is connected to the first electrode, and the second region is connected to the second electrode. 9. The semiconductor substrate is of a first conductivity type, and a first region and a second region of a second conductivity type are formed separately from each other on a surface layer of the semiconductor substrate, and the first region and the second region are separated from each other. In the surface layer of the semiconductor substrate between the second regions, a fourth region of the second conductivity type is provided apart from the first region and the second region,
It is formed in a loop shape so as to surround the first region, the first region and the first electrode are connected, and the second region and the second electrode are connected. 3. The semiconductor device according to any one of 3 above.