JPS6214470A - Vertical type semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to miniaturize and highly integrate cells and also effectively prevent the punch-through phenomenon by forming the third semiconductor layer of reverse conductive type with lower density of impurity than that of the first semiconductor layer deeply. CONSTITUTION:A semiconductor film 6 is formed on the first insulative film 5a formed on the main surface of a semiconductor substrate and is underetched to form a semiconductor film pattern 6, and an overhang-shaped mask is formed at the same time. Then, reverse conductive type ions with low density are deeply implanted into the substrate through the overhang-shaped mask so as to deeply form the reverse conductive type, third semiconductor layer 11, and further, reverse conductive type ions are shallowly implanted with the pattern 6 as a mask to shallowly form the first conductor layer 4. And one conduction type ions are implanted to form the one conduction type, second semiconductor layer 8. The second insulation film 5d is formed, and an opening 10a is selectively formed to partially expose the first semiconductor layer 4 and the second semiconductor layer 8 so that a metallic electrode film 9 is formed.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a vertical semiconductor film device for the purpose of switching or amplification and a manufacturing method thereof, and particularly relates to technology for miniaturization and high performance. .

(Prior art) Among MIS type semiconductor film devices, MOSFETs in particular were traditionally considered to be low voltage and low power devices, but with recent developments in semiconductor manufacturing technology and circuit design technology, high voltage and high power devices have been developed. It has become possible to design it, and it has now secured its place as a power device.

Typical examples of such high-voltage power MO8FETs are ■offset gate structure, ■V-Groove or jl-GroOVe structure, and ■DSA (DiHus
ion Self-Alignment) structure, etc., but among these, the conventional DSA structure power MO8FET (hereinafter referred to as DS) is advantageous in terms of manufacturing technology and high performance.
FIG.
) and (b), and the cross-sectional structures in the sequential manufacturing steps are shown in FIGS. 9(a) to (f). However, the source electrode is omitted in FIG. 8(a).

DSA MOS forms a channel by double diffusion, and the channel region is formed through the same diffusion window surrounded by a lattice-shaped gate polycrystalline silicon film 6 formed through a gate oxide film 5a. Impurity diffusion (p
It is characterized in that a semiconductor layer 4) and an impurity diffusion (n+ type semiconductor 118) for forming a source region are performed. Since the channel length is determined by the difference in diffusion depth between the p-type semiconductor layer 4 and the n0-type semiconductor layer 8, it can be formed extremely short, several microns or less. The source electrode 9 formed on the insulating film 5d is in ohmic contact with both the n-type semiconductor layer 8 forming the source region and the p-type semiconductor layer 4 (or p-type semiconductor 113) forming the channel region. .

Generally, the gate electrode has a lattice shape or a stripe shape, and the lattice shape is shown here. An n-type semiconductor substrate 1 is a drain region, and an n-type epitaxial growth layer 2 is deposited thereon to form an n-on n-type structure. A drain electrode (not shown) is formed on the back surface of the chip, and when a positive voltage is applied between the gate and source to turn on the channel, current flows vertically from the substrate 1 and passes through the channel length 114 to the source region. Flows into 8. Incidentally, the broken lines in FIG. 8(a) indicate the contours of the openings in the polycrystalline silicon film pattern 6 constituting each cell.

Next, using FIG. 9 (a > to (f)), the conventional DSA
The manufacturing process of MOS will be explained. 0+ type half board 1
An n-type epitaxial growth layer 2 is formed on top with a specific resistance of 10, for example.
~25Ω mark, 30~60μ-thick bond, p from the surface
A ten-shaped semiconductor layer 3 is formed. Excellent, gate oxidation Ill
Figure 9 (a) shows how 5a was formed to a thickness of approximately 1000 mm.

Next, a polycrystalline silicon film 6 is deposited to a thickness of, for example, 6000 nm, selectively buttered, and ions are implanted using this polycrystalline silicon film pattern as a mask to form a p-type semiconductor 114 that will become a channel region. Form in a self-consistent manner. This situation is shown in FIG. 9(b).

Subsequently, an opening is selectively formed in a portion where an n0 type semiconductor layer 8, which will become a source region, is to be formed using photoresist using a photo-etching technique, as shown in FIG. 9(C).

Next, the n-type semiconductor layer 8 and oxide film 5b, which will become the source region.
(shown in FIG. 9(d)), and then PSG (phospho 5 ilicat) was formed thereon by CVD method.
eGlass) l! 5c 800OA thick 1.
: 1 ftlL is shown in Figure 9<8). Figure 8 (
In b), this oxide film 5b and PSGII 50 are combined to form a second
It is shown as an insulating film 5d.

Next, the oxide film 5b and the PSG
By forming an electrode extraction opening 10a in the film 5C and forming an aluminum (fl) l pole 9, the source-drain breakdown voltage VDSS is approximately 200 to 600 V (7) D
SA MOS FET is completed.

This situation is shown in FIG. 9(f).

In general, MOS FETs have the advantage of high-speed switching because there is no accumulation of minority carriers, and high thermal stability because the drain current has a negative temperature coefficient, so they can be used as equal-power devices, but bipolar transistors Compared to this, since it is a majority carrier element, there is a significant trade-off between high withstand voltage and high power, and the substrate resistance layer required for high withstand voltage directly leads to an increase in saturation voltage, resulting in a large on-resistance for the same chip area. There was a drawback. In order to solve this problem, it is necessary to reduce the resistance of the power path of the FET, especially the drain resistance. In other words, the question is how to increase the area efficiency of the drain, and for this purpose, it is necessary to design the best pattern by making full use of microfabrication technology. A DSA MOS FET is generally employed as a structure that satisfies these requirements.

However, the pattern design of conventional DSA MOS FETs is not necessarily an optimal design. Various ideas are needed for the polycrystalline silicon film pattern and the shape of the channel region so that the width of the current path, that is, the channel width, which is the peripheral length of the channel, can be increased or the channel length can be shortened within the limited silicon chip area. It is. By increasing the channel width, it is possible to increase the drain current, and in addition, a large mutual conductance of 9 m can be obtained in the large current region.

Since these are the biggest factors that make it possible to reduce on-resistance, the biggest goal was how to increase the channel width within a limited area.

Therefore, when we examine the gate polycrystalline silicon patterns of high-voltage power MO8FETs conventionally used in switching power supplies, etc., we find that most of them exhibit a square lattice shape as shown in Figure 8(a). There is.

In the plan view of FIG. 8(a), the length of the gate polycrystalline silicon film from the edge of the open pattern of the polycrystalline silicon film 6 of the cell to the edge of the open pattern of the cell adjacent vertically and horizontally is 1. If the length between diagonally adjacent cells is 12, then β2 is 1. It is f7- times longer than . n+ type source region 8 within a defined area
In order to integrate a large number of gate polycrystalline silicon 116, it is desirable that the above length λ and J22 be equal. That is, since the channel region 4 exists along the pattern edge of the gate polycrystalline silicon BI6, it is desirable to set it to 1l-12 in order to obtain a large channel width.
> fl l, the polycrystalline silicon film 6 occupies an extra area corresponding to 2-J2+. This increases the gate area and increases the drain-gate capacitance, which impedes switching speed.

In addition, it is well known that each pattern is generally miniaturized to increase the channel width, and as a result, the gate polycrystalline silicon film pattern and source region are reduced, and the channel width increases accordingly. I can figure it out. However, in the conventional gate polycrystalline silicon pattern having a rectangular lattice shape, the source 'Ift pole opening tends to be too large in proportion to the drain current capacity. Although miniaturization allows the formation of a large number of independent channel regions, resulting in an overall increase in channel width, the channel width within one cell becomes smaller. In other words, when operating as a MOS transistor under the same conditions, even though the smaller the channel width, the smaller the current capacity, there are many electrode extraction openings in the source region formed in the cell. Become.

As is well known, a MOS FET has less thermal runaway than a bipolar transistor, and the current density obtained from one cell area is small, so there is no need for an unnecessary opening for the source electrode.

It is necessary to use this unnecessary portion to form more channel regions and to arrange patterns to increase the channel width. Therefore, it is important to devise a pattern to reduce the area of the source electrode extraction opening and effectively increase the channel width accordingly.

In terms of performance, especially with regard to improving switching speed, it is important to reduce the capacitance between the gate and drain. Typical methods for achieving this are increasing the thickness of the gate oxide film and reducing the area occupied by the gate polycrystalline silicon film pattern. However, the threshold voltage Vth, which is one of the MOS operating characteristics, and the mutual conductance □
For these reasons, there is a limit to increasing the thickness of the gate oxide film. Therefore, another typical method is to reduce the area occupied by the gate polycrystalline silicon film pattern on the gate oxide film. The easiest way to implement this method is to make the gate polycrystalline silicon film pattern thin. However, making it thinner has the drawback of increasing resistance and slowing down switching speed.

Most conventional gate electrode materials are polycrystalline silicon films or high melting point metal films such as molybdenum films, and these materials are used as multilayer wiring material films because they are resistant to high-temperature processes.

For this reason, in high power DSA MOS FETs, the typical gate 1! A polycrystalline silicon film is used as the electrode material, and has a two-layer electrode structure with an insulating film interposed between it and the source electrode A°C film. Moreover, in order to increase the channel width, the gate polycrystalline silicon film pattern is designed to be thin and extremely long. Within a limited silicon chip, the relationship between the length of the channel width and the wiring resistance of the gate polycrystalline silicon film pattern is determined in order to lower the on-resistance. Designing the channel width to be long increases gate resistance, which has the disadvantage of slowing down switching speed. Therefore, in the past, efforts were made to sacrifice the channel area within the chip, provide several highly conductive /l stripe patterns, and connect these to the gate polycrystalline silicon film in an effort to reduce gate resistance. Ta. However, since the gate AJ2 is a polycrystalline silicon gate with a length of several hundred to several thousand microns between the two electrodes,
Gate resistance remains high.

On the other hand, as another method of lowering the gate resistance, see Figure 10 (
As shown in a) and (b), there is a comb-shaped electrode structure in which a gate AA pattern and a source An pattern are alternately arranged on a gate polycrystalline silicon film pattern with an insulating film interposed therebetween.

In FIG. 10, the same parts as those shown in FIG. 8 are designated by the same reference numerals. This semiconductor film device having a comb-shaped electrode structure has an n-type epitaxial layer 2 grown on an n-sized semiconductor substrate 1, and has a first insulating layer 11u5a on its main surface.
A patterned polycrystalline silicon film 6 is formed so as to have openings in a lattice shape through the polycrystalline silicon film 6, and a p-type first semiconductor 82 is formed in the openings of the polycrystalline silicon Ill6.

A portion of the main surface of the epitaxial layer 2 is covered with a first insulating layer 5a.
A p-type second semiconductor layer 4 is formed so as to overlap with the polycrystalline silicon film 6 via the first insulating layer J15a, and a p-type second semiconductor layer 4 is formed so as to partially overlap with the polycrystalline silicon film 6 via the first insulating layer J15a. A half-shaped third semiconductor layer 8 is formed, and a second insulating layer 1 is formed to cover the polycrystalline silicon film 6 and its opening.
15d is formed. Striped source and gate Aβ electrodes 9a and 9b are formed on this second insulating film, and the source/l electrode 9a is connected to an opening 10a in the second insulating film 5d and an opening in the polycrystalline silicon I[16]. The gate A°C electrode 9b is connected to the polycrystalline silicon film 6 through an opening 10b formed in the second insulating film 5d. There is.

(Problems to be Solved by the Invention) The semiconductor film device having the conventional comb-shaped electrode structure shown in FIG.
Considering the preferential treatment of the pattern by isotropically etching the film thickness of the J2 electrodes 9a and 9b, the source AJ211 pole 9a and the gate A (electrode 9b) must be separated by a certain distance. If you do not increase the pattern width or increase the cell area, the source/
Electrode separation between the L electrode 9a and the gate AJ2 electrode 9b becomes extremely difficult due to photolithography, which limits miniaturization.In particular, the capacitance between the gate and the source increases, which in turn becomes a factor that hinders the improvement of switching speed. there were. On the other hand, the simplest way to lower the gate resistance is to increase the thickness of the gate polycrystalline silicon 116, which is slightly effective. 9b has a drawback that it tends to break off at the edge of the opening formed in the polycrystalline silicon 116.

Another factor for improving switching speed is to narrow the channel length. This channel length is determined by the difference in diffusion depth between the p-type semiconductor layer 4 in the channel region and the source n+-type semiconductor layer 8.

However, when considering switching speed, the following conditions must be met. Generally, the drain current flows from the source n-type semiconductor 18 through the p-type semiconductor WJ4 in the channel region to the n-type epitaxial layer 2 in the vertical direction.
It flows to the drain region of the ten-shaped semiconductor substrate 1 and is taken out from the drain MFi on the back surface of the substrate. Therefore, the drain current flows between the p-type semiconductor layers 4 forming the channel region. Therefore, the p-type semiconductor 114 is the gate polycrystalline silicon 11! Since they are formed facing each other on both sides of I6, if the p-type semiconductor layer is formed deeply,
The flow path for the drain current becomes narrow, and the current path has a resistance valve, which in turn causes an increase in on-resistance. In addition, p forming the channel region
By forming the type semiconductor layer 4 deeply, firstly, the area overlapping with the gate polycrystalline silicon 16 increases. As is well known, the gate insulating film 5a has conventionally a thickness of 500λ to 1200λ.
Therefore, as a matter of course, the capacitance between the gate and source increases, and switching
It is obvious that this will hinder speed. Therefore, the p-type semiconductor layer 4 forming the channel region is formed as shallowly as possible, and the source n-type semiconductor layer 8 is formed as shallowly as possible.
By forming the channel to be shallow, it becomes possible to realize an O8AMO8FET with a narrow channel length and a high switching speed.

However, by forming the p-type semiconductor 114 forming the channel region shallowly and narrowing the channel length, the following new problem arises.

First, when MO8 is operated, a depletion layer spreads from the p-type semiconductor layer 4 forming the channel region to the n-type epitaxial layer 112 side of the drain region. At the same time, a depletion layer also spreads within the p-type semiconductor layer 4.

This depletion layer spreads more easily as the concentration of the semiconductor layer or the diffusion layer becomes lower, and as the drain voltage becomes higher. Therefore, as a matter of course, a large amount of the depletion layer spreads to the n-type epitaxial layer 21111 in the drain region, which has a low concentration. However, in the case of an MO8 type FET having a DSA structure, since the channel regions 4 are formed to face each other in the cell portion, the depletion layers of both regions are spread close to each other, and the channel regions 4 are formed to face each other in the cell portion, so that the depletion layers of both regions are spread close to each other, and the channel regions 4 are formed to face each other in the cell portion. Since they collide in the nearby drain region, there is no obstacle to obtaining a large source-drain breakdown voltage. On the other hand, on the p-type semiconductor H4 side, by increasing the drain voltage higher and higher, the depletion layer in the p-type semiconductor layer 4 forming the channel region expands more and more, and reaches the source n-type semiconductor [18]. . This is the so-called punch-through phenomenon. At this point, the voltage between the source and drain has already broken down. In other words, since the channel length is narrow, the depletion layer is the n+ type semiconductor layer 8.
Since the voltage reaches the voltage immediately, the voltage breaks down at a value smaller than the breakdown voltage determined by the bulk characteristics. In particular, in order to obtain a long channel width, the gate polycrystalline silicon film pattern must be miniaturized, and accordingly, the p-type semiconductor layer 4 constituting the channel must be formed by shallow diffusion. Naturally, thin and long patterns are formed between the gate polycrystalline silicon film patterns, so punch-through phenomenon is likely to occur in such portions.

In addition, as a method to make the bunch-through phenomenon less likely to occur,
In the conventional DSA MOS FET, a p-sized semiconductor B3 is formed within the cell by photoetching technology. However, this method has the following drawbacks. First, with photolithography technology,
In order to align with the p-type semiconductor 113 and form the pattern of the gate polycrystalline silicon film 6, the p-type semiconductor WJ4 in the channel region is formed in a self-aligned manner by the pattern of the gate polycrystalline silicon 16; The positional relationship of the p-type semiconductor layer 3 that is not formed in a self-aligned manner becomes inaccurate, and the long and short portions of the p-type semiconductor layer (channel region) 4 narrowed by the n-type semiconductor layer 8 become the n-type semiconductor layer 3. It is formed under 11i8. In this case, bunch-through is likely to occur in the part where the narrow p-type semiconductor layer 4 is formed long, and conversely, in the short part, a part of the highly doped p-type semiconductor layer 3 reaches the channel p-type semiconductor layer 4 and MO8 type A transistor characteristic that affects the threshold voltage value. Furthermore, when performing the alignment U, it is necessary to form a pattern taking alignment errors into consideration.
Another drawback is that the cell area increases and the channel width decreases accordingly. Furthermore, since the p-type medium semiconductor layer 3 is formed by alignment using photolithography, the number of photo-etching steps is increased, which in turn impedes productivity improvement.

Furthermore, in order to improve the area utilization efficiency of the chip and obtain a long channel width, the opening pattern of the gate polycrystalline silicon film is connected to two or more enlarged portions with a large area and a narrow connection connecting the adjacent enlarged portions. The present inventor proposes a structure having a section. In such a semiconductor film arrangement, an elongated channel region is formed along the edge of the connecting portion, so that the channel width can be increased, but there is a drawback that punch-through is particularly likely to occur in this elongated channel region.

The present invention has been made in view of the above-mentioned points, and even if the width of the gate polycrystalline silicon pattern is made as equal as possible, and the overall pattern is made finer, the source electrode extraction opening can be optimized according to the current capacity. so that you can get
Roughly speaking, the p medium semiconductor layer 3 and the n medium semiconductor layer are formed in a self-aligned manner in the source electrode extraction opening! f
18 is electrically connected by the metal electrode film 9, the purpose is to miniaturize the aperture, it is possible to arrange an appropriate pattern in accordance with the purpose, and to obtain benefits from these effects. This effectively forms a channel region in the extra area, prevents the bunch-through phenomenon especially in elongated channel regions, makes it possible to narrow the channel length, reduces the photo-etching process, lowers the on-resistance, The present invention provides a vertical semiconductor film device and a method for manufacturing the same, which can improve device performance such as mutual conductance, switching speed, etc., reduce chip area, and improve productivity.

(Means for Solving the Problems) A vertical semiconductor film arrangement according to the present invention includes a semiconductor substrate of one conductivity type, and a semiconductor film or conductor formed on the main surface of the semiconductor substrate via a first insulating film. a film pattern, and a film pattern of an opposite conductivity type formed on the main surface of the semiconductor substrate within the opening of the pattern at a position where the film pattern partially overlaps with a part of the semiconductor film or conductor film pattern via the first insulating film. a second semiconductor layer of one conductivity type formed in the first semiconductor layer so as to partially overlap with a part of the semiconductor film or conductor film pattern; a third semiconductor layer of the opposite conductivity type formed in the opening with a lower impurity concentration of 81 degrees and deeper than the first semiconductor layer, at equal intervals along the edge or until reaching the same position as the edge; , a second insulating film formed to cover the semiconductor film or the conductive film and having an opening;
A metal electrode film is provided on the second insulating film so as to include the opening.

Roughly speaking, the manufacturing method of the present invention includes the steps of forming a Wg1 film on the main surface of a first semiconductor substrate of one conductivity type, forming a semiconductor film or a conductor film on this first insulating film, and then forming a semiconductor film or a conductive film on the first insulating film. forming a mask, and then under-etching the semiconductor film or conductive film through this mask to form a semiconductor film or conductive film pattern, and at the same time forming an overhang-like mask; A step of deeply implanting ions of the opposite conductivity type into the semiconductor substrate at a low concentration through the semiconductor substrate to form a third semiconductor layer of the opposite conductivity type deeply, and after removing the mask, forming a semiconductor film or conductor film pattern. A step of shallowly implanting ions of the opposite conductivity type at a high concentration using the semiconductor film or conductor film pattern as a mask to form a shallow first semiconductor layer of the opposite conductivity type; and implanting ions of one conductivity type using the semiconductor film or conductor film pattern as a mask. forming a second semiconductor layer of one conductivity type in the first semiconductor layer; forming a second insulating film to cover the semiconductor film or the conductor film and its opening; selectively forming an opening in the film to partially expose the first semiconductor layer and the second semiconductor layer; forming a metal 'R' electrode on the second insulating film to cover the opening; It is characterized by comprising a process.

<Function> In the semiconductor film device of the present invention, the third semiconductor layer of the opposite conductivity type has a lower impurity concentration and is formed deeper than the first semiconductor layer, so that miniaturization and high integration of cells can be achieved. Not only is this possible, but also the punch-through phenomenon can be effectively prevented. Further, by forming the first semiconductor layer and the second semiconductor layer shallowly, the capacitance between the gate and the source can be reduced, the mutual conductance 9m can be increased, and the switching speed can be improved. Furthermore, in the semiconductor film device of the present invention, the channel width can be increased within a predetermined chip area, and the volume between the gate and drain can be reduced by reducing the area occupied by the polycrystalline silicon film.

Therefore, a large drain current can be obtained and at the same time a fast switching speed can be obtained.

In particular, as in the embodiment described later, the opening of the polycrystalline silicon film pattern is divided into an annular portion surrounding the independent pattern portion, an end portion located symmetrically on both sides of this annular portion, and the annular portion and the end portion. By arranging a plurality of such apertures so that the end portions of adjacent apertures are arranged interdigitally, the utilization efficiency of the chip area can be significantly improved. As a result, the above-mentioned effects can be exhibited even more effectively.

(Example) The present invention will be specifically explained below using examples.

FIGS. 1(a) and (b) are a plan view and a cross-sectional view of a DSA MOS FET which is an embodiment of the present invention. In FIG. 1(a), part of the Aλ electrode film and insulating film are cut away. be.

In this device, an n-type epitaxy cell growth layer 2 is provided on an n-type semiconductor substrate 1, and an insulating oxide film (a polycrystalline silicon GL (semiconductor film A p-type semiconductor layer 3 doped with impurities of the opposite conductivity type at a high concentration is provided in the epitaxial layer 2 within the opening of this pattern. , a p-type semiconductor layer (a first semiconductor layer) doped with impurities of the opposite conductivity type at a low concentration is formed at a position partially overlapping with a part of the polycrystalline silicon film pattern 6 via the first insulating film 5a. 4) are formed shallowly in the openings of the polycrystalline silicon film pattern 6, with equal intervals maintained along the edges of the pattern, and p-type semiconductor layers having a lower impurity concentration than the p-type first semiconductor layer 4. The semiconductor Il! (third semiconductor layer) 11 is formed deeper than the p-type semiconductor layer 4, and the p-type first semiconductor W4
An n0-type semiconductor layer (second semiconductor layer) 8 is formed on the surface of the polycrystalline silicon layer 4 at a position partially overlapping with a part of the conductive film pattern 6 via the first insulating layer 5a. An insulating oxide film (second insulating film) 5d is formed to cover the silicon film pattern 6, and a source eight electrode film (metallic bridge i19) is formed on this insulating film.
The 2W1 pole 1119 is ohmically connected to the first and second semiconductors B4 and 8 through the source electrode extraction opening 10a in the cell formed in the insulating film 5d.

The planar shape of the pattern of the p-type semiconductor layer 4 surrounded by the polycrystalline silicon film pattern 6 and formed on the surface of the n-type epitaxial layer 2, that is, the open pattern of the polycrystalline silicon 116, is shown in FIG. As shown, octagonal enlarged portions 4A and 4B.

4C and narrow connecting portions 4D and 4E connecting adjacent sides of these three hexagonal patterns. Here, the distance J21 between each side of horizontally and vertically adjacent cells and the distance J22 between each side of diagonally adjacent cells are (,÷f!,2.Also, the cell are arranged so that the central octagonal enlarged portion 4B of the vertically adjacent cell is located between the octagonal enlarged portions 4A and 4C located at opposite ends of the horizontally adjacent cells. It is.

In order to improve the performance of the vertical field effect transistor of this example, the gate polycrystalline silicon film pattern is modified, the channel width is lengthened, and the current capacity per unit area is increased. . This will be explained by comparing the dimensional relationship with a conventional device.

A plan view of the conventional example in Fig. 8 (a) and Fig. 1 (a)
The same design rule is used for the magnification of the plan view of
Set the width (7) and XL as 160 μm.

In FIG. 8(a), there are 3×4−12 source electrode extraction openings 10a, and the length of one side of one cell is lo.
+ (=LO2) is 20μ, so cell 1
The channel width (total sound quality of one cell) is 80μ, and the total channel width within this broken line frame is 960μ.

On the other hand, in FIG. 1(a), the hexagonal ends 4A, 4
The length of the straight side LO3 of B and 4C is 10 μm. The length of the side 1o 4 (-(T/2LO3)) which is inclined at 45° is approximately 7 μ-, and the length of one side of the connecting portions 4D and 4E is LO
Since s is 20 μm, the channel width of one cell is approximately 244 μ−, and the total channel width in the pattern area within the broken line is approximately 1132 μ−. In this way, the channel width of this embodiment is larger than that of the conventional one,
Moreover, the difference becomes larger as the number of cells increases or as the pattern area becomes larger.

In this way, according to this embodiment, the channel width can be significantly increased. The reason for this is that by effectively using diagonal lines, f+<A2 in the plan view of Fig. 8(a).
This is because the relationship is set to f + * f 2 in FIG. 1(a). Therefore, by arranging the cells so that they are alternately shifted by bits, it is possible to integrate the cell pattern arrangement in the center as a whole despite the same design rule, which allows for more cells than in the conventional method. It becomes possible to accumulate

Next, when miniaturization progresses, especially when cell and gate polycrystalline silicon film patterns are downsized, conventional semiconductor film layouts require source electrode extraction openings at intervals of several microns. In other words, the source electrode extraction opening has the drawback of being constrained by design rules. On the other hand, this embodiment has the advantage that the interval between the source electrode extraction openings can be arbitrarily designed, and the channel width does not decrease.

From the above, in this example, an appropriate gate polycrystalline silicon film pattern is obtained so that the channel width can be increased within a defined chip area, and the cells corresponding to the openings of this gate polycrystalline silicon film pattern are By appropriately arranging the drain current, it is possible to obtain a large drain current, increase the mutual conductance axis in the large current region, increase the switching speed, reduce the on-resistance, and further reduce the chip area. The optimal pattern has been applied to reduce the size and improve productivity.

Next, configure the channel region in the center of the cell pattern.
Since the p-type semiconductor layer 11, which is deeper than the p-type semiconductor layer 4, is formed in a self-aligned manner, accurate and fine cells can be formed. In order to improve switching speed and on-resistance performance, even if the channel length is narrowed as much as possible, the p-type semiconductor layer 11 is deep and the gate polycrystalline silicon film 6 (or channel region) is Since it is formed in the center of the cell in a self-aligned manner, it is a p-type semiconductor! l! The p-type semiconductor layer 4 of the channel region is formed at equal intervals from 111. Therefore, it is possible to prevent non-uniformity of the threshold voltage due to a change in the concentration of the channel region due to misalignment of the Q-type semiconductor layer 11. Therefore, the punch-through phenomenon can also be prevented, and the p-type semiconductor layer 4 can be formed shallowly so that it partially overlaps the gate polycrystalline silicon film 6 formed on the extremely thin gate oxide film 5a. Since the area of the p-type semiconductor layer 4 is small, the capacitance between the gate and the source is reduced, and the source n+-type semiconductor layer 8 is also made shallow along with the p-type semiconductor layer 4, thereby increasing the mutual conductance 9m. It is possible. Since the p-type semiconductor layer 4, which becomes the channel, and the n-type semiconductor layer 8 form a shallow junction (Shal low Junction), the drain current flow path (n-type epitaxial Layer 2) is expanded, and the width of the gate polycrystalline silicon film pattern can be reduced accordingly.

Therefore, in order to particularly form a long channel width, it is preferable to make the openings (cells) of the gate polycrystalline silicon film pattern narrow and form a long and narrow channel region as a long pattern arrangement. Punch-through phenomenon can also be effectively prevented by forming the p-type semiconductor layer 11 deeper than the p-type semiconductor layer 4.

In the present invention, the p-type semiconductor layer 4 constituting the channel region has a pattern connecting portion 4 formed in an elongated manner.
In D and 4E, the depletion layer is also formed in a self-aligned manner in the center of the cell directly under the source n-type semiconductor layer 8, and the depletion layer is wider than the channel region in order to prevent a decrease in breakdown voltage due to the punch-through phenomenon. A deep ρ-type half layer 11 is formed with a low concentration and a low concentration. Since this p-type semiconductor layer 11 is formed in a self-aligned manner, the number of photo-etching steps is reduced by one compared to the conventional one. This is very effective for increasing productivity.

FIGS. 2(a), (b) and (C) are plan views of an O3A MOS FET which is another embodiment of the present invention;
and a perspective cross-sectional view, Aj21 in Fig. 2<a)
The electrode film is cut out, and in FIG. 2(C), the β electrode film and the second insulating film are cut out.

This device performs n-type epitaxial growth on a medium-sized semiconductor film substrate 1! li2 is provided, and this first semiconductor 1
! An insulating oxide film (polycrystalline silicon 1s (semiconductor film or conductor film) pattern 6 via a first insulating film>5a) is provided on the main surface of i2, and a reverse conductive film is formed in the epitaxial layer 2 within the opening of this pattern. p doped with a high concentration of type impurities
A medium-sized semiconductor 3 is provided. Further, in the opening of the polycrystalline silicon film pattern 6, a p-type semiconductor of the opposite conductivity type is located at a position partially overlapping with a part of the polycrystalline silicon film pattern 6 via the first insulating film 5a. (first semiconductor layer) 4 is provided in the opening of the polycrystalline silicon film pattern 6, with equal intervals maintained along the edge of the pattern, and with a higher degree of impurity than the p-type semiconductor layer 4. The low p-type semiconductor layer (third semiconductor layer) 11 is a p-type semiconductor ll! 4, and is formed at a position on the surface of the 11 semiconductor layer 4 and partially overlaps with a part of the semiconductor film or conductor film pattern 6 via the first insulating film 5a.
I (second semiconductor layer) 8 is formed, an insulating oxide film (second insulating film>56 is formed to cover the polycrystalline silicon film pattern 6, and on this insulating film, a source A11! electrode film ( the first metal m#1 film) 9a and the gate electrode film (second metal m#1 film) 9a;
Gold ffi'Fi electrode film) 9b is formed in a stripe shape. The source/l electrode film 9a is ohmically connected to the semiconductor layers 3 and 8 through the source electrode extraction opening 10a in the cell formed in the insulating film 5d, and the second/IM@electrode film 9b is formed in the insulating film 5d. The gate electrode is connected to the polycrystalline silicon film pattern 6 through the metal conductor extraction opening 10c as illustrated. The polycrystalline silicon model pattern 6 consists of a continuous lattice-like portion 6a and an independent island-like portion 6b, and the planar shape of the cell defined by these portions is an annular portion 12A surrounding the independent portion 6b. , two end portions 12B and 12C formed symmetrically with respect to the annular portion, and connecting portions 12D and 12E that connect the annular portion and these end portions. The contour shape of the end portions 12B and 12G is a polygon that is an integral multiple of 2, in this example a quadrilateral, and the contour shape of the annular portion 12A is also a polygon that is an integral multiple of 2, which is a quadrilateral in this example. The shapes of these end portions and the annular portion are not limited to quadrangles, but may also be octagonal, for example,
It can also be circular.

In this example, as shown in FIG. 2(a), the annular portion 12
A plurality of cells are arranged so that A is aligned, and the annular portions 12A of one row and the annular portions 12A of an adjacent row are shifted in pitch from each other, and the sequential end portions 12[3 of the rows are aligned.
and 12C, with the sequential end portions 12C and 12B of adjacent columns interdigitated. In this case, when focusing on the end portion 12B, the distances from the adjacent end portion 12C1 to the connecting portion 12E and the annular portion 12A are all approximately equal.

The second AJ2 electrode 119b constituting the gate electrode is the gate electrode extraction opening 10b formed in the second insulating film 5d.
The continuous portion 6a of the polycrystalline silicon film pattern is connected to the island-shaped independent portion 6b of the polycrystalline silicon pattern through the opening 10c formed in the second insulating film 5d at an intermediate position between the adjacent independent portion. It is connected to the. That is, the continuous portion 6 of the polycrystalline silicon film pattern
a and the independent portion 6b are interconnected via the second AJ2 electrode II 9 b. In this way, in this example, the first/first
The number of the l electrode 1119a and the second AA electrode 1119b is about ten or more.
The width of the 182nd electrode film 9a forming the source 8β electrode is the same as that of the 2nd AI electrode 1 forming the gate Aλ electrode.
It is wider than 19b.

As described above, in this embodiment, the polycrystalline silicon film pattern 6 is configured with a mesh-like continuous part 6a and an island-like independent part 6b, so that the channel width can be made roughly longer than in the above-mentioned embodiment. can do. That is, the gate electrode structure has a continuous mesh-like part and a plurality of independent parts surrounded by the mesh-like part, and these parts are covered with the second AJ2 electrode film 9 having excellent conductivity.
The configuration is such that they are connected at b. On the other hand, the source/l electrode film includes, at the end portions 12B and 12C inside the cell, the p-type semiconductor layer 3 that is electrically in contact with the p-type semiconductor layer 4 that constitutes the channel region, and the n-type semiconductor layer 3 that constitutes the source region. The first AJ2'l pole 11 is formed by exposing the ten-type semiconductor layer 8 on the surface.
19a.

These first and second AJ2 electrode films 9a and 9b are alternately arranged in a comb shape. In this way, the gate polycrystalline silicon pattern has a continuous mesh structure,
The greatest feature of this embodiment is that the source electrode and the gate electrode are made of a metal film such as AJ2 having excellent conductivity in a comb shape by forming an independent multi-structure.

Next, a manufacturing method of the present invention for manufacturing an O8A MOS FET, which is an embodiment of the semiconductor film device of the present invention, will be described with reference to FIGS.

/ n-type semiconductor substrate 1 containing a high concentration of n-type impurities
At a lower concentration than above, the resistivity is, for example, 10 to 20.
An n-type epitaxial layer 2 of Ω-1 is formed to a thickness of 35 to 45 μm, and a p-type small semiconductor is formed on the main surface of this epitaxial layer! ! FIG. 3(a) shows a state in which the i3 is selectively formed and a zero gate oxide 1115a having a thickness of, for example, about 1000 layers is formed on the surface thereof.

Next, a polycrystalline silicon film 6 is formed to a thickness of, for example, about 8,000 μm, and a PSG film 21 is formed on it to a thickness of, for example, about 1.5 μm using the CVD method, as shown in FIG. 3(b).
).

Next, the polycrystalline silicon film 6 and PSG [121] are selectively patterned by a photoetching technique using photoresist. Incidentally, at this time, the polycrystalline silicon film 6
In this step, Freon-based isotropic dry etching is performed using the photoresist as a mask, and the polycrystalline silicon film is underetched to the inside of the photoresist edges to form the photoresist in an overhang shape. Using the overhang-like photoresist as a mask, a low concentration of n-type impurity 11a is applied at 200 to 400 KC.
Deep ion implantation with high acceleration energies reaching V or 1000 Ke V. This situation is shown in FIG. 3(C).

After that, heat treatment is performed in, for example, an N2 and 02 gas atmosphere, and the p-type semiconductor layer 11 containing a low concentration of n-type impurities is formed.
FIG. 3(d) shows how a thin oxide film 22 having a thickness of, for example, 500 to 700 layers is formed.

In normal Gaussian Brehner diffusion, the lateral diffusion length is said to be approximately 20% shorter than the vertical diffusion length, and impurities are implanted with high acceleration energy using the photoresist overhang as an implant mask. For,
The p-type semiconductor layer 11 has a lateral diffusion length that is short compared to the vertical diffusion length, and is therefore formed so as not to reach the edge of the polycrystalline silicon film 6.

In this process, n-type impurity ions, which determine the threshold voltage of the gate, are implanted and heat treated to form a p-type semiconductor l! ! 4 is shown in FIG. 3(e).

Next, n-type impurity ions were selectively implanted at a high concentration, and about 50,000 rcVD-3i02ll5C were formed using the CVD method, and then heat treatment was performed to form an n0-type semiconductor layer 8 by diffusion. This is shown in Figure 3(f).

In addition, in FIG. 2(b), the oxide film 5b and cVD-8i
02 film 5c is collectively shown as an insulating film 5d.

For example, after forming electrode extraction openings 10a in each region, an An metal film 9 with a thickness of about 3.5 μm is formed to complete the semiconductor film arrangement, as shown in Fig. 3(,'). .

In this example, the depth of the p medium semiconductor layer 3 is 10 μm.
-, the depth of the p-type semiconductor layer 4 is 0.5 to 1 μm,
The depth of the p-type semiconductor layer 11 is set to 1 to 2 μm.

In this example, in FIG. 3(C), p-type ion 1
1a to form the p-type semiconductor layer 11, the polycrystalline silicon 116 may be etched to set back the pattern wedge of the polycrystalline silicon film.

FIG. 4 shows still another embodiment according to the present invention.
FIG. 4A is a plan view, FIG. 4B is a cross-sectional view taken along A-Al1, and FIG. 4A shows the An electrode film completely removed. In order to keep the gate polycrystalline silicon film pattern width constant, the channel width is made longer by using diagonal lines in the cell shape and integrating many cells. Therefore, in the pattern area per unit area,
This is the structure with the longest channel width. In this embodiment, the same parts as in the previous example are denoted by the same reference numerals. In this example, the planar shape of the cell surrounded by the continuous portion 6a of the polycrystalline silicon film pattern is octagonal annular portion 12A.
As shown in FIG. 2, it is composed of substantially octagonal end portions 128, 120 arranged symmetrically on both sides, and narrow connecting portions 12D, 12E that connect the annular portion with these end portions. It is only different from the example described above,
Since the other configurations are the same, no further explanation will be given.

5 to 7 show the planar shape of a pattern of an n-type semiconductor layer 4 surrounded by a polycrystalline silicon film pattern 6 in still another embodiment of the semiconductor film arrangement of the present invention. Fifth
In the embodiment shown in the figure, the octagonal end portions 4F and 4G are connected by a narrow connecting portion 4H, which are arranged at different pitches. Further, in the embodiment shown in FIG. 6, the hexagonal end portions 41a3 and 4J are connected by a narrow connecting portion 4, and the hexagonal end portions 41a3 and 4J are shifted by one inch. Furthermore, in the embodiment not shown in FIG. 7, the rectangular end portions 4L and 4M are connected by a narrow connecting portion 4N, which is shifted by one bit! Sil! It is location. In the embodiments shown in FIGS. 5 to 7, the p'' type half layer 11 with a low impurity concentration is self-aligned with the n type semiconductor layer 4.
It is formed deeper than the Furthermore, since the spacing between adjacent cells is approximately equal to each other, a long channel width can be obtained within a limited area.

The present invention is not limited to the embodiments described above, but can be modified and modified in many ways.

For example, in the above-described embodiment, the gate electrode material was polycrystalline silicon, but it is not limited to this.
, Ti, Cr, or a high melting point metal such as molybdenum silicide, nickel silicide, or platinum silicide. Further, the conductivity types of the n-type semiconductor layer and the n-type semiconductor layer may be opposite. Further, in the above-described embodiment, the p-type semiconductor layer 3 is formed in the opening of the polycrystalline silicon film pattern, but this can be omitted. Roughly speaking, in the above example, among the vertical field effect transistors, especially the DSA
Although the MO8 type semiconductor film is used, the present invention is not limited to this, and the gate polycrystalline silicon film pattern may be used as the emitter and the cell pattern as the base, or vice versa. It can also be applied to a bipolar type semiconductor film device used as an emitter. Furthermore, in the above embodiment, the DSA-MO
SFET, but for example, V-groove or U-groove MO8F
It can also be applied to ET. In this case, a channel region can be formed by forming a V-groove or a U-groove in the polycrystalline silicon film pattern itself or its edge portion. In the embodiment briefly described above, a power transistor is used, but a high frequency transistor or a power switching transistor may also be used. Particularly in high-voltage transistors, since a field limiting ring can be formed by the present invention, it is also applicable to other 5ITs (static Ti-induced transistors) of DSA-FETs.

(Effects of the Invention) As described above, to summarize the effects of the present invention, not only can the channel width be made longer and the on-resistance lower, but even if the channel length is narrowed, it is possible to
The through phenomenon does not occur, a high breakdown voltage between the source and drain is obtained, and by forming the channel p-type semiconductor layer and the source n-medium semiconductor layer shallowly, the capacitance between the source and gate can be reduced. Accordingly, the pattern width of the gate polycrystalline silicon film can be reduced, and since the area of the gate polycrystalline silicon film is also reduced, the capacitance j between the gate and drain can also be reduced.

Because the channel area is narrow, the transconductance is large (9 m), which in turn makes it possible to improve the switching speed.
type transistors can be provided by a highly productive manufacturing method.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are a plan view and a cross-sectional view showing the structure of an embodiment of a vertical semiconductor film device according to the present invention, and FIGS. 2(a), (b), and (C) are A plan view sectional view and a perspective sectional view showing the configuration of another embodiment of the vertical semiconductor film device, and FIGS. 4(a) and 4(b) are plan views and sectional views showing the structure of still other embodiments, and FIGS. 5 to 7 show modifications of the cell pattern. A plan view showing an example, FIGS. 8(a) and (b) are a plan view and a cross-sectional view showing the structure of a conventional vertical field effect transistor, and FIG. 9(a)
) to (f) are sectional views showing the structure in the same sequential manufacturing process, and FIGS. 10(a) and 10(b) are a plan view and a sectional view showing the structure of another example of the conventional vertical field effect transistor. be. 1...n-type semiconductor substrate 2...n-type epitaxial layer 3...p-type semiconductor layer 4...p-type semiconductor layer (first semiconductor layer) 5a...first
Insulating film 5d...Second insulating film 6...Polycrystalline silicon film 6a...Continuous portion 6b...Independent portion 8...n Small semiconductor layer (second semiconductor layer) 9a...
・1st AJ2′R pole R9b-・2nd AJ2 electrode control 10
a, 10b, 10c...opening 11...
p-type semiconductor layer (third semiconductor layer) 12A... annular portion 12B, 12G... end portion 120, 12E
...Connection parts 4A to 4C, 4F, 4G, 41.4J, 41°4M...
- Enlarged section 4[), 4E, 48. 4, 4N...
Connecting Department Patent Applicant: TDC Co., Ltd.
-,,,,,,,,,,-1-. Figure 2 (C) Figure 3 (a) n Figure 9 (a) Figure 9 (d) (e) Figure 9 (f)

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, a semiconductor film or conductive film pattern formed on the main surface of the semiconductor substrate via a first insulating film, and within an opening of this pattern, a first semiconductor layer of an opposite conductivity type formed on the main surface of the semiconductor substrate at a position that partially overlaps with a part of the semiconductor film or conductor film pattern with the first insulating film interposed therebetween; a second semiconductor layer of one conductivity type formed so as to partially overlap with a part of the semiconductor film or conductor film pattern; A third semiconductor layer of an opposite conductivity type formed deeper and with a lower impurity concentration than the first semiconductor layer and covering the semiconductor film or the conductive film so as to maintain a gap or reach the same position as the edge. What is claimed is: 1. A vertical semiconductor device comprising: a second insulating film which is formed in the second insulating film and has an opening; and a metal electrode film formed on the second insulating film so as to include the opening. 2. The planar shape of the first semiconductor layer surrounded by the semiconductor film or conductor film pattern is made into a polygonal or circular enlarged portion that is an integral multiple of 2, and a narrow width that connects adjacent enlarged portions. 2. The vertical semiconductor device according to claim 1, further comprising a connecting portion. 3. The vertical semiconductor device according to claim 2, wherein the expanded portion of the first semiconductor layer has an octagonal shape, and opposing sides of two or more adjacent expanded portions are connected by a connecting portion. 4. The semiconductor film or conductor film pattern has a mutually continuous pattern portion and an independent pattern portion located within the pattern opening, and these continuous pattern portions and independent pattern portions are connected via the metal electrode film. Claim 1, 2 or 3 characterized in that the invention is interconnected with each other.
The vertical semiconductor device described above. 5. Forming a first insulating film on the main surface of a first semiconductor substrate of one conductivity type; forming a semiconductor film or a conductive film on the first insulating film, and forming a mask thereon; A step of under-etching the semiconductor film or conductive film through this mask to form a semiconductor film or conductive film pattern and simultaneously forming an overhang-like mask; forming a third semiconductor layer of the opposite conductivity type deeply by deeply implanting ions of the opposite conductivity type at a low concentration; a step of shallowly implanting ions at a high concentration to form a first semiconductor layer of an opposite conductivity type; and implanting ions of one conductivity type into the first semiconductor layer using the semiconductor film or conductor film pattern as a mask. a step of forming a second semiconductor layer of one conductivity type on the semiconductor film or the conductor film and a step of forming a second insulating film so as to cover the opening thereof;
selectively forming an opening in an insulating film to partially expose the first semiconductor layer and the second semiconductor layer; and forming a metal electrode film on the second insulating film to cover the opening. A method for manufacturing a vertical semiconductor device, comprising: