JP3381490B2 - MOS type semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS field effect transistor (hereinafter referred to as a MOSFET) provided with a plurality of source regions having metal-oxide film-semiconductor (MOS) structure gates dispersed in a surface layer of a semiconductor substrate. Note), a MOS type semiconductor device such as an insulated gate bipolar transistor, and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a switching circuit, a MOS type semiconductor device is widely used because of its low on resistance and high switching speed. 4A to 4C show an example of a conventional MOSFET which is one of MOS type semiconductor devices,
(A) is a plan view, (b) is a sectional view taken along line CC of (a),
(C) is a DD sectional view taken on the line (a). That is, n
A plurality of p ⁺ well regions 2 and a surrounding p channel region 3 are formed in a rectangular shape on the surface layer of the type semiconductor layer 1, and an n ⁺ source region 4 is further formed on the surface layer. And
For example, a gate electrode 5 made of polycrystalline silicon is provided on a portion sandwiched between the n ⁺ source region 4 of the p channel region 3 and the exposed surface of the n-type layer 1 with a gate oxide film 6 interposed therebetween. A source electrode 8 made of an Al—Si alloy is provided in common contact with the p ⁺ well region 2 and the n ⁺ source region 4, and is insulated by an interlayer insulating film 7 made of boron-phosphorus silica glass (BPSG) to form a gate. It extends above the electrode 5. Although not shown, a drain electrode made of an Al—Si alloy is provided on the back surface side of the n-type semiconductor layer 1. The unit structure having the n ⁺ source region 4, the source electrode 8 and the like above and below the p channel region 3 as shown in the figure is called a cell structure. Although a square cell structure is drawn in FIG. 4A and the explanation is also made into a square, in an actual semiconductor device, the corners are rarely at right angles or less, and are usually rounded. Often shaped or octagonal with the corners shaved. Here and thereafter, a rectangle having four major sides consisting of two pairs of parallel lines and having their extensions intersecting at an angle close to a right angle is called a rectangle. In an actual MOSFET, many such cell structures are juxtaposed. The n-type layer 1 may be the n-type semiconductor substrate itself or a semiconductor layer laminated on the p-type or n-type semiconductor substrate by an epitaxial method or the like.

[0003]

In recent years, in switching circuits, MOSF which is the switching device.
The ET has become more susceptible to the surge voltage generated due to simplification of the circuit such as omission of the snubber circuit and downsizing of the device. This leads to a cause of breakdown in the MOSFET, and improvement in the breakdown resistance (avalanche resistance) is required. In order to improve the avalanche resistance of such a MOSFET, the diffusion depth of the p ⁺ well region 2 is increased. However, if the diffusion depth of the p ⁺ well region 2 is increased, other characteristics such as ON resistance are affected. FIG. 5 shows the relationship between the diffusion depth of the p ⁺ well region 2 and the avalanche withstand capability (solid line) and on-resistance (broken line) in a 900 V, 5 A class device. The horizontal axis represents the diffusion depth of the p ⁺ well region 2, and the vertical axis represents the avalanche resistance and on-resistance. It can be seen that if the p ⁺ well region 2 is deepened, the avalanche resistance is improved, but the on-resistance is also increased. Therefore, in order to achieve both improvement of the avalanche resistance and other characteristics, it is necessary to conduct an experiment for determining the manufacturing process conditions and the like, which takes time. In addition, there is a problem that improvement of avalanche resistance is limited in order to achieve compatibility with each characteristic.

In view of the above problems, it is an object of the present invention to provide a MOS semiconductor device having an improved avalanche withstand capability without sacrificing other characteristics.

[0005]

To achieve the above object, the present invention provides a second conductivity type channel region of a surface layer of a first conductivity type semiconductor layer and a first conductivity type of a surface layer of the channel region. In a MOS semiconductor device having a plurality of rectangular cell structures having four main sides formed so that at least two sides are parallel to the type source region, one side of a channel region of one rectangular cell structure is It is assumed that one side of the channel region of the adjacent cell structure is connected and one side of the channel region of another cell structure is connected to the side of the connected part.

[0006]

[0007] Also, the impurity concentration than the channel region in a part of the surface layer of the second conductivity type channel region is high, and it has a shallow base region of the shallow diffusion depth second conductivity type.
Only the channel region may be provided as the second conductivity type region below the shallow base region.

At least the sides of the channel region of the second conductivity type channel region formed in the surface layer of the first conductivity type semiconductor layer and the first conductivity type source region formed in the surface layer of the channel region. In a case where a plurality of rectangular cell structures each having four main sides formed so that two sides each having a side of the source region are parallel to each other are provided, one side of the two sides of the rectangular cell structure is Channel region
It is assumed that the cell structure is connected to the channel region on one of the two sides of the adjacent cell structure. The source region may be annular.

It is also assumed that one cell structure is rectangular and the short side of the channel region is connected to one side of the channel region of the adjacent cell structure. The short sides of the channel regions of one rectangular cell structure may be connected to the short sides of the adjacent channel regions of the cell structure. Further, it is effective to provide a first conductivity type semiconductor region having a lower resistivity than the first conductivity type semiconductor layer in the vicinity of the surface of the first conductivity type semiconductor layer.

FIGS. 6A and 6B show how avalanche current flows in the conventional MOSFET and the MOSFET of the embodiment of the present invention, respectively. In the arrangement of the conventional rectangular cell structure shown in FIG. 6A, the spacing between the corners of the channel region 3 of the cell structure is wider than the spacing between the sides. At the corner of the p-channel region 3, the breakdown voltage is low due to the large curvature of the pn junction, and the avalanche current I ₁ due to avalanche breakdown is shown in FIG.
As shown in (a), the avalanche withstand capability decreases because the region is surrounded by the four corners and concentrates on the four corners.
On the other hand, as shown in FIG. 6B, when the sides of the channel region are connected to each other, the corner of the channel region disappears, the avalanche current is not concentrated on the corner, and the avalanche current I ₂ is a straight line facing each other. Since it flows on two sides of the shape, the withstand capacity increases. As a result, in the cross-sectional view showing the parasitic bipolar transistor in the cell structure of the MOSFET of FIG. 7, the avalanche current flowing through the resistance R _b of the p channel region 3 immediately below the n ⁺ source region 4 decreases, and the n-type layer 1,
The parasitic bipolar transistor composed of the p-channel region 3 and the n ⁺ source region 4 is less likely to be erroneously ignited.
Prevents SFET destruction. Moreover, the curvature of the pn junction becomes small and the breakdown voltage also becomes large.

Further, another channel region is laterally connected to a portion where the sides of the channel region are connected to each other to form the channel region in a lattice type so that the corner of the channel region can be eliminated. However, since the avalanche current does not concentrate on the corner, the avalanche withstand capability increases. Also, if the outer side of the channel region of the cell structure where the cell structures of the semiconductor chip are arranged is made to be substantially parallel to the side of the semiconductor chip, a pn junction is formed close to a straight line and electric field concentration is prevented. It is hard to occur. Further, if the first conductivity type source region is provided only in the chip center side portion of the peripheral cell structure, the first conductivity type source region is not formed in the outer portion, so that even if a large avalanche current flows,
Without parasitic transistor operates, it improves the avalanche resistance.

[0012]

Furthermore, if a second conductivity type shallow base region having a higher impurity concentration than the channel region and a shallow diffusion depth is formed in a part of the surface layer of the second conductivity type channel region, the conductivity of the channel region is increased. Increase, the base resistance of the parasitic transistor decreases, and it becomes difficult for the parasitic transistor to operate.
It contributes to the improvement of avalanche resistance. In particular, even if only the channel region as the second conductivity type region below the shallow base region and no second conductivity type well region is provided, the avalanche withstand capability is significantly improved.

Further, the channel region on one side of the two sides of the rectangular cell structure formed by making at least two sides of the channel region and the source region parallel to each other has a channel region on one side of the two sides of the adjacent cell structure. If the source region at this time is connected to the channel region and has an annular shape, the area of the source region is large, so that the on-resistance can be reduced.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION FIGS.
1 shows a MOSFET according to a first embodiment of the present invention, FIG. 1 is a plan view excluding an upper structure, FIG. 2 (a) is a sectional view taken along the line AA of FIG. 1, and FIG. 2 (b) is B of FIG. In the cross-sectional view taken along the line B, the same parts as those in FIG. 4 are designated by the same reference numerals.

In FIG. 1, a rectangular p-channel region 3 having an n ⁺ source region 4 and a p ⁺ well region 2 therein is arranged on the surface layer of the n-type semiconductor layer 1 by connecting the short sides of the rectangle. ing. The connected boundaries are indicated by a dashed line in the figure. Although the p-channel region 3 is rectangular in this figure, it may be square. Note that the corners of the p-channel region 3, the n ⁺ source region 4, etc. are not actually right angles, but are somewhat rounded, and have a radius of 1.5 to 2 μm, for example. A p-channel region 3 is formed in the surface layer of the n-type layer 1 having a resistivity of 45 Ωcm and a thickness of 100 μm, a p ⁺ well region 2 having a diffusion depth deeper than that of the p-channel region 3, and an n ⁺ layer in the surface layer.
The source region 4 is formed. n ⁺ source region 4 and n
A gate electrode 5 made of polycrystalline silicon is provided on the surface of the p channel region 3 sandwiched between the exposed surface of the mold layer 1 and a gate oxide film 6. n ⁺ source region 4 and p
^A source electrode 8 is provided in common contact with the surface of the ⁺ well region 2 and extends above the gate electrode 5 via an interlayer insulating film 7. Although not shown, a drain electrode is provided on the back surface side of the n-type layer 1 via an n ⁺ substrate. The operation of the MOSFET of the first embodiment shown in FIGS. 1 and 2 is performed as follows. When a positive voltage equal to or higher than a certain value is applied to the gate electrode 5, an inversion layer is formed in the vicinity of the surface of the p-channel region 3 directly below the gate electrode 5, and between the n ⁺ source region 4 and the n-type layer 1. Conducts. Then, if a voltage is applied between the drain electrode and the source electrode 8 provided on the back surface side of the n-type layer 1, a current flows. Therefore, since the current flows, the exposed surface portion of the n-type layer 1 needs to have a certain area.

In FIG. 2B, it can be seen that the two p-channel regions 3 are connected. In this cross section, there is no n ⁺ source region in the surface layer of the p channel region 3. A thin gate electrode 5 made of polycrystalline silicon is provided on the surface of the portion where the p-channel region 3 is connected via a gate oxide film 6.
Wide gate electrodes 5 of two adjacent cell structures connected in the direction perpendicular to the plane of the drawing are connected. The gate electrode 5 and the source electrode 8 are insulated by the interlayer insulating film 7.

Returning to FIG. 1 again, in the figure, the p-channel region 3 is formed in a lattice shape, and the conventional MOSFE is used.
Since there is no protruding corner of the p-channel region 3 like T, the depletion layer usually has a small curvature, and therefore the breakdown voltage is reduced at the corner of the cell structure where breakdown easily occurs, and The avalanche current is not concentrated and the avalanche withstand capability is improved. Although the portion surrounded by the cell structure is wide and the avalanche current is large, the pn junctions facing each other are almost straight and can withstand a large avalanche current. Also, FIG.
In the cross section between the side portions of the two cell structures in (a), the n-type layer 1 under the gate electrode 5 is wide, so
The current path is wide when the SFET is conducting, and the on-resistance can be suppressed low.

In FIG. 1, the left side and the lower side are MOSFs.
This is the end of the ET chip 12. At the outermost periphery of the portion where the cell structures of the semiconductor chip 12 are arranged, the outer peripheral side of the channel region of the cell structure is parallel to the side of the semiconductor chip 12, and the outer side of the channel region is a semiconductor. Outer corner cell structure 2 having an arc shape toward the corner of the tip 12
0 is provided. By doing this, the outermost pn
Since the curvature of the junction is small, electric field concentration is less likely to occur and the avalanche withstand capability is improved. Further, the outer peripheral cell structure 19 and the outer corner cell structure 20 have the first-conductivity-type source region only in the portion near the center of the chip of the cell. This improves the avalanche withstand capability for the following reason. That is, the avalanche breakdown usually starts from the outermost pn junction, but since the n ⁺ source region is not formed in this portion, the parasitic transistor does not operate even when a large avalanche current flows,
Avalanche resistance is improved. Moreover, the outer cell structure 1
9 and the outer angle cell structure 20 have a larger area than the inner rectangular cell structure, the avalanche energy absorption is also increased and the avalanche withstand capability is improved. Outer cell structure 1
The dotted line near 9 is the boundary of the polycrystalline silicon ring 18. The outer side of the p-channel region of the outer corner cell structure 20 is
The arc does not necessarily have to be an arc toward the corner of the semiconductor chip, and electric field concentration can be avoided even if it is a polygonal line imitating an arc.

FIG. 3 shows a sectional view of the end of the MOSFET chip 12. A drain electrode 13 is provided on the back surface side of the n-type layer 1 via an n ⁺ substrate. A polycrystalline silicon ring 18 for taking out a gate lead is provided via a thick field oxide film 14 on the p ⁺ well region 2 at the outermost periphery where the cell structures are arranged, and a p layer is formed on the outermost surface layer of the chip 12. Peripheral region 16 and peripheral electrode 1 on it
7 is provided.

The parameters of each part are as follows. n
Mold layer 1: impurity concentration 1 × 10 ^{13 to} 3 × 10 ¹⁶ cm ⁻³ , thickness 5 to 150 μm, p ⁺ well region 2: boron ion dose amount 5 × 10 ¹⁴ to 2 × 10 ¹⁵ cm ⁻² , diffusion Depth 5
10 μm, p channel region 3: Boron ion dose amount 3 × 10 ^{13 to} 5 × 10 ¹⁴ cm ⁻² , diffusion depth ² to 4 μm,
n ⁺ source region 4: arsenic ion dose amount 4 × 10 ¹⁵ to
5 × 10 ¹⁵ cm ^-2 , diffusion depth 0.2 to 0.3 μm, gate electrode 5: polycrystalline silicon thickness 500 to 1000 nm,
Gate oxide film 6: thickness 25 to 120 nm, interlayer insulating film 7: BPSG thickness 0.6 to 1.1 μm, source electrode 8:
Al—Si thickness 3 to 5 μm, field oxide film 14: thickness 500 to 1100 nm, passivation film 15: S
iN thickness 800 nm, width L1: 6 to 40 μm of the gate electrode 5 of polycrystalline silicon in FIG. 1, distance L between the gate electrodes 5
2: 6 to 20 μm, length of n ⁺ source region 4 L3: 12
˜200 μm, width L4 of thin gate electrode 5: 2 to 6 μm
m. As for the p base region, there are three types of p channel region 3 and p ⁺ well region 2, p channel region 3 and p shallow base region 11, p channel region 3, p ⁺ well region 2 and p ⁺ shallow base region 11. Can be used.

The MOSFETs of FIGS. 1 and 2 are generally manufactured by the following manufacturing process. First, an epitaxial wafer in which an n-type semiconductor layer 1 is laminated on an n ⁺ substrate is prepared, and acceptor-forming impurities are selectively introduced from the surface to form a p-well region 2. Next, a gate oxide film 6 is formed by thermal oxidation, and a polycrystalline silicon film is deposited thereon by a low pressure CVD method. A pattern of the gate electrode 5 is formed on the polycrystalline silicon film by using a photoetching technique, and the p-channel region 3 and the n ⁺ source region 4 are formed by ion implantation and thermal diffusion of impurities using the end of the gate electrode 5. And are formed in a self-aligned manner. An interlayer insulating film 7 of BPSG is deposited on the gate electrode 5 by a CVD method,
A window is opened on the p ⁺ well region 2 and the n ⁺ source region 4 to provide a source electrode 8 made of an Al-Si alloy.
A passivation film 15 of a nitride film is further laminated on the source electrode 8. Finally, on the back surface of the n ⁺ substrate, Al-
The drain electrode 13 made of Si alloy is formed. Further, in FIG. 1, the gate electrode 5 and the polycrystalline silicon ring 1 are
The portion on which the polycrystalline silicon of 8 was deposited is shown by hatching. There is a thin gate electrode 5 connecting the gate electrodes 5 on the n-type layer 1, but below that, the p-channel region 3 is connected by lateral diffusion of impurities. Even with a thin gate electrode 5 in which the p-channel region 3 is connected by the lateral diffusion of impurities, the resistance to the current flowing in the gate electrode is reduced if there are many, and it is extremely effective for uniforming the gate bias. Thus, the MOSFET of the first embodiment
Just change the mask to form the cell structure,
It can be manufactured without adding any extra step to the conventional MOSFET manufacturing process.

FIG. 8 shows the temperature characteristics of the avalanche withstand capability of the MOSFETs of FIGS. 1 and 2 and the conventional MOSFET shown in FIG. 4, and the MOSF of the embodiment of the present invention shown by the line 21.
The avalanche resistance of ET is the conventional MOS shown by the line 22.
Compared with the avalanche withstand capability of FET, it is about 1.6 times at 25 ° C. and about 4.7 times at 125 ° C.
9 and 11 (a), (b) show a MOSFET of the second embodiment of the present invention. 9 is a plan view excluding the upper structure, and FIG. 11A is a cross-sectional view taken along the line EE of FIG.
9B is a cross-sectional view taken along the line FF of FIG. 9, and the same reference numerals are given to portions common to other figures. In this embodiment of FIG. 9, in the modification of the first embodiment shown in FIG. 1, the rectangular cell structure is not only connected at the short sides, but also separated from the side of the connected portion. The cell structures of are connected. Also in the other cell structure, n inside the p channel region 3
^{The +} source region 4 and the p ⁺ well region 2 are further inside. The exposed surface of the n-type layer 1 is seen in a rectangular shape surrounded by the p-channel regions 3 vertically connected horizontally. Figure 1
The sectional view of FIG. 1A is almost the same as the sectional view of FIG. That is, the p channel region 3 having the deep p ⁺ well region 2 is formed in the surface layer of the n-type semiconductor layer 1, and the n ⁺ source region 4 is formed in the surface layer. The gate electrode 5 is provided on the surface of the p channel region 3 sandwiched between the n ⁺ source region 4 and the n-type semiconductor layer 1 via the gate oxide film 6, and the surface of the n ⁺ source region 4 and the p ⁺ well region. The source electrode 8 is provided so as to be in common contact with. G in FIG.
It can be easily understood that the cross section along the line -G is almost the same as that in FIG. In the cross section taken along the line FF of FIG. 9, two p channel regions 3 are connected as shown in FIG. That is, the p-channel region 3 is connected at the surface layer of the n-type layer 1, and the thin gate electrode 5 is provided above the p-channel region 3 via the gate oxide film 6. In this way, the p-channel regions 3 of the cell structure are connected to each other to prevent the breakdown voltage from decreasing at the corners of the cell structure and prevent the avalanche breakdown voltage from decreasing. The width L8 of the gate electrode 5 at this connecting portion is 2 to
It is 6 μm. In the cross-sectional view of FIG. 11A, the distance between the two cell structures is sufficiently large, there is a large exposed portion of the n-type layer 1 under the gate electrode 5, and the on-resistance can be kept low even when the MOSFET is conducting. . The width L5 of the gate electrode 5 in this portion is 16 to 190 μm, the distance L6 between the gate electrodes 5 is 6 to 20 μm, and the n ⁺ source region 4 is formed.
Has a length L7 of 12 to 200 μm. Also in this example, as shown in FIG. 9, the outer peripheral cell structure 19 at the outermost peripheral portion of the portion where the cell structures of the semiconductor chip are arranged is
The outer side of the p-channel region 3 is parallel to the side of the semiconductor chip, the n ⁺ source region 4 is provided only in the inner part of the cell structure, and the area is larger than that of the inner rectangular cell structure.
The outer corner cell structure 20 has an arc shape in which the outer side of the p channel region 3 faces the corner of the semiconductor chip, and has a larger area than the other outer peripheral cell structure 19. These contribute to the improvement of the avalanche resistance as in the above example.

In the structure of the second embodiment of FIG. 9, the p-channel region 3 and the n ⁺ source region 4 are larger in area than the MOSFET of the first embodiment of FIG. 1, so that the on-resistance can be reduced. In the MOSFET of the second embodiment, the conventional MO can be changed only by changing the mask for forming the cell structure.
It can be manufactured without adding any extra process to the manufacturing process of the SFET.

FIG. 10 shows a MOS according to the third embodiment of the present invention.
FIG. 10 shows a FET, and FIG. 10 is a plan view excluding the upper structure, and the same reference numerals are given to portions common to other figures. This embodiment is a modification of the second embodiment shown in FIG. The cell structures are vertically connected in the same manner, except that the n ⁺ source regions 4 in the cell structure are formed in a square ring shape. Therefore, the cross section taken along the line HH of FIG. 10 is almost the same as the cross section of FIG. However,
The cross section taken along the line I-I of FIG. 10 is as shown in FIG. 12, unlike the cross-sectional view of FIG. That is, n is also formed in the connecting portion between the two p channel regions 3 below the thin gate electrode 5.
⁺ There is a source region 4. In the structure of this embodiment, since the area of the n ⁺ source region 4 is larger than that of the MOSFET of the second embodiment shown in FIG. 9, the on resistance can be further reduced.

FIG. 13 shows a MOS according to the fourth embodiment of the present invention.
In the cross-sectional view of the cell structure of the FET, the same parts as those in the other figures are designated by the same reference numerals. In this case, the p-shallow base region 11 having a higher impurity concentration than the p-channel region 3 and a shallow diffusion depth is formed in a part of the surface layer of the p-channel region 3 in FIG.
For example, the dose amount of boron is 1 × 10 ^{15 to} 3 × 10 ¹⁵ c
It is formed by ion implantation and diffusion heat treatment with m ⁻² and a diffusion depth of 0.5 to 1 μm. As a result, the channel resistance is reduced, so that the operation of the parasitic transistor is suppressed and the avalanche withstand capability is improved.

FIG. 14 shows a MOS according to the fifth embodiment of the present invention.
In the cross-sectional view of the cell structure of the FET, the same parts as those in the other figures are designated by the same reference numerals. In this case, in the fourth embodiment of FIG. 12, a p-shallow base region 11 having a higher impurity concentration than the p-channel region 3 and a shallow diffusion depth is formed in a part of the surface layer of the p-channel region 3. Same as example, but p
⁺ Well region is not formed. On that improve the placement of the cell structure, by forming a p shallow base region 11, by reducing the channel resistance, parasitic transistor operation can be suppressed, since the avalanche resistance is sufficiently improved, p ⁺ well region Even if 2 is not formed, an avalanche withstand capacity that can be practically used can be obtained, and the problem of increasing the on-resistance described above can be solved. In particular, if the formation of the p ⁺ well region 2 having a large diffusion depth can be omitted, there are great advantages in terms of time and cost.

FIG. 15 shows a MOS according to the sixth embodiment of the present invention.
It is sectional drawing which shows FET. This embodiment is a modification of the first to fifth embodiments and corresponds to FIG. The difference between this embodiment and the first to fifth embodiments is that the n-type semiconductor region (having a higher resistivity than the n ⁺ source region 4) has a lower resistivity than the n-type semiconductor layer (for convenience (n ⁻ )) 1. 31 is formed. The parameters of the n-type semiconductor region 31 are a dose amount of phosphorus (P) ions of 5 × 10 ¹² cm ⁻² and a diffusion depth of ² to 4 μm. With this n-type semiconductor region 31,
The doping concentration can be increased as compared with the prior art, and the gate-drain capacitance can be reduced and the switching speed can be increased by reducing the area by reducing the resistivity. The sixth embodiment can be applied to all the first to fifth embodiments.

Although the embodiments of the MOSFET have been described above, the present invention can be applied to a MOS type semiconductor device such as an insulated gate bipolar transistor having a gate of a MOS structure and an MCT (MOS control thyristor), and the like. It is possible to obtain the desired effect.

[0030]

As described above, according to the present invention, a channel region of another cell structure is laterally connected to a portion where sides of a channel region of a rectangular cell structure of a MOS semiconductor device are connected, By eliminating the corners of the channel region, it is possible to prevent the breakdown voltage and the avalanche withstand capability from decreasing at the corners of the channel region, which have been conventionally problems.
Also, provided the shallow base region of a high impurity concentration Ji Yaneru area, by subtracting the channel resistance, it is possible to improve the avalanche resistance. The on-resistance can be reduced by making the source region of the cell connecting the channel regions annular.

[Brief description of drawings]

FIG. 1 is a plan view of a MOSFET according to a first embodiment of the present invention excluding an upper structure.

2A is a sectional view of the MOSFET of the first embodiment taken along the line AA of FIG. 1, and FIG. 2B is a sectional view taken along the line BB of FIG.

FIG. 3 is a sectional view of a peripheral portion of the MOSFET shown in FIG.

FIG. 4 shows a conventional MOSFET, (a) is a plan view excluding an upper structure, (b) is a sectional view taken along line CC of (a),
(C) is the DD sectional view taken on the line of (a).

FIG. 5 is a relational diagram of avalanche withstand capability and on-resistance with respect to diffusion depth of p-well region of MOSFET.

FIG. 6 shows avalanche current, where (a) is a conventional MO.
A plan view of the SFET, (b) is a MOS of the embodiment of the present invention
Top view of FET

FIG. 7 is a cross-sectional view showing a parasitic bipolar transistor generated near the surface of MOSFET.

FIG. 8 is a MOSFET according to an embodiment of the present invention and a conventional MOS.
Temperature characteristic diagram of avalanche resistance with FET

FIG. 9 is a plan view of the MOSFET of the second embodiment of the present invention excluding the upper structure.

FIG. 10 is a plan view of the MOSFET according to the third embodiment of the present invention excluding the upper structure.

11 (a) is an MO of the second embodiment of the present invention of FIG.
EE line sectional view of SFET, (b) FF line sectional view

FIG. 12 is a schematic diagram showing the MOSFET I-of the third embodiment of FIG.
I line cross section

FIG. 13 is a cross-sectional view of essential parts of a MOSFET according to a fourth embodiment of the present invention.

FIG. 14 is a cross-sectional view of essential parts of a MOSFET according to a fifth embodiment of the present invention.

FIG. 15 is a cross-sectional view of essential parts of a MOSFET according to a sixth embodiment of the present invention.

[Explanation of symbols]

1 n-type layer 2 p ⁺ well region 3 p channel region 4 n ⁺ source region 5 gate electrode 6 gate oxide film 7 interlayer insulating film 8 source electrode 11 p ⁺ shallow base region 12 chip 13 drain electrode 14 field oxide film 15 passivation film 16 p Peripheral region 17 Peripheral electrode 18 Polycrystalline silicon ring 19 Peripheral cell structure 20 Outer corner cell structure 31 n-type semiconductor layer

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A 61-82477 (JP, A) JP-A 59-167066 (JP, A) JP-A 60-150674 (JP, A) JP-A 59- 65483 (JP, A) JP-A-1-238173 (JP, A) JP-A-3-142972 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21 / 336

Claims (8)

(57) [Claims] 1. A second conductivity type channel region formed in a surface layer of a first conductivity type semiconductor layer and at least two sides of a first conductivity type source region formed in a surface layer of the channel region are parallel to each other. A plurality of square cell structures having four main sides formed by connecting one side of a channel region of one square cell structure to one side of a channel region of an adjacent cell structure, A MOS semiconductor device, wherein one side of a channel region of another cell structure is connected to the side of the connected part. 2. A higher impurity concentration than the channel region in a part of the surface layer of the second conductivity type channel region, to claim 1, characterized in that it comprises a shallow base region of the shallow second conductive type diffusion depth The described MOS type semiconductor device. 3. A channel region only as a second conductivity type region is provided below the shallow base region.
2. The MOS semiconductor device according to item 2 . 4. A side of at least the channel region of the second conductivity type channel region formed in the surface layer of the first conductivity type semiconductor layer and the first conductivity type source region formed in the surface layer of the channel region. In a case where a plurality of rectangular cell structures each having four main sides formed so that two sides each having a side of the source region are parallel to each other are provided, one side of the two sides of the rectangular cell structure is A MOS type semiconductor device, wherein a channel region is connected to a channel region on one side of the two sides of adjacent cell structures. 5. The MOS type semiconductor device according to claim 4, wherein the source region has a ring shape. 6. The MOS semiconductor according to claim 4 , wherein one cell structure is rectangular, and a short side of the channel region is connected to one side of a channel region of an adjacent cell structure. apparatus. 7. The MOS type semiconductor device according to claim 6 , wherein a short side of a channel region of one rectangular cell structure is connected to a short side of a channel region of an adjacent cell structure. 8. A MOS according to claim 1 or 4, further comprising a first conductivity type semiconductor region of low resistivity than said one conductivity type semiconductor layer in the vicinity of the surface of the first conductive type semiconductor layer
Type semiconductor device.