JP2000188397A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve breakdown strength against surge of a power insulating gate-type semiconductor device, such as a UMOS. SOLUTION: An n-type semiconductor region 3, p-base regions 4 arranged in the n-type semiconductor region 3, groove parts formed shallower than the deepest parts in the p-base regions 4, n+-source regions 5 arranged on the surfaces of the p-base regions 4, an n+-embedded drain region 2 arranged under the p-base region 4, gate insulating films 6 formed on the sidewalls of the groove part and control electrodes 7 embedded in the groove parts are installed. An n-type pull-out region (sinker) 8 reaching the n+-embedded drain region 2 from the surface of the n-type semiconductor region 3 is provided. The base corner parts of the groove parts are covered by the p-base regions 4, and the centers of the base parts of the groove parts are brought into contact with the n-type semiconductor region 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a U-groove (trench).
Related to a semiconductor device having a buried gate electrode inside a semiconductor device, especially an IPD (Intelligent Power Device)
The present invention relates to a novel structure of a semiconductor device that can be used for an integrated circuit such as the above, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Power semiconductor devices such as MOSFETs
In, how to reduce the on-resistance per unit chip area is one of the very important issues.
This is because the reduction of the on-resistance directly leads to the reduction of the conduction loss of the power semiconductor element, and further contributes to the improvement of the efficiency of circuits and systems such as inverters using the power semiconductor element, thereby enabling energy saving. Because. For this reason, as one of the techniques for lowering the on-resistance, how to effectively use the available area on the chip is being studied.

In a DMOSFET in which an element is formed by double diffusion of a base region and a source region, as the cell size is reduced, a neck portion (n region) sandwiched between the base regions
Due to the current concentration on the JFET, the JFET resistance increases rapidly. JFE
The T resistance is the resistance of a JFET whose channel is an n region sandwiched between adjacent p base regions. For this reason, DMO
The on-resistance of the SFET tends to increase after it takes a minimum value with the miniaturization of the size of the cell region.

[0004] The UMOSFET has a typical structure capable of eliminating the JFET resistance, and can reduce the cell size to the limit of the processing technology and the on-resistance.

On the other hand, in an insulated gate bipolar transistor (hereinafter, referred to as "IGBT"), conductivity can be modulated by injecting carriers from the collector side, so that it is relatively easy to reduce on-resistance. However, a gate structure technique that eliminates the same JFET resistance as described above and does not increase the channel resistance is important. For the same reason as described above, miniaturization of an IGBT having a structure in which an element is formed by double diffusion of a base region and an emitter region causes an increase in on-resistance due to the influence of the JFET resistance.

Japanese Patent Application Laid-Open No. 8-316467 discloses a horizontal UMOSFET as shown in FIG. As shown in FIG. 17, in the conventional lateral power UMOSFET, an n-well region 3 is formed in a p-epi layer 30 formed on an upper surface of a p-substrate 1. An n ⁺ buried layer 17 is formed at the bottom of the n well region 3, and the n ⁺ buried layer 17 and the drain electrode 10 are connected by an n ⁺ drain extraction region (n ⁺ sinker) 8. n in the p base region 4
⁺ Source region 5 is formed, and a U-groove (trench) penetrating p base region 4 and reaching n well region 3 is formed. A U-shaped gate electrode 7 is formed inside the trench with a U-shaped gate insulating film 6 interposed therebetween. First
The source electrode 9 and the drain electrode 10 are formed insulated from the U-shaped gate electrode 7 by the interlayer insulating film 11. A second-layer drain electrode (second-layer second main electrode) 13 is formed on the source electrode 9 and insulated by the second-layer interlayer insulating film 12.

FIG. 18 is a plan view of a conventional lateral UMOSFET corresponding to FIG. The U-shaped gate electrode 7 is formed in a lattice shape, and the source cell 16 is surrounded by the U-shaped gate electrode 7. The source cells 16 are arranged at a predetermined pitch in a matrix (square mesh). One row of source cells 16 surrounds one drain cell 15.

[0008]

However, the conventional UMO
In the SFET, the depth of the U groove (trench) is deeper than the depth of the p base region 4. According to a detailed study by the inventor, it has been found that the depth of the U-groove (trench) is deeper than the depth of the p base region 4 in the conventional UMOSFET.
It was found that this was the reason for the low breakdown strength.

That is, in the UMOSFET, an inversion channel is formed on the surface of the p base region 4 located on the side surface of the U-type gate insulating film 6, and the element is conducted. During the operation of the UMOSFET, particularly in the cut-off state (blocking state), the strong electric field concentrated on the U-type gate electrode 7 causes the bottom corner portion of the U-type gate insulating film 6 and the U
It was found to be at the bottom of the groove.

When the device (UMOSFET) is in a cut-off state (blocking state), a high voltage is applied between the gate and the drain and between the source and the drain, and the p base region 4
A depletion layer extends at the junction interface composed of the n-well region 3 and a high electric field is applied. At this time, the bottom corner of the U-type gate insulating film 6 is protected from direct high voltage by the depletion layer, but a high electric field in the cut-off state (blocking state) is applied to the bottom corner of the U-type gate insulating film 6. concentrate. Therefore, various investigations have revealed that when a surge is applied to the drain electrode 10, the bottom corner of the U-type gate insulating film 6 is destroyed first.

The phenomenon that the electric field is concentrated on the bottom corner of the U-type gate insulating film 6 is the same in other insulated gate semiconductor devices having a trench structure. For example, according to the study of the present inventors, UMOSFE is also used for IGBT.
As in the case of T, it has been found that it is necessary to consider the electric field concentration at the bottom corner of the U-type gate insulating film 6. In a high-breakdown-voltage IGBT, a portion having a strong electric field is generated in an n drift layer formed of a high resistivity region, and an avalanche phenomenon occurs at a voltage lower than a normal collector-emitter breakdown voltage, and the IGBT is turned off ( Off) causing destruction. In the case of a trench vertical IGBT in which a channel is formed on the side surface of the U-type gate and the bottom corner of the U-type gate insulating film exists in the n-drift layer, this phenomenon appears more remarkably.

Furthermore, a broader definition of an insulated gate semiconductor device such as a high electron mobility transistor (HEM)
A similar problem exists in T). For example, AlG
In a HEMT using a heterojunction such as aAs / GaAs, a wide bandgap semiconductor (AlGaAs) performs the same function as an insulating layer, and a substantially similar high electric field is applied to a bottom corner of an AlGaAs thin film formed in a U groove. Because it concentrates on the department. As can be easily understood, the limit of the wide bandgap semiconductor with the wide bandgap can be interpreted as an insulator, and although there is a difference such as the presence or absence of a two-dimensional electron cloud, such a heterojunction. Also in the case of the gate structure, when a high voltage exceeding the rating is applied to the drain electrode, the bottom corner portion of the U-type wide bandgap semiconductor thin film is destroyed first.

In order to prevent the bottom corner of the U-type gate insulating film 6 from being destroyed first, design specifications such as excessive withstand voltage are required when forming the gate insulating film.
There is a secondary problem that the manufacturing cost of the semiconductor device increases. In particular, for forming a U-groove (trench),
Etching techniques, such as reactive ion etching (RI
In E), highly accurate control of the etching depth and control of the cross-sectional shape are required, and various devices for removing damage and contamination at the time of etching are required. As the element size becomes finer, the controllability of RIE becomes more difficult, and the manufacturing cost further increases. Further, various measures are required for a technique for forming a gate insulating film such as a gate oxide film, which leads to an increase in the number of steps, an increase in a manufacturing period, and an increase in manufacturing cost.

In view of the above problems, an object of the present invention is to improve the breakdown strength of a semiconductor device having a gate structure in a U-groove (trench).

Specifically, the bottom corner of the U groove, that is,
It is an object of the present invention to provide an insulated gate semiconductor device having a novel structure capable of relaxing an electric field concentrated on a bottom corner portion of a gate insulating film and improving a breakdown strength against a surge or the like.

Another object of the present invention is to have a high breakdown strength,
An object of the present invention is to provide an insulated gate semiconductor device capable of reducing conduction resistance such as on-resistance by eliminating the influence of JFET resistance as much as possible.

Still another object of the present invention is to alleviate an electric field concentrated on the bottom corner of a U-groove (trench) in which a thin-film semiconductor layer having a wide bandgap (wide bandgap) is formed, thereby reducing surges and the like. An object of the present invention is to provide a semiconductor device having a heterojunction gate, which can improve the breakdown strength.

Still another object of the present invention is to provide a method of manufacturing a semiconductor device having a gate structure in a groove having a high breakdown strength without increasing the number of steps.

It is still another object of the present invention to provide a method of manufacturing a semiconductor device which can easily suppress an increase in manufacturing cost and can achieve high breakdown strength and low on-resistance at the same time.

[0020]

In order to achieve the above object, the present invention provides a semiconductor region of a first conductivity type, a base region of a second conductivity type disposed inside the semiconductor region, A groove formed shallower than the deepest part in the region,
A first main electrode region of a first conductivity type disposed on the surface of the base region; a second main electrode region disposed below the base region; a gate insulating film formed on a side wall of the groove; And a control electrode embedded in the semiconductor device. Here, the “first conductivity type” and the “second conductivity type”
When the first conductivity type is n-type, the second conductivity type is p-type, and when the first conductivity type is p-type, the second conductivity type is n-type. Also, the “first main electrode region”
For example, in a MOSFET or a MOS static induction transistor (SIT) or the like, it means either a source region or a drain region, and in an IGBT, it means either an emitter region or a collector region. . The “second main electrode region” is a MOSFET
Or MOSSIT means either the source region or the drain region which does not become the first main electrode region, and the IGBT means either the remaining emitter region or the collector region which does not become the first main electrode region. are doing. That is, the “main electrode region” means an electrode region through which a main current flows. The main electrode region may be a region connected to the metal electrode via the main electrode lead-out region like a buried layer, or may be a region formed on the back surface of the substrate. That is, it does not matter whether the region is in direct contact with the metal electrode or indirectly connected. Similarly, the “control electrode” in the present invention means an electrode for controlling the main current, and means gate electrodes of MOSFET, MOSSIT, and IGBT.

According to the first feature of the present invention, the depth of the bottom of the trench is smaller than the diffusion depth of the deepest portion of the base region, and the depth of the trench is lower than the corner of the trench, ie, the bottom of the gate insulating film. The corner portion is covered by the base region.
The phrase “the deepest part of the base region” means that the depth of the base region is not uniform, and the other part, that is, the base region located at the center of the trench is shallow, so that the The bottom center has a structure in contact with the n-well region. That is, the base region has a curved bottom that is convex downward.

When the semiconductor device (device) according to the first aspect of the present invention is in a cutoff state, a high voltage is applied between the first and second main electrode regions. In order to prevent the base region from being in a floating state, the first main electrode region and the base region are usually used in a short-circuit state. For this reason, in the cutoff state, a predetermined high voltage equal to or lower than the rated voltage is applied between the base region and the second main electrode region, and the depletion layer extends at the junction between the base region and the semiconductor region. In this state, in the first aspect of the present invention, the bottom corner of the gate insulating film is covered with the base region, and the interface potential is maintained at the voltage value of the base region. For this reason, it is possible to reduce the concentration of the electric field on the corner at the bottom of the gate insulating film. Therefore, even when an abnormal high voltage or a surge voltage equal to or higher than the rated voltage is applied between the first and second main electrode regions in the cut-off state of the semiconductor device according to the first feature of the present invention, The bottom corner is less likely to break.

Preferably, in the first aspect of the present invention, the second main electrode region includes a main region having a substantially flat main surface, and a convex partial region extending from the main region to the bottom of the groove. What is necessary is just to comprise from. This convex-shaped partial region may be in contact with the bottom of the groove, or may be separated from the bottom of the groove. As described above, when the convex partial region is configured, in the conductive state of the semiconductor device according to the first aspect of the present invention, the carriers that constitute the main current flow from the first main electrode region side to the second main electrode. When moving to the area side,
The carriers can flow from the end of the base region through the semiconductor region or directly into the low-resistance convex partial region, and can flow into the external circuit through the main region of the second main electrode region. That is, the path of the carrier constituting the main current can be widened, and the on-resistance is dramatically reduced.

Further, according to the first feature of the present invention, if the semiconductor device further includes a lead-out region of the same conductivity type as the second main electrode region reaching the second main electrode region from the surface of the semiconductor region, The metal electrode for the second main electrode region can be taken out from the same surface, and a semiconductor device having a horizontal structure suitable for integration of an IPD, a logic integrated circuit, or the like can be obtained.
On the other hand, it is also possible to obtain a vertical structure semiconductor device in which the metal electrode for the second main electrode region is taken out from the back side, and the metal electrodes for the first and second main electrode regions are taken out from different main surfaces. For example, for an individual device (discrete device) for a large current, the vertical structure is an advantageous structure.

In the first feature of the present invention, the second feature
If the main electrode region is of the same first conductivity type as the first main electrode region, a unipolar device such as MOSFET or MOSSIT is obtained. If the second main electrode region is of the second conductivity type opposite to the first main electrode region, IGBTs, emitter switched thyristors (EST) and MOS controlled thyristors (MCT)
Of course, such a bipolar device can be produced.
In each of these unipolar devices and bipolar devices, since the bottom corner of the gate insulating film formed in the U-groove is protected by the base region, it is possible to realize a high breakdown strength when a surge or the like is applied. In addition, low on-resistance and low on-voltage can be achieved.

According to a second feature of the present invention, a semiconductor region of the first conductivity type, a base region of the second conductivity type disposed inside the semiconductor region, and shallower than the deepest portion in the base region. A groove, a first main electrode region of a first conductivity type disposed on the surface of the base region, a second main electrode region disposed below the base region, and a semiconductor region formed on a side wall of the groove. A semiconductor device is characterized by comprising at least a thin-film semiconductor layer having a wider bandgap than a base region and a control electrode embedded in a trench. For example, a semiconductor structure and a base region are made of gallium arsenide (GaAs), and a gate structure is formed as a thin film semiconductor layer of AlGaAs having a bandgap wider than the GaAs, whereby a HEMT or a HEMT-like heterojunction semiconductor device can be formed. It is.

Like the semiconductor device according to the first feature,
Even in a semiconductor device having such a HEMT or a HEMT-like heterojunction gate structure, destruction of the semiconductor device due to a high voltage such as a surge voltage can be effectively prevented. That is, when a high voltage is applied between the base region and the second main electrode region in the cutoff state and the depletion layer extends at the junction between the base region and the semiconductor region, the bottom of the thin film semiconductor layer having a wide bandgap is formed. Since the corner is covered with the base region, the interface potential is maintained at the voltage value of the base region. For this reason, it is possible to alleviate the electric field concentration on the corner at the bottom of the thin-film semiconductor layer having a wide forbidden band. According to a second feature of the present invention, a thin film semiconductor layer (channel layer) of the same material as a semiconductor region is formed in a trench, and a thin film semiconductor layer having a wide band gap is deposited on the thin film semiconductor layer. Alternatively, a two-dimensional electron cloud may be formed at the heterojunction interface.

A third feature of the present invention resides in a step of forming a semiconductor region of the first conductivity type and a step of forming a second region inside the semiconductor region.
Forming a conductive type base region; forming a first conductive type first main electrode region on the surface of the base region; forming a groove portion shallower than the deepest portion in the base region;
A method of manufacturing a semiconductor device, comprising at least a step of forming a gate insulating film on a sidewall of a groove and a step of burying a control electrode inside the groove, wherein the semiconductor region is formed above the second main electrode region. It is.

The method of manufacturing a semiconductor device according to the third aspect of the present invention is basically similar to the method of manufacturing a conventional insulated gate semiconductor device, and does not increase the number of steps. And
In the same process as the conventional method of manufacturing an insulated gate semiconductor device, the etching depth of the trench (trench) is made slightly shallower than the deepest portion in the base region, so that the bottom corner portion of the gate insulating film is formed. Is easily covered with the base region. Therefore, it is possible to provide a highly reliable semiconductor device having a high breakdown strength while suppressing an increase in manufacturing cost.

Further, in the method of manufacturing a semiconductor device according to the third aspect of the present invention, the second main electrode region has a main region having a substantially flat main surface, and the conductivity type of the main region is changed. It is preferable to further include a step of selectively introducing another impurity having a diffusion coefficient larger than the diffusion coefficient of the impurity to be determined into the main region to form a partial region. If a partial region is formed by selectively introducing an impurity having a large diffusion coefficient, a subsequent heat treatment step is performed toward the bottom of the groove where the control electrode is formed, and a convex shape is formed on the main region. A partial region (partially buried region) is formed. Therefore, when the carrier constituting the main current moves from the side of the first main electrode region to the side of the second main electrode region, the carrier is formed from the end of the base region via the semiconductor region or directly into a low-resistance convex shape. A structure that flows into the partial region and flows into the external circuit through the main region of the second main electrode region can be easily manufactured. As a result, it is possible to easily manufacture a semiconductor device having a wide on-path of the carrier constituting the main current and low on-resistance.

For example, a second region including a main region and a partial region
If the upper region of the main electrode region is a semiconductor region with a relatively low impurity density and the lower region of the second main electrode region is a semiconductor substrate with a relatively high impurity density, heat diffusion accompanying a subsequent heat treatment step allows for more diffusion. Since the impurities are diffused in a direction in which the impurities are easily diffused, that is, toward the semiconductor region having a relatively low impurity density, it is possible to cause upward diffusion of the impurities. If a region below the second main electrode region is a semiconductor substrate having a relatively low impurity density, the region also has a convex shape below. By diffusing impurities in the partial region upward, it is possible to easily obtain a structure in which the bottom corner of the gate insulating film is covered with the base region and the central bottom portion of the gate insulating film is in contact with the high impurity density partial region. Becomes By selecting the heat treatment conditions, a structure in which the high impurity density partial region is not in contact with the bottom central portion of the gate insulating film is also possible, and the low impurity density region is provided between the insulating film bottom central portion and the high impurity density partial region. A high withstand voltage can be achieved by sandwiching the semiconductor region. For example, if the impurity that determines the conductivity type of the main region of the second main electrode region is n-type, a combination of phosphorus (P) and antimony (Sb) can be adopted. The diffusion coefficient at a thermal diffusion temperature of about 1200 ° C. is about 5 × 10 ⁻¹² cm ^2.
s ^-1 , antimony (Sb) is about 5 × 10 ^-13 cm ² · s
^-1 different from ^-1 digit. Therefore, when heat treatment is performed at the same time, phosphorus (P) diffuses deeper, and only phosphorus (P) can realize an impurity profile extending in a convex shape. On the other hand, if the impurity that determines the conductivity type of the second main electrode region is p-type, aluminum (Al) and boron (B)
Can be adopted.

[0032]

According to the present invention, there is provided an insulated gate semiconductor device in which an electric field concentrated on the bottom corner of a U-groove (trench) in which a gate insulating film is formed is alleviated, and a breakdown strength against a surge or the like is improved. Can be provided.

According to the present invention, it is possible to provide a high-efficiency insulated gate semiconductor device having a high breakdown strength and a small conduction loss.

According to the present invention, there is provided a heterojunction gate in which the electric field concentrated on the bottom corner of the U-groove (trench) in which the wide bandgap thin film semiconductor layer is formed is relaxed, and the breakdown resistance against a surge or the like is improved. A semiconductor device having the same.

According to the present invention, it is possible to provide a method of manufacturing a semiconductor device capable of alleviating an electric field concentrated on the bottom corner of a U-shaped groove and improving the breakdown strength against a surge or the like.

According to the present invention, it is possible to provide a method of manufacturing a semiconductor device capable of simultaneously increasing the breakdown resistance and reducing the conduction resistance.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The first to fourth embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, it should be noted that the drawings are schematic, and dimensions in the thickness and planar structure, and relationships and ratios of the dimensions are different from actual ones.

(First Embodiment) FIG. 1 shows a horizontal UMO as a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is an enlarged view of the periphery of the U-shaped gate electrode 7. Here, FIG. 1 is a cross-sectional view along the AA direction of the plan view shown in FIG. 3, and FIG.
3 is a diagram showing a part of a cross section along the BB direction in the plan view shown in FIG.

As shown in FIG. 1, the lateral UMOSFET according to the first embodiment of the present invention has a first conductivity type (n
Semiconductor region 3, a second conductivity type (p-type) base region (p base region) 4 disposed inside the semiconductor region 3, and formed shallower than the deepest portion in the p base region 4. Groove, the first main electrode region 5 of the first conductivity type (n-type) disposed on the surface of the p base region 4, and the second main electrode region (n ⁺⁾ disposed below the p base region 4. A drain region 2, a gate insulating film 6 formed on the side wall of the trench,
And at least a control electrode 7 embedded in the groove. Specifically, a p-type semiconductor substrate (p substrate 1)
On top of the p-type epitaxial layer (p epitaxial layer 3
0) is formed, and the semiconductor region 3 is formed as an n-type well region (n-well region) 3 inside the p epitaxial layer 30. Then, in this n-well region 3, p
A base region 4 is configured. n in p base region 4
A first main electrode (source electrode) 9 is ohmic-connected to the first main electrode region (n ⁺ source region) 5 of the mold. This source electrode 9 is arranged such that n ⁺ source region 5 and p base region 4 are short-circuited.

Further, as shown in FIG.
The lateral UMOSFET according to the embodiment further has a lead-out region (sinker) 8 of the same conductivity type (n-type) as the second main electrode region 2 reaching the second main electrode region 2 from the surface of the semiconductor region 3. . This second main electrode lead-out region (n
⁺ Drain extraction region) 8, a second main electrode (drain electrode) 10 arranged on the surface of the semiconductor region (n-well region) 3 and an n-type high impurity density region ( The second main electrode region 2, which is a buried layer, is electrically connected. Thus, this UMO
The SFET has a so-called “horizontal UMOST” in which a drain electrode 10 and a source electrode 9 are arranged on the same main surface.
ET (lateral UMOS) ". Then, on the same main surface, the second-layer drain electrode 10 and the source electrode 9 are electrically separated via the second-layer interlayer insulating film 12 to form a two-layer wiring structure in which the two layers are arranged one above the other.

As shown in the enlarged view of FIG.
The lateral UMOSFET according to the embodiment has a groove-shaped cross-sectional structure, the depth of the groove is smaller than the diffusion depth of the deepest part of the p base region 4, and the bottom corner of the gate insulating film 6 is formed in the p base region 4. Covered in. "The deepest part of the p base region 4" means that the depth of the p base region 4 is not uniform, and as shown in FIG. Since the p base region to be formed is shallow, the center of the bottom of the gate insulating film 6 is
The structure is in contact with. That is, the lateral UMOSFET according to the first embodiment of the present invention is composed of a plurality of p base regions 4 in cross section, and each of the p base regions 4 has a downwardly convex curved bottom. That is, the bottom surface of the p base region near the interface where the adjacent p base regions 4 are in contact with each other is designed to be shallow, and this portion is designed to be located exactly at the center of the bottom of the gate insulating film 6. The control electrode (U-type gate electrode) 7 embedded in the groove may be made of, for example, a polycrystalline silicon (n ⁺ doped polysilicon) film doped with an n-type impurity. Instead of n ⁺ doped polysilicon, tungsten (W), titanium (T
i), using a high melting point metal such as molybdenum (Mo)
When the gate electrode 7 is formed, the gate resistance is reduced, so that high-speed operation and uniform operation in a large area can be performed. Further, a refractory metal silicide (WSi ₂ , Ti
It is also possible to use Si ₂ , MoSi ₂ ) or polycide using these silicides.

As shown in FIG. 3, the plan shape of the n ⁺ source region 5 is a donut shape, and the center of the donut is the p base region 4. Various geometric shapes such as a circular donut shape, a rectangular donut shape, or a polygonal donut shape can be adopted as the planar shape of the n ⁺ source region 5. The outside of the donut shape is surrounded by the U-shaped gate electrode 7, and the U-shaped gate electrode 7 is formed in a lattice shape. In the present invention, a region where the n ⁺ source region 5 is surrounded by the U-type gate electrode 7 is called a “source cell”. The source cells 16 are periodically arranged in a square mesh at a predetermined pitch. One drain cell 15 has a large area corresponding to the area occupied by the area occupied by the four (2 × 2 arrangement) source cells 16 and their spacing. That is, the pattern of one drain cell 15 is arranged in a specific 2 × 2 array portion periodically selected in the matrix pattern composed of the array of source cells 16. Therefore, the region where the n ⁺ drain extraction region 8 is surrounded by the U-shaped gate electrode 7 is a “drain cell”, and a plurality of drain cells are regularly arranged in a matrix.

As a result, as shown in FIG. 3, one row of source cells 16 is arranged around one drain cell 15. Two rows of source cells 16 are arranged between the two drain cells 15. With this pattern arrangement as a basic pattern, a plurality of source cells 16 and drain cells 15 are periodically arranged by the number corresponding to the rated current. In addition to the above-described planar configuration in which the rectangular cells are arranged, other planar arrangements are possible. For example, a striped or interdigital (interdigital) cell pattern may be used, and a planar pattern in which a plurality of these are arranged may be used.

As shown in FIG. 3, the p base region 4 is a plurality of regions patterned for each source cell 16 at the same pitch as the pattern of the source cells 16. The p base region 4 located at the outermost periphery is configured as a continuous region. The outer peripheral portion of each p base region 4 corresponding to the source cell 16 located on the inner side extends to the vicinity of the center of the U-shaped gate electrode 7. The outermost peripheral portion of the diffusion region of n well region 3 has a pattern shape surrounding the outermost peripheral portion of p base region 4. In FIG. 3, the corners of the lattice pattern formed by the U-shaped gate electrode 7 or the corners of the rectangular pattern of the drain opening and the source opening may be rounded. The rounding of the corner makes it possible to reduce the electric field concentration on the surface of the semiconductor substrate.

In the lateral UMOSFET according to the first embodiment of the present invention shown in FIGS. 1 to 3, when a positive voltage is applied to the U-type gate electrode 7 with respect to the n ⁺ source region 5, the U-type gate electrode The surface of p base region 4 in contact with 7 is inverted to n-type. As a result, a channel is formed in the vertical direction near the U-type gate insulating film 6 along the side surface of the groove. n
^{When a} forward bias voltage is applied between the ⁺ source region 5 and the n ⁺ drain extraction region 8, that is, a voltage that makes the potential on the n ⁺ drain extraction region 8 side higher than the n ⁺ source region 5, the electrons become n ⁺ The source region 5 is vertically injected into the semiconductor region (n-well region) 3 from the lower end face of the p base region 4 through the channel.

In this case, (a) in a region of one row (12) of source cells 16 surrounding one drain cell 15, that is, in a region where the source cell 16 and the drain cell 15 face each other,
The injected electrons pass through the n-well region 3 in the lateral direction (horizontal direction to the substrate) and are guided to the n ⁺ drain extraction region 8. In this case, the current component passing through the second main electrode region (n ⁺ buried layer) 2 is small. (B) On the other hand, two rows of source cells 16 are arranged between two drain cells 15, and a region sandwiched between the two rows of source cells 16, that is, the source cells 16 are arranged.
On the side not facing the drain cell 15, the injected electrons pass vertically through the n-well region 3 (perpendicular to the substrate).
The second main electrode region (n ⁺ buried layer) 2 is reached. Then, the electrons further pass through the n ⁺ buried layer 2 in the horizontal direction and rise in the vertical direction in the n ⁺ drain extraction region 8. In any case, n-well region 3 functions as a drift layer for electrons.

In a device cut-off state in which a negative or zero voltage is applied to the U-type gate electrode 7 with respect to the n ⁺ source region 5, a high voltage is applied between the source and the drain. A depletion layer extends at the junction with the n-well region 3. However, in the lateral UMOSFET according to the first embodiment of the present invention, the interface potential at the bottom corner of the U-type gate insulating film 6 is kept at the voltage value of the p base region 4. Therefore,
Even when an abnormal high voltage or a surge voltage exceeding the rated value is applied, the electric field concentration on the bottom corner of the U-type gate insulating film 6 can be reduced, and the horizontal UMO
Destruction of the SFET can be prevented.

In the lateral UMOSFET according to the first embodiment of the present invention, the source contact portion
The groove structure may be used, and the ohmic contact may be made on the U groove side surface. By adopting such a structure,
Since the projected area of the contact portion can be further reduced, and the cell size can be reduced, the on-resistance per unit area can be further reduced.

Next, referring to FIGS. 4 to 7, the horizontal UMOS according to the first embodiment of the present invention shown in FIGS. 1 to 3 will be described.
A method for manufacturing an FET will be described.

(A) Impurity density 1 × 10 ¹⁴ cm ^{-3 to} 2 ×
A p substrate 1 of about 10 ¹⁶ cm ⁻³ is prepared. By thermal oxidation
As shown in FIG. 4A, a thickness of 350 nm
A first oxide film 41 of about 1 μm is formed. Then, using a photolithography technique, a diffusion window is opened in the first oxide film, and an n-type impurity is selectively introduced from the diffusion window. For example, antimony ions (Sb
⁺ ) Is ion-implanted under the conditions of an acceleration energy of about 50 to 150 KeV and a dose of about 3 × 10 ^{15 to} 3 × 10 ¹⁶ cm ⁻² , and a substrate temperature of about 1100 ° C. to 1200 ° C.
Then, thermal diffusion is performed for a predetermined time, and an n ⁺ diffusion layer (n ⁺ buried layer) 17 as a second main electrode region as shown in FIG.
To form Since the diffusion coefficient of Sb is small and the solid capacity is small, it is used when forming an embedded region.
Alternatively, n ⁺ buried layer 17 may be formed using arsenic (As). After that, the first oxide film 41 is removed, and p
As shown in FIG. 4B, a p-type epitaxial layer 30 having a thickness of several μm to ten and several μm is grown on the substrate 1 by vapor phase epitaxial growth. At this time, in the vapor phase epitaxial growth, monosilane (SiH ₄ ), dichlorosilane (SiH ₂ Cl ₂ ), and trichlorosilane (Si
HCl ₃ ) or silicon tetrachloride (SiCl ₄ ) at a substrate temperature of 1 using hydrogen (H ₂ ) or the like as a carrier gas.
The growth may be performed at 050 ° C. to 1250 ° C. In order to form a p-type semiconductor region, a predetermined amount of a dopant gas such as a gas containing a small amount of diborane (B ₂ H ₆ ) may be added during growth by controlling the gas in a predetermined amount by a mass flow controller or the like. Alternatively, it may be grown using a liquid source such as trichlorosilane (SiHCl ₃ ) containing a small amount of boron (B) as a dopant, such as silicon tetrachloride (SiCl ₄ ).

(B) Next, on the p epitaxial layer 30,
A second oxide film having a thickness of 350 nm to 1 μm is formed. Then, using a photolithography technique, a diffusion window is opened in the second oxide film, and the first conductivity type (n
N-type impurities for forming the semiconductor region (n-well region) 3 of the (type). The introduction of the n-type impurity for forming the n-well region 3 may be performed by ion implantation using a photoresist or a metal film as a mask. That is, after forming a predetermined diffusion mask, an impurity is selectively introduced into the pattern (n-well region) 3 of the diffusion region shown in the plan view of FIG. For example, a phosphorus ion (P
⁺ ) With an acceleration energy of about 100 KeV to 2 MeV,
Ion implantation is performed at a dose of about 5 × 10 ^{12 to} 5 × 10 ¹³ cm ⁻² and a substrate temperature of about 1100 ° C. to 1200 ° C.
Then, heat treatment (drive-in) is performed for a predetermined diffusion time. This diffusion time may be determined in consideration of the thickness of the p epitaxial layer 30. As a result, as shown in FIG.
The bottom of well region 3 reaches n ⁺ buried layer 17.
Although not shown, when the n ⁺ drain extraction region 8 is formed of an n ⁺ diffusion region, the n well region 3
Before the diffusion (drive-in), a diffusion mask is similarly formed for the n ⁺ drain extraction region 8, and n-type impurity ions such as phosphorus ions (P ⁺ ) are selectively ionized into the drain cell formation region. Infusion must be done.
The conditions for this ion implantation are, for example, acceleration energy: about 100 KeV to 2 MeV, and dose: about 5 × 10 ^{15 to} 5 × 10 ¹⁶ cm ⁻² . By doing so, the bottom of the n ⁺ drain extraction region 8 reaches the n ⁺ buried layer 17 simultaneously with the bottom of the n well region 3 by the heat treatment (drive-in) for a predetermined diffusion time. Thus, n ⁺ buried layer 17 is formed at a position between n well region 3 and p substrate 1.

(C) Next, the p in which the n-well region 3 is formed
A third oxide film having a thickness of 350 nm to 1 μm is formed on the entire surface on the epitaxial layer 30. Then, using a photolithography technique, a diffusion window is opened in the third oxide film, and a p-type impurity for forming a second conductivity type (p-type) base region (p base region) 4 from the diffusion window is formed. Is introduced. P-type impurities for forming the p-base region 4 may be ion-implanted using a photoresist or the like as a mask. The p base region diffusion mask has a pattern having a window for each source cell 16 shown in FIG. For example, boron ions (B ⁺ ) as p-type impurities are accelerated at an energy of about 30 to 100 KeV and a dose of about 2 × 1.
Ion implantation is performed under the conditions of 0 ^{13 to} 1 × 10 ¹⁵ cm ⁻² , thermal diffusion is performed at a substrate temperature of about 1100 ° C. to 1200 ° C. for a predetermined time, and a depth of 1 μm to 20 μm as shown in FIG.
An approximately m p-base region 4 is formed.

(D) The third oxide film is removed, and a thickness of 350 is formed on the entire surface of the n-well region 3 and the p-type epitaxial layer 30 in which the p-base region 4 is formed inside the n-well region 3.
A fourth oxide film of nm to 1 μm is formed. Then, a diffusion window is opened in the fourth oxide film by using a photolithography technique, and a first main electrode region (n ⁺ source region) 5 of a first conductivity type (n type) is formed from the diffusion window. Is introduced. The n-type impurity for forming the n ⁺ source region 5 may be ion-implanted using a photoresist or the like as a mask. As shown in FIG. 5E, since the n ⁺ source region 5 is formed in a very shallow region, arsenic ions (As ⁺ ) having a small diffusion coefficient as an n-type impurity
Is implanted under the conditions of an acceleration energy of about 30 to 80 KeV and a dose of about 1 × 10 ^{15 to} 4 × 10 ¹⁶ cm ⁻² , and thermal diffusion is performed at a substrate temperature of about 800 ° C. to 1000 ° C. for a predetermined time. . In order to form the n ⁺ source region 5 shallowly, a high-speed annealing (R
TA) may be performed.

(E) The fourth oxide film is removed, and a fifth oxide film (cover film) 21 is formed on the entire surface on the p epitaxial layer 30.
To form Since this cover film 21 is for forming an etching mask for forming a groove (trench) 20 as shown in FIG.
And the etching selectivity between silicon and the oxide film. Then, using a photolithography technique, the cover film 21 is patterned in a grid pattern like the pattern of the U-shaped gate electrode 7 shown in FIG. The patterning of the cover film 21 may be performed by RIE using a photoresist as a mask. Then, the photoresist used for patterning the cover film 21 is removed.
Is used as a mask to perform anisotropic etching of silicon.
Since the trench 20 has a high aspect ratio, the silicon anisotropic etching is performed using a mixed gas of SiCl ₄ and chlorine (Cl ₂ ), a mixed gas of boron trichloride (BCl ₃ ) and Cl ₂ , or sulfur fluoride. RIE or ECR ion etching (or microwave plasma etching) using (SF ₆ ) or the like may be used. These RIE and EC
For anisotropic etching such as R ion etching,
Use of side wall protection film, and substrate temperature of -30 ° C to -14 ° C
By using the low-temperature control process at 0 ° C., the side wall of the trench 20 can be processed vertically. As a result, FIG.
As shown in (f), a trench 20 is formed between two adjacent p base regions. As shown in FIG. 6F, the etching depth is controlled so that the depth of the trench 20 is slightly smaller than the depth of the deepest part of the p base region 4. Thus, a structure in which the bottom corner of trench 20 is covered by p base region 4 and the center of the bottom is in contact with n well region 3 can be obtained. Note that the n ⁺ source region 5 is separated and exposed above the sidewall of each trench 20.

(F) A thin oxide film (sacrificial oxide film) is formed on the side wall of the trench 20, and the sacrificial oxide film is further removed. The process of forming and removing the sacrificial oxide film is performed when there is a concern about damage due to excessive discharge energy during the etching of the trench 20, or when there is a concern about contamination of the sidewall of the trench with a heavy metal or an etching gas component. This can be omitted in some cases. In any case, after cleaning the side wall of the trench 20, gate oxidation is performed,
As shown in FIG. 6 (g), a thickness of 30 nm to 150 nm
U-shaped gate insulating film 6 is formed. The gate oxidation may be dry oxidation, wet oxidation by burning hydrogen (H ₂ ), or may be performed by mixing hydrochloric acid (HCl) during dry oxidation. In FIG. 6G, the cover film 21 and the U-type gate insulating film 6 are shown as a continuous oxide film.

(G) As shown in FIG. 7H, the control electrode (U-type gate electrode) 7 is formed by embedding n ⁺ -type polycrystalline silicon (n ⁺ -doped polysilicon) in the trench 20. Is formed. The n ⁺ -doped polysilicon is formed by depositing polysilicon to which impurities are not added by low-pressure CVD or normal-pressure CVD, and then adding phosphorus oxytrichloride (POCl ₃ ).
It can be formed by introducing an n-type impurity such as vapor phase diffusion (pre-deposition) using. Instead of gas phase diffusion (predeposition), ion implantation of n-type impurity ions such as P and As may be used. Alternatively, it is also possible to directly deposit n ⁺ -doped polysilicon by using an n-type dopant gas containing phosphine (PH ₃ ) or the like during low-pressure CVD or normal-pressure CVD.

(H) As shown in FIG. 7I, the n ⁺ -doped polysilicon is etched back, and a conductive material for a control electrode (gate electrode) is embedded in the trench 20.
N ⁺ -doped polysilicon may be embedded inside trench 20 using chemical mechanical polishing (CMP). Thereafter, hydrofluoric acid (HF) / ammonium fluoride (NH)
₄ F) using an oxide film etchant of the mixed solution or the like to remove the cover film 21. As a result, n ⁺ -doped polysilicon projects above trench 20. Then, if the n ⁺ -doped polysilicon is oxidized and selectively etched, a cap oxide film 22 is formed on the U-type gate electrode 7 as shown in FIG.

(1) Thereafter, the first interlayer insulating film 1 is formed on the p epitaxial layer 30 including the cap oxide film 22.
1 is formed by a CVD method or the like (see FIG. 1). And
Using a photolithography technique, a first drain contact hole and a source contact hole are opened at desired locations in the first interlayer insulating film 11 at desired locations.
At this time, since the cap oxide film 22 is formed on the U-type gate electrode 7, a window of a photoresist is formed in a wide area including a plurality of source cells, and the first interlayer insulating film 11 is etched. A source contact hole can be opened only in the upper part of the source cell in a self-aligned manner. Since the drain cell has a relatively large area, even if the first drain contact hole is opened by mask alignment, the mask displacement is
Almost no problem. After opening the contact hole, a conductive material is deposited by a sputtering method or a vacuum evaporation method such as electron beam (EB) evaporation. As the conductive material for forming the electrode, Al-Si, Al-Cu, A
An Al alloy such as l-Si-Cu may be used. And
The source electrode 9 and the first layer drain electrode 10 are patterned by photolithography and RIE (see FIG. 1). Further, on the source electrode 9 and the first layer drain electrode 10, an oxide film (NSG film), PSG
A second interlayer insulating film 12 made of a film, a BPSG film, or a composite film of these films is deposited by a CVD method. Thereafter, by heating at a temperature of 850 ° C. to 950 ° C., heat flow (reflow) is caused to flatten a portion of the second interlayer insulating film 12 where the unevenness is severe. In some cases, CMP
May be used to flatten the surface. Thereafter, a second drain contact hole is formed in the second interlayer insulating film 12 by photolithography and RIE. Further, a conductive material such as an Al alloy is deposited by a sputtering method or a vacuum evaporation method such as an EB evaporation method. Finally, if the second layer drain electrode 13 is formed by patterning a conductive material by photolithography and RIE, the lateral UMOF according to the first embodiment of the present invention can be obtained.
ET is completed. On top of this, NSG film, PSG film, BP
A final passivation film such as an SG film, a silicon nitride film (Si ₃ N ₄ film), or a polyimide film may be deposited.
In addition, as for the method of forming the electrode portions 9, 10, and 13 of the two-layer wiring structure, it is needless to say that various conventionally known methods other than the method described above can be adopted.

(Second Embodiment) FIG. 8 is a sectional structural view of a lateral UMOSFET according to a second embodiment of the present invention. This cross-sectional structure diagram corresponds to A in the plan view shown in FIG.
It is -A sectional drawing.

As shown in FIG. 8, the lateral UMOSFET according to the second embodiment of the present invention has a first conductivity type (n
) Semiconductor region (n-well region) 3, a second conductivity type (p-type) base region (p base region) 4 disposed inside the semiconductor region 3, and a deepest region in the p base region 4. And a first main electrode region (n) of a first conductivity type (n type) disposed on the surface of p base region 4.
⁺ Source region) 5 and a second main electrode region (2, 24) of the first conductivity type (n-type) disposed below the p base region 4
And a gate insulating film 6 formed on the side wall of the groove, and a control electrode 7 buried inside the groove. N-type high impurity density second main electrode region (2, 24)
Is formed on a semiconductor substrate of the second conductivity type (p type) (p substrate 1) and functions as an n ⁺ drain region. And
The second main electrode region (2, 24) includes a main region (buried layer) 2 having a substantially flat main surface, and a convex partial region (n ⁺ portion) extending from the main region 2 to the bottom of the groove. (Buried layer) 24.

Further, the second main electrode region 2 reaching the second main electrode region (buried layer) 2 from the surface of the semiconductor region 3
And an extraction region (n ⁺ drain extraction region) 8 of the same conductivity type (n type). A first main electrode (source electrode) 9 is connected to the n ⁺ source region, and a first layer second main electrode (first layer drain electrode) 10 is connected to the n ⁺ drain extraction region 8.
Is connected. That is, the first-layer drain electrode 10 and the second main electrode region 2 are electrically connected with low resistance by the n ⁺ drain extraction region 8. And the source electrode 9
N ⁺ source region 5 and p base region 4 are short-circuited.

As shown in FIG. 8, the depth of the groove is smaller than the diffusion depth of the deepest part of the base region 4, and the bottom corner of the groove is covered with the base region 4. The convex partial region (n ⁺ partial buried layer) 24 faces the bottom of the gate insulating film 6 below the U-shaped gate electrode 7 and is in contact with the bottom. Further, the lateral UMOSFET in FIG. 8 is a so-called lateral UMOSFET in which the drain electrode 10 is arranged on the surface of the semiconductor substrate, and the second-layer drain electrode 1 is disposed on the upper surface of the semiconductor substrate via the second-layer interlayer insulating film 12.
3 and a source electrode 9 have a two-layered wiring structure in which they are vertically overlapped.

FIG. 9 is a plan view corresponding to the sectional structural view of the horizontal UMOSFET of FIG. Here, in particular, the planar arrangement of the drain cell 15 and the source cell 16 and the respective regions of the n well region 3, the p base region 4, and the n ⁺ partial buried layer 24 are shown. As in the first embodiment, n ⁺
The planar shape of the source region 5 is a donut shape,
The p base region 4 is exposed at the center of the donut. The outside of the donut shape is surrounded by a U-shaped gate insulating film 6 and a U-shaped gate electrode 7. The U-shaped gate electrode 7 is formed in a lattice shape. In the cutout on the upper left of FIG.
A relatively lower n ⁺ partially buried layer 24 is shown. The n ⁺ partial buried layer 24 at a horizontal level (depth) near the lower main region 2 has a continuous and uniform pattern. However, as can be easily understood by referring to FIG. 8, at a horizontal level (depth) near the p base region 4, the n ⁺ partial buried layer 24 corresponds to the pattern of the U-type gate electrode 7. It becomes a pattern.

As shown in FIG. 9, the p base region 4 is a plurality of regions patterned at the same pitch as the pattern of the source cell 16. The p base region 4 located at the outermost periphery is configured as a continuous region.
The respective outer peripheral portions of the p base region 4 corresponding to the source cells 16 located inside extend to near the center of the U-shaped gate electrode 7. Although not shown, the outer peripheral portion of the p-type base region 4 is surrounded by the outer peripheral portion of the n-well region 3, and the outside is further surrounded by the p-type semiconductor region. As described above, the IPD is electrically separated from other elements or circuits by the so-called “pn junction isolation structure”. The n ⁺ buried layer 2
On the plane pattern, it is located almost immediately below the n-well region 3. The n ⁺ partial buried layer 24 becomes a pattern disposed inside the n ⁺ buried layer 2. Other pattern arrangements of the source cell 16 and the drain cell 15 are the same as those in the first embodiment.
Since the third embodiment is the same as the first embodiment, the description is omitted.

The operation of the lateral UMOSFET according to the second embodiment of the present invention shown in FIGS.
The operation is substantially the same as the operation of the lateral UMOSFET according to the embodiment. That is, between the n ⁺ source region 5 and the n ⁺ drain lead region 8, the potential of the n ⁺ drain lead region 8 side while applying a voltage higher than the n ⁺ source region 5, n ⁺ source region 5 When a positive voltage is applied to U-type gate electrode 7, the surface of p base region 4 in contact with U-type gate electrode 7 is inverted to n-type, and a channel is formed in the vicinity of U-type gate insulating film 6 in the vertical direction. You. As a result,
The electrons pass vertically through the channel from the n ⁺ source region 5 and p
The semiconductor region (n-well region) 3 or the n ⁺ partial buried layer 24 is implanted from the lower end face of the base region 4.

In this case, in the first embodiment, a region corresponding to one column (12) of source cells 16 surrounding one drain cell 15, that is, the source cell 16 and the drain cell 15 are formed. The electron flow in the opposing region and the two rows of source cells 16 between the two drain cells 15
Is a region sandwiched between two rows of source cells 16 in the arrangement,
That is, a remarkable difference in the electron flow (path) from the electron flow on the side of the source cell 16 not facing the drain cell 15 was shown. However, in the second embodiment of the present invention, the flow of electrons in these two regions is significantly similar due to the presence of the n ⁺ partial buried layer 24.

If the n ⁺ partial buried layer 24 is in contact with the U-type gate insulating film 6 or is located near the U-type gate insulating film 6, the n ⁺ partial buried layer 24 is located on the side of the source cell 16 facing the drain cell 15. Most of the electrons injected into the n-well region 3 also flow into the n ⁺ partial buried layer 24 having a low potential for electrons. Therefore, the ratio of electrons guided to the n ⁺ drain extraction region 8 through the n-well region 3 in the lateral direction is smaller than that in the first embodiment. Then, the current component passing through the second main electrode region (n ⁺ buried layer) 2 via the n ⁺ partial buried layer 24 becomes relatively large. On the other hand, among the source cells 16, the drain cells 15
On the side that is not opposed to the above, electrons injected into the n-well region 3 flow into the n ⁺ partial buried layer 24 having a low potential for electrons. Alternatively, if the n ⁺ partial buried layer 24 is in contact with the U-type gate insulating film 6, electrons are directly injected from the p base region 4 into the n ⁺ partial buried layer 24. n ⁺
Since the partial buried layer 24 has an upwardly convex shape, the injected electrons or the inflowing electrons reach the second main electrode region (n ⁺ buried layer) 2 having a low specific resistance at a wide angle.
Then, further through the n ⁺ buried layer 2 laterally, n ⁺
In the drain extraction region 8, electrons rise in the vertical direction. As described above, since the n ⁺ partial buried layer 24 has an upwardly convex shape, the electron path under the U-type gate insulating film 6 has a wide angle, and the electric resistance of the path is small, so that the on-resistance is greatly increased. To be reduced. That is, by forming the n ⁺ partial buried layer 24 into a convex shape, the horizontal UMO
The advantage that the JFET resistance, which is a feature of the SFET, is small can be made more remarkable. As a result, the on-resistance can be easily reduced even in a fine structure in which the arrangement pitch of the source cells is shortened.

On the other hand, in the device cut-off state in which a negative or zero voltage is applied to the U-type gate electrode 7 with respect to the n ⁺ source region 5, the p base region 4 and the n ⁺ partial buried layer (after thermal diffusion) 24 A depletion layer extends at the junction. The bottom corner of the U-type gate insulating film 6 is protected from a direct high voltage by a depletion layer, and the interface potential is maintained at the voltage value of the p base region 4. Therefore, it is possible to reduce the electric field concentration on the bottom corner of the U-type gate insulating film 6.

In the lateral UMOSFET according to the second embodiment of the present invention, the source contact portion and the drain contact portion have a U-groove structure, and the ohmic contact with the metal electrode is made on the U-groove side surface, or WS
Deformation such that ohmic contact is made on the side surface of the U groove via silicide of a refractory metal such as i ₂ , TiSi ₂ , or MoSi ₂ may be added. By employing such a structure, the projected area of the contact portion can be further reduced. Therefore, the cell size can be reduced, and the on-resistance per unit area can be further reduced.

Next, referring to FIGS. 10 to 13, the horizontal UM according to the second embodiment of the present invention shown in FIGS.
A method for manufacturing an OSFET will be described.

(A) First, the same p as in the first embodiment is used.
A substrate 1 is prepared. Then, a first oxide film is formed on the p substrate 1 by thermal oxidation, a diffusion window is opened in the first oxide film using photolithography technology, and an n-type impurity is selectively introduced from the diffusion window. I do. For example, antimony ion (Sb ⁺ ) is used as an n-type impurity having a small diffusion coefficient.
Is implanted under the conditions of an acceleration energy of about 50 to 150 KeV and a dose of about 1 × 10 ^{15 to} 8 × 10 ¹⁶ cm ⁻² . Thereafter, the substrate temperature is about 1100 ° C. to 1200
Thermal diffusion is performed at a temperature of ° C. for a predetermined time to form an n ⁺ diffusion layer (n ⁺ buried layer) 17 as a second main electrode region. further,
As shown in FIG. 10A, a second oxide film 42 is formed on the p substrate 1, and the second oxide film 42 is formed by using a photolithography technique.
A diffusion window is opened in the second oxide film 42, and an n-type impurity having a large diffusion coefficient is selectively introduced from the diffusion window. As an n-type impurity having a large diffusion coefficient, for example, phosphorus ions (P
⁺ ) Can be used. Phosphorus ions (P ⁺ ) have an acceleration energy of about 30 to 130 KeV and a dose of about 8 × 10
Ion implantation is performed under conditions of ^{14 to} 5 × 10 ¹⁵ cm ⁻² , and thermal diffusion is performed at a substrate temperature of about 1000 ° C. to 1200 ° C. for a predetermined time to form an n ⁺ partial buried layer (before thermal diffusion) 23.
At this time, phosphorus ions (P ⁺ ) are simultaneously ion-implanted also into a portion corresponding to a region immediately below the region where the n ⁺ drain extraction region is to be formed, to form a drain extraction region buried layer (not shown). In the case, p substrate 1
Form other oxide film above, during the addition of the oxide film, n ⁺ outside the buried layer 17, n ⁺ buried layer 17 opening in the diffusion window at a position surrounding the boron ions from the diffusion window ( B ⁺ ) or the like may be selectively introduced.

(B) After that, the first oxide film and the second oxide film 42 are removed, and as shown in FIG. 10B, impurities having a thickness of 10 μm to 100 μm are formed on the p substrate 1 by vapor phase epitaxial growth. Density 5 × 10 ¹² cm ^{-3 to} 8 × 10
An n epitaxial layer ^{3 of} about ¹⁵ cm ^-3 is grown. In order to form an n-type semiconductor region (epitaxial layer), phosphine (PH ₃ ) or arsine (AsH ₃ ) is added as a dopant gas during growth. Further, the third oxide film is formed on the n epitaxial layer 3, by using a photolithography technique, in the third oxide film on the outside of the n ⁺ buried layer 17, p-well at a position surrounding the n ⁺ buried layer 17 A diffusion window for forming is opened. Through the diffusion window for forming the p-well, p-type impurities such as boron ions (B ⁺ ) are added, for example, at an acceleration energy of about 100 KeV to 3 M.
Ion implantation is performed at eV and a dose of about 5 × 10 ^{13 to} 5 × 10 ¹⁵ cm ⁻² . Further, a fourth oxide film is formed on the n-epitaxial layer 3, a diffusion window is opened in the fourth oxide film using a photolithography technique, a diffusion mask is formed for an n ⁺ drain extraction region, and phosphorus ions ( P ⁺ ) or the like, for example, by accelerating energy: about 100 Ke.
V to 2 MeV, dose amount: about 5 × 10 ^{15 to} 5 × 10
Ion implantation at ¹⁶ cm ^-2 . Then, the substrate temperature is about 1100
Heat treatment (drive-in) is performed at a temperature of 1 to 1200 ° C. for a predetermined diffusion time. The diffusion time is set such that the p-well and the n ⁺ drain lead region are diffused halfway in the n epitaxial layer 3 in consideration of the thickness of the n epitaxial layer 3 and the rise of phosphorus (P) in the n ⁺ partial buried layer. Should be determined. At this time, if a p-type impurity such as boron ion (B ⁺ ) is selectively introduced into a position surrounding the n ⁺ buried layer 17, the p-type impurity also rises from below by this heat treatment (drive-in), Further, P implanted immediately below the n ⁺ drain extraction region also rises. Note that n
If the epitaxial layer 3 is thin, the heat treatment at this point can be omitted.

(C) Further, a fifth oxide film is formed on the n-epitaxial layer 3, and a diffusion window is opened in the fourth oxide film by using a photolithography technique.
A p-type impurity for forming the base region 4 is introduced.
For example, boron ions (B ⁺ ) as p-type impurities are accelerated at an energy of about 30 to 100 KeV and a dose of about 2
Ion implantation is performed under the conditions of × 10 ^{13 to} 2 × 10 ¹⁴ cm ⁻² . Then, at a substrate temperature of about 1100 ° C to 1200 ° C,
If heat diffusion (drive-in) is performed for a predetermined time, FIG.
As shown in (c), a p base region having a depth of about 1 μm to 20 μm is formed. In FIG. 11C, the illustration of the p well and the n ⁺ drain lead region is omitted. The temperature during heat diffusion (drive-in) is 1200 ° C
The diffusion coefficient at this temperature is as follows: phosphorus (P) is about 5 × 10 ⁻¹² cm ² · s ⁻¹ , and Sb (Sb) is about 5 ×
It is about one digit different from 10 ^-13 cm ² · s ^-1 . Therefore, FIG.
As shown in FIG. 2C, the phosphorus (P) selectively ion-implanted into the n ⁺ partial buried layer 23 is directed upward to the n-type epitaxial layer 3 side from the semiconductor substrate 1 side, and has a convex shape. And reaches the p base region 4.
As described above, since phosphorus ions (P ⁺ ) are simultaneously ion-implanted also into the portion immediately below the n ⁺ drain extraction region 8, the ion-implanted phosphorus (P) is also increased on the n epitaxial layer 3 side. Diffuses upward with a convex shape. On the other hand, on the surface of n epitaxial layer 3, p
Phosphorus ions (P
⁺ ) Is simultaneously diffused toward the substrate 1 at the time of p-base drive-in, so that it is connected to a diffusion region rising from the buried layer side, and an n ⁺ drain extraction region (not shown) is formed. Similarly, the p-type impurity such as boron (B) introduced into the position surrounding the n ⁺ buried layer 17 also rises, is introduced from the surface side into the position surrounding the n ⁺ buried layer 17, and is pushed in the depth direction. A p-well region (not shown) is formed by combining with a p-type impurity such as boron (B).

(D) The third to fifth oxide films are removed, and a sixth oxide film is formed on the entire surface of the n epitaxial layer 3 on which the p base region 4 has been formed. Then, using a photolithography technique, a diffusion window is opened in the sixth oxide film, and an n-type impurity for forming n ⁺ source region 5 is introduced from the diffusion window. As shown in FIG. 11D, since the n ⁺ source region 5 is formed in a very shallow region,
Arsenic ion (As ⁺ ) with a small diffusion coefficient as a type impurity
Is implanted under the conditions of an acceleration energy of about 30 to 80 KeV and a dose of about 1 × 10 ^{15 to} 4 × 10 ¹⁶ cm ⁻² , and thermal diffusion is performed at a substrate temperature of about 800 ° C. to 1000 ° C. for a predetermined time. .

(E) The sixth oxide film is removed, and a seventh oxide film (cover film) 21 is formed on the entire surface on the n-type epitaxial layer 3. Using a photolithography technique, the cover film 21 is patterned in a grid pattern like the pattern of the U-shaped gate electrode 7 shown in FIG. The patterning of the cover film 21 may be performed by RIE using a photoresist as a mask. Then, the photoresist used for patterning the cover film 21 is removed, and anisotropic etching of silicon is performed using the cover film 21 as a mask. As a result, FIG.
As shown in (e), a trench 20 is formed between two adjacent p base regions. As shown in FIG. 12E, the etching depth is controlled so that the depth of the trench 20 is slightly smaller than the diffusion depth of the p base region 4. Thus, the bottom corner of trench 20 is covered with p base region 4, and n ⁺ partial buried layer 24 is exposed at the center of the bottom. Note that the n ⁺ source region 5 is separated and exposed above the sidewall of each trench 20.

(F) After performing a predetermined process for cleaning the surface of the n ⁺ partial buried layer 24 exposed at the side wall portion and the bottom central portion of the trench 20, the gate is oxidized, and FIG.
U having a thickness of 30 nm to 150 nm as shown in FIG.
A mold gate insulating film 6 is formed. The gate oxidation may be dry oxidation or wet oxidation, or may be performed by mixing HCl. In FIG. 12F, the cover film 21 and the U-type gate insulating film 6 are shown as a continuous oxide film. Thereafter, as shown in FIG.
By embedding n ⁺ doped polysilicon in U,
A mold gate electrode 7 is formed. Then, as shown in FIG. 13H, the n ⁺ -doped polysilicon is etched back to bury a gate electrode conductive material inside the trench 20. The n ⁺ -doped polysilicon may be embedded in the trench 20 by planarization by CMP. Thereafter, the cover film 21 is etched using a predetermined oxide film etchant.
Is removed. As a result, n ⁺ -doped polysilicon projects above trench 20. Therefore, if the n ⁺ doped polysilicon is oxidized, as shown in FIG.
A cap oxide film 22 is formed on the mold gate electrode 7.

(G) In the subsequent steps after the step of forming the first interlayer insulating film, various conventionally known methods can be adopted, and the description thereof is the same as that of the first embodiment. The description is omitted. Through the above manufacturing steps, the lateral UMOSFET according to the second embodiment of the present invention is completed.

(Third Embodiment) FIG. 14 is a sectional structural view of a vertical UMOSFET according to a third embodiment of the present invention.

As shown in FIG. 14, a vertical UMOSFET according to a third embodiment of the present invention has a first conductivity type (n
Semiconductor region 31, a second conductivity type (p-type) base region (p-base region) 4 disposed inside the semiconductor region 31, and formed shallower than the deepest portion in the p-base region 4. Groove, a first conductive type (n-type) first main electrode region (n ⁺ source region) 5 disposed on the surface of p base region 4, and a first main electrode region 5 disposed below p base region 4. Conductive (n-type) second main electrode region (n ⁺ drain region) 8
And a gate insulating film 6 formed on the side wall of the groove, and a control electrode 7 buried inside the groove. In FIG. 14, a semiconductor region 31 is formed on a semiconductor substrate (n ⁺ substrate) 8 of a first conductivity type (n type) 8.
Although shown as the epitaxial layer 31, a thickness of 300 μm is required to realize a vertical UMOSFET having a high withstand voltage.
The n-substrate of 1 mm to 1 mm may be used as the semiconductor region 31, and the second main electrode region (n ⁺ drain region) 8 may be formed as a diffusion layer on the back surface of the n-substrate 31. In the n ⁺ source region 5,
A first main electrode (source electrode) 9 is connected to the n ⁺ drain region 8, and a second main electrode (drain electrode) 10 is connected to the n ⁺ drain region 8.
Source electrode 9 is arranged such that n ⁺ source region 5 and p base region 4 are short-circuited. As shown in FIG. 14, in the vertical UMOSFET according to the third embodiment of the present invention, the bottom corner of the U-type gate insulating film 6 is covered with the p base region 4, and the U-type gate insulating film The center of the bottom of 6 is in contact with n-well region 3.

A vertical U according to the third embodiment of the present invention
In MOSFET, the potential of the n ⁺ drain region 8 side while applying a voltage higher than the n ⁺ source region 5, to n ⁺ source region 5, when a positive voltage is applied to the U-shaped gate electrode 7, The surface of p base region 4 in contact with U-type gate electrode 7 is inverted to n-type, and a channel is formed near U-type gate insulating film 6 in the vertical direction. As a result, electrons are injected into the n epitaxial layer 31 from the lower end of the p base region 4 through the channel vertically from the n ⁺ source region 5.
The injected electrons pass through the n epitaxial layer 31,
The n ⁺ drain region 8 is reached. Therefore, the n epitaxial layer 31 functions as a drift layer for carriers. In the device cutoff state where a negative or zero voltage is applied to the U-type gate electrode 7 with respect to the n ⁺ source region 5, p
At the junction interface between the base region 4 and the n-type epitaxial layer 31, a depletion layer extends. In the vertical UMOSFET according to the third embodiment of the present invention, the bottom corner of the U-type gate insulating film 6 is covered with the p base region 4, and the interface potential is lower than the voltage value of the p base region 4. Will be kept. Therefore, even when a high voltage is applied in the device cutoff state, the electric field concentration on the bottom corner of the U-type gate insulating film 6 can be reduced, and the U-type gate insulation against abnormal high voltage and surge voltage can be achieved. Destruction of the film 6 can be effectively prevented.

Next, a method of manufacturing the vertical UMOSFET according to the third embodiment of the present invention shown in FIG. 14 will be described with reference to FIG.

(A) First, an n ⁺ substrate 25 having an impurity density of about 1 × 10 ¹⁸ cm ^{−3 to} 1 × 10 ²¹ cm ⁻³ is prepared. As shown in FIG. 15A, an impurity density of 1 × 10 ¹² cm ^{-3 to} 8 is formed on the n ⁺ substrate 25 by vapor phase epitaxial growth.
N of about 10 ¹⁵ cm ^-3 and a thickness of 10 μm to 100 μm
The epitaxial layer 31 is grown. Alternatively, in order to realize a vertical UMOSFET having a high withstand voltage, an impurity density of about 6 × 10 ¹¹ cm ^{−3 to} 8 × 10 ¹⁹ cm ⁻³ and a thickness of 300 μm are used.
No m prepared n substrate 1 mm, on the rear surface of the n-type substrate 31, the impurity density of 1 × 10 ¹⁸ cm ^-3 to 8 × 10 ²⁰ cm ^-3 or so, a second main electrode region of the depth of 5μm to 30 [mu] m (n ⁺ (Drain region).

(B) Then, a first oxide film is formed on the n-epitaxial layer 31, and a diffusion window is opened in the first oxide film by using a photolithography technique. A p-type impurity for forming is introduced. Because of the vertical structure, unlike the first and second embodiments, an n-type impurity introduction step is not required for the n ⁺ drain lead-out region 8. Thereafter, when thermal diffusion (drive-in) is performed at a predetermined substrate temperature and a predetermined diffusion time, a p-base region having a predetermined depth, for example, a depth of 1 μm to 15 μm is formed.

(C) The first oxide film is removed, and a second oxide film is formed on the entire surface of the n epitaxial layer 31 on which the p base region 4 has been formed. Then, a diffusion window is opened in the second oxide film using a photolithography technique, and an n-type impurity for forming n ⁺ source region 5 is introduced from the diffusion window. Further, thermal diffusion is performed at a predetermined substrate temperature for a predetermined time. After that, similarly to the first and second embodiments,
The second oxide film is removed, and a third oxide film (cover film) is formed on the entire surface on the n-type epitaxial layer 31. Using a photolithography technique, the cover film is patterned in a grid pattern like the pattern of a U-shaped gate electrode, and silicon is anisotropically etched using the cover film as a mask to form a trench. Controlling the etching depth so that the depth of the trench is slightly shallower than the diffusion depth of the p base region is the same as in the first and second embodiments. Next, a U-type gate insulating film is formed on the side wall of the trench, and further, n ⁺ -doped polysilicon as a conductive material for a gate electrode is embedded in the trench. Thereafter, the cover film is removed using a predetermined oxide film etchant, and n ⁺ -doped polysilicon projects above the trench.
Therefore, the n ⁺ -doped polysilicon is oxidized to form a cap oxide film on the U-type gate electrode in a self-aligned manner.

(D) Thereafter, as shown in FIG. 15B, the n-type epitaxial layer 31 including the cap oxide film is formed.
A first-layer interlayer insulating film 11 is formed thereon by a CVD method or the like. Then, using photolithography technology, the first
A source contact hole is opened in the interlayer insulating film 11. At this time, the cap oxide film 2 is formed on the U-type gate electrode 7.
2 is formed, a photoresist window is formed in a wide area including a plurality of source cells, and the first interlayer insulating film 1 is formed.
If 1 is etched, a source contact hole can be opened only in the upper part of the source cell in a self-aligned manner. After opening source contact hole, sputtering method or EB
A conductive material such as an Al alloy is deposited by a vacuum evaporation method such as evaporation, and further, photolithography technology and RIE
Thus, the source electrode 9 is patterned. Finally,
If a multilayer metal film such as chromium (Cr) nickel (Ni) silver (Ag) is deposited on the back surface of the n ⁺ substrate 25 by a sputtering method or a vacuum evaporation method and heat treatment (sintering) is performed, the drain electrode 10 is formed. The vertical UMOSFET according to the third embodiment of the present invention is completed. The drain electrode 10 may be a Mo plate or a W plate formed on the back surface of the n ⁺ substrate 25 by an alloy reaction.

In FIG. 15A, an impurity density of 1 × 10 ¹⁸ cm ^{−3 to} 1 × 10 ²¹ cm ^{−3 using} antimony (Sb) as a dopant is used as an n-type impurity having a small diffusion coefficient.
By preparing about n ⁺ substrate 25 and selectively introducing an n-type impurity having a large diffusion coefficient such as phosphorus (P) onto n ⁺ substrate 25, substantially the same as in the second embodiment, It is possible to form a second main electrode region including a main region having a flat main surface and a convex partial region extending from the main region to the bottom of the groove. That is, the phosphorus ion (P ⁺ ) is accelerated at an energy of about 30 to 130 KeV and a dose is:
Ion implantation is performed under the condition of about 3 × 10 ^{15 to} 5 × 10 ¹⁶ cm ⁻² , and thermal diffusion is performed at a substrate temperature of about 1000 ° C. to 1200 ° C. for a predetermined time to form an n ⁺ partially buried layer.
If the epitaxial layer 31 is grown, in a subsequent heat treatment step, a vertical UMOSF having an upwardly convex partial region is formed.
ET can be formed.

As a result, electrons injected from the p base region 4 of the vertical UMOSFET into the n epitaxial layer (n drift layer) 31 are n ^{+ having} a low potential with respect to the electrons.
It flows into the partially buried layer. Alternatively, if the n ⁺ partial buried layer is in contact with U-type gate insulating film 6, electrons are directly injected from p base region 4 to the n ⁺ partial buried layer.
Since the n ⁺ partial buried layer has an upwardly convex shape, the injected electrons or the inflowing electrons reach the low-resistivity second main electrode region 8 at a wide angle.
The on-resistance of T is dramatically reduced.

(Fourth Embodiment) FIG. 16 is a sectional structural view of a vertical IGBT according to a fourth embodiment of the present invention.

As shown in FIG. 16, the vertical IGBT according to the fourth embodiment of the present invention has a semiconductor region 31 of the first conductivity type (n-type) and a semiconductor region 31 disposed inside the semiconductor region 31. 2 conductivity type (p type) base region (p base region) 4
A trench formed shallower than the deepest portion in p base region 4, and a first conductive type (n-type) first main electrode region (n ⁺ emitter region) disposed on the surface of p base region 4 26
And a second conductivity type (p
A second main electrode region (p ⁺ collector region) 27 of the mold), a gate insulating film 6 formed on the side wall of the groove, has at least a control electrode 7 buried in the groove. In FIG. 16, the semiconductor region 31 has the second conductivity type (p
) Is shown as an n-type epitaxial layer 31 formed on a semiconductor substrate (p ⁺ substrate) 8 of a semiconductor substrate (p ⁺ substrate) 8. Region 31 and n substrate 31
A second main electrode region (p ⁺ collector region) 27 may be formed as a diffusion layer on the back surface of the semiconductor device. A first main electrode (emitter electrode) 28 is connected to the n ⁺ emitter region 26, and a second main electrode (collector electrode) 29 is connected to the p ⁺ collector region 27. The emitter electrode 28 is connected to the n ⁺ emitter region 26
And p base region 4 are short-circuited. As shown in FIG. 16, the vertical type I according to the third embodiment of the present invention
In the GBT, the bottom corner of the U-type gate insulating film 6 is covered with the p base region 4, and the center of the bottom of the U-type gate insulating film 6 is in contact with the n-epitaxial layer 31 functioning as a drift layer. .

Next, the operation of the vertical IGBT according to the fourth embodiment of the present invention will be described. When a positive voltage is applied to the n ⁺ emitter region 26 while a forward bias voltage is applied between the n ⁺ emitter region 26 and the p ⁺ collector region 27, the U The surface of p base region 4 in contact with gate electrode 7 is inverted to n type, and a channel is formed in the vertical direction near U type gate insulating film 6. As a result, electrons are injected from the lower end of p base region 4 into n drift layer (n epitaxial layer) 31. The injected electrons are converted into the n epitaxial layer 31 and the p ⁺
The potential is accumulated between the potential valleys near the interface with the collector region 27, and the potential barrier against holes in the p ⁺ collector region 27 decreases. As a result, p ⁺ collector region 27
Then, holes are injected into the n-type epitaxial layer 31, and a forward bias is applied between the n-type epitaxial layer 31 as a drift layer and the p ⁺ collector region 27. The injected holes further promote the injection of electrons from n ⁺ emitter region 26. Thus, the n-type epitaxial layer 31, which is a high resistivity region, has a large number of two types of carriers, electrons and holes, and the charge density increases. That is, by increasing the electron density and the hole density equally, conductivity modulation occurs in which the substantial resistance of the high resistivity region is reduced by orders of magnitude.

[0091] For the n ⁺ emitter region 26, Fumata in the device blocking state of applying a voltage of zero U-shaped gate electrode 7, the reverse bias of the high voltage applied between the n ⁺ emitter region 26 and p ⁺ collector region 27 A depletion layer extends at the junction between p base region 4 and n epitaxial layer 31. The bottom corner of the U-type gate insulating film 6 is protected from a direct high voltage by a depletion layer, and the interface potential is maintained at the voltage value of the p base region 4. Therefore,
Even when an abnormally high voltage or surge voltage is applied between the emitter and the collector, the electric field concentration on the bottom corner of the U-type gate insulating film 6 can be reduced. Therefore, it is possible to prevent the gate insulating film from being broken by an abnormally high voltage or a surge voltage.

Next, the method of manufacturing the vertical IGBT according to the fourth embodiment of the present invention differs from the method of manufacturing the vertical UMOSFET of the third embodiment only in the initial substrate. That is, instead of providing the n ⁺ substrate 25, the impurity density of 1 × 10 ¹⁸ cm ^- may be prepared from ³ to 6 × 10 ¹⁹ cm ^-3 of about p ⁺ substrate 27. The manufacturing method thereafter is substantially the same as the vertical UMOSFET according to the third embodiment.
Is basically the same as the manufacturing method. However, since there is conductivity modulation due to injection of holes from the collector side, the thickness of the n epitaxial layer (n drift layer) 31 is
Even if the thickness is larger than that of the MOSFET, the on-resistance can be maintained at a relatively low value. Therefore, the impurity density is 6 × 10
An n substrate having a thickness of 300 μm to 1 mm having a thickness of about ¹¹ cm ^{−3 to} 8 × 10 ¹⁹ cm ⁻³ is prepared, and an impurity density of 1 × 10 ¹⁸ cm ^{−3 to} 8 × 10 ¹⁹ cm ⁻³ is provided on the back surface of the n substrate 31. Degree, depth 5μ
2 to 50 μm second main electrode region (p ⁺ collector region)
27 can provide a semiconductor power device with higher withstand voltage and lower on-resistance. Further, an n buffer layer is provided between the n epitaxial layer (n drift layer) 31 and the p ⁺ collector region 27, or a p ⁺ collector region is divided into a plurality of portions, and an n ⁺ short region is provided therebetween. A short structure may be adopted.

(Other Embodiments) As described above, the present invention has been described with reference to the first to fourth embodiments.
The discussion and drawings that form part of this disclosure should not be understood as limiting the invention. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

For example, in the fourth embodiment of the present invention, a vertical IGBT has been described.
A horizontal IGBT can be obtained by forming a p ⁺ buried collector layer, further providing a p ⁺ collector extraction region, and forming a collector electrode on the same surface side as the emitter electrode side.

In the first to third embodiments of the present invention, a description has been given of a UMOSFET. If you can control, UM
OSSIT. The potential barrier of UMOSSIT is a saddle point (saddle point) in a two-dimensional space defined by a gate potential and a drain potential, and its height can be controlled by the gate potential and the drain potential. Therefore, U
MOSSIT has a drain current-drain voltage characteristic of 3
It grows exponentially, similar to a polar vacuum tube.

In the first to third embodiments of the present invention, the UMOSFET has been described, but the gate insulating film is not limited to the silicon oxide film (SiO ₂ ). Silicon nitride film (Si ₃ N ₄ film), Si ₃ N ₄
Of course, various insulating films such as a composite film of a film and a SiO ₂ film or a ferroelectric film such as a BSTO film can be used.

[0097] Further, in the first and second embodiments of the present invention, n ⁺ drain lead-out region 8 has been illustrated structure formed from the impurity diffusion region, n ⁺
A trench may be formed in a portion where the drain extraction region 8 is to be formed, and a highly conductive material may be embedded in the trench. Examples of the highly conductive material include a low-resistance polysilicon (doped polysilicon), a high melting point metal such as W, Ti, and Mo;
These silicides (WSi ₂ , TiSi ₂ , MoS
i ₂ ), etc., or polycide using these silicides can be used. With these highly conductive materials, the n ⁺ buried layer 17 and the drain electrode can be conducted. As a result, the resistance of the n ⁺ drain extraction region 8 can be reduced, and the on-resistance of the element can be reduced. In addition, since the impurity diffusion region always accompanies the lateral diffusion, it occupies a wide diffusion region and the area efficiency is low. On the other hand, the n ⁺ drain extraction region 8 formed by the trench reduces the occupied area. It is possible to increase the integration density of the element and to reduce the chip size.

The n ⁺ buried layer 17 is made of W, Ti, Mo.
High melting point metals such as silicides (WSi ₂ , Ti
Si ₂ , MoSi ₂ ) or the like may be used. This gives n
The resistance of the current path when carriers flow from the ⁺ source region 5 to the n ⁺ drain extraction region 8 can be reduced, and the on-resistance can be reduced. In the case of an individual semiconductor element (discrete device), the second main electrode region (embedded region) 2
Need not necessarily be formed as a local region as in the first and second embodiments, but may be formed over the entire surface of the semiconductor substrate 1. In this case, the first
The semiconductor region 3 of the conductivity type is a semiconductor region 30 of the second conductivity type.
And need not be present as a locally formed well 3, and may be formed over the entire surface via a buried region (second main electrode region) 2. In addition, the first and second
In the embodiment, the structure of the so-called “pn junction isolation” in which the semiconductor region 3 of the first conductivity type is surrounded by the semiconductor region 30 of the second conductivity type and separated from other elements and circuits has been described. The element isolation may be “dielectric isolation”. In this case, for example, a second main electrode region (buried region) of the first conductivity type is locally formed on the semiconductor substrate of the second conductivity type, and a semiconductor region of the first conductivity type is epitaxially grown thereon. Then, a trench reaching the semiconductor substrate after the epitaxial growth may be formed in the semiconductor region of the first conductivity type so as to surround the second main electrode region, and a dielectric may be embedded in the trench. As the dielectric to be embedded in the trench, it is possible to use, for example, semi-insulating polysilicon (SIPOS) to which oxygen is added, in addition to an insulating film such as an oxide film. Further, an SOS structure in which the second main electrode region is formed on the sapphire substrate instead of the semiconductor substrate, or an SIS structure in which the second main electrode region is formed on the semiconductor substrate via the buried insulating film may be employed.

In the first to fourth embodiments, an n-channel insulated gate semiconductor device has been described. However, if the conductivity type and the polarity are all reversed, the present invention can be applied to a p-channel insulated gate semiconductor device. It will be easy to understand.

In the first to fourth embodiments, silicon has been described as a semiconductor material. However, other semiconductor materials such as silicon carbide (SiC) and gallium arsenide (GaAs) can be used. AlGaAs inside the U-groove
In a structure similar to a HEMT using a heterojunction such as / GaAs, a thin semiconductor (AlGaAs) having a wide band gap is used.
The layer s) has a function similar to that of the gate insulating film described in the first to fourth embodiments, and such a structure can be understood as an insulated gate transistor in a broad sense. Therefore, it should be noted that the present invention includes a semiconductor device having such a HEMT or a HEMT-like heterojunction gate structure. In this case, G
A trench is formed shallower than the p base region of aAs, and a GaAs channel layer and AlGaAs are formed in the trench.
A structure in which a thin-film semiconductor layer is formed and a gate electrode is formed on the thin-film semiconductor layer is applicable.

Further, the present invention is suitable for a power semiconductor device having a high voltage of 600 V or more, further, 1 KV to 4.5 KV, but is not necessarily limited to a power semiconductor device. For example, the structure of the present invention can be applied to a small signal element such as a logic integrated circuit.

As described above, the present invention naturally includes various embodiments and the like not described herein. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the claims that are appropriate from the above description.

[Brief description of the drawings]

FIG. 1 shows a horizontal UMO according to a first embodiment of the present invention.
It is sectional drawing of the basic structure of SFET.

FIG. 2 is an enlarged view of a cross section of the lateral UMOSFET shown in FIG.

FIG. 3 is a plan view of a basic structure of a lateral UMOSFET corresponding to FIGS. 1 and 2;

FIG. 4 is a horizontal UMO according to the first embodiment of the present invention.
FIG. 9 is a process cross-sectional view for describing the method for manufacturing the SFET. (Part 1)

FIG. 5 is a horizontal UMO according to the first embodiment of the present invention.
FIG. 9 is a process cross-sectional view for describing the method for manufacturing the SFET. (Part 2)

FIG. 6 is a horizontal UMO according to the first embodiment of the present invention.
FIG. 9 is a process cross-sectional view for describing the method for manufacturing the SFET. (Part 3)

FIG. 7 is a horizontal UMO according to the first embodiment of the present invention.
FIG. 9 is a process cross-sectional view for describing the method for manufacturing the SFET. (Part 4)

FIG. 8 shows a horizontal UMO according to a second embodiment of the present invention.
It is sectional drawing of the basic structure of SFET.

FIG. 9 shows a horizontal UMO according to a second embodiment of the present invention.
It is a top view of the basic structure of SFET.

FIG. 10 shows a horizontal UM according to a second embodiment of the present invention.
FIG. 9 is a process cross-sectional view for describing the method for manufacturing the OSFET. (Part 1)

FIG. 11 shows a horizontal UM according to a second embodiment of the present invention.
FIG. 9 is a process cross-sectional view for describing the method for manufacturing the OSFET. (Part 2)

FIG. 12 shows a horizontal UM according to a second embodiment of the present invention.
FIG. 9 is a process cross-sectional view for describing the method for manufacturing the OSFET. (Part 3)

FIG. 13 is a horizontal UM according to a second embodiment of the present invention.
FIG. 9 is a process cross-sectional view for describing the method for manufacturing the OSFET. (Part 4)

FIG. 14 is a vertical UM according to a third embodiment of the present invention.
It is sectional drawing of the basic structure of OSFET.

FIG. 15 is a vertical UM according to a third embodiment of the present invention.
FIG. 9 is a process cross-sectional view for describing the method for manufacturing the OSFET.

FIG. 16 is a vertical IG according to a fourth embodiment of the present invention.
It is sectional drawing of the basic structure of BT.

FIG. 17 is a sectional view of a basic structure of a conventional lateral UMOSFET.

FIG. 18 is a plan view of a basic structure of a conventional lateral UMOSFET.

[Explanation of symbols]

Reference Signs List 1 p substrate 2 buried layer 3 n-well region 4 p base region 5 first main electrode region (n ⁺ source region) 6 U-shaped gate insulating film 7 U-shaped control electrode (U-shaped gate electrode) 8 second main electrode lead-out region (N ⁺ drain extraction region) 9 first main electrode (source electrode) 10 second main electrode (drain electrode) 11 first layer interlayer insulating film 12 second layer interlayer insulating film 13 second layer second main electrode (second Layer drain electrode) 15 second main electrode cell (drain cell) 16 first main electrode cell (source cell) 17 n ⁺ buried layer 20 trench 21 cover film 22 cap oxide film 23 n ⁺ partial buried layer (before thermal diffusion) 24 n ⁺ partial buried layer (after thermal diffusion) 25 n ⁺ substrate 26 first main electrode region (n ⁺ emitter region) 27 second main electrode region (p ⁺ collector region) 28 first main electrode (emitter electrode) 29 Second main electrode (collector electrode) 30 p epitaxial layer 31 n epitaxial layer

Claims (8)

[Claims] A first conductive type semiconductor region; a second conductive type base region disposed inside the semiconductor region; a trench formed shallower than a deepest portion in the base region; A first main electrode region of a first conductivity type disposed on a surface of the region, a second main electrode region disposed below the base region, a gate insulating film formed on a side wall of the groove, and the groove And a control electrode embedded inside the semiconductor device. 2. The method according to claim 1, wherein the second main electrode region includes a main region having a substantially flat main surface, and a convex partial region extending from the main region to the bottom of the groove. The semiconductor device according to claim 1, wherein: 3. The semiconductor according to claim 1, further comprising a lead-out region of the same conductivity type as the second main electrode region, which extends from the surface of the semiconductor region to the second main electrode region. apparatus. 4. The semiconductor device according to claim 1, wherein said second main electrode region is of a first conductivity type. 5. The semiconductor device according to claim 1, wherein said second main electrode region is of a second conductivity type. 6. A semiconductor region of a first conductivity type; a base region of a second conductivity type disposed inside the semiconductor region; a trench formed shallower than a deepest portion in the base region; A first main electrode region of a first conductivity type disposed on a surface of the region; a second main electrode region disposed below the base region; and the semiconductor region and the base formed on sidewalls of the groove. A semiconductor device comprising at least a thin-film semiconductor layer having a wider forbidden band than a region, and a control electrode embedded in the trench. 7. A step of forming a first conductivity type semiconductor region, a step of forming a second conductivity type base region inside the semiconductor region, and a first conductivity type first region on a surface of the base region. Forming a main electrode region; forming a groove shallower than the deepest portion in the base region; forming a gate insulating film on a side wall of the groove; and embedding a control electrode inside the groove. Wherein the semiconductor region is formed above the second main electrode region. 8. The second main electrode region has a main region having a substantially flat main surface, and has a diffusion coefficient larger than a diffusion coefficient of an impurity determining a conductivity type of the main region. 8. The method according to claim 7, further comprising the step of selectively introducing an impurity into the main region to form a partial region.