CN115084247A - Manufacturing method of double-groove type silicon carbide MOSFET - Google Patents
Manufacturing method of double-groove type silicon carbide MOSFET Download PDFInfo
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- CN115084247A CN115084247A CN202211002970.6A CN202211002970A CN115084247A CN 115084247 A CN115084247 A CN 115084247A CN 202211002970 A CN202211002970 A CN 202211002970A CN 115084247 A CN115084247 A CN 115084247A
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 35
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 125
- 230000004888 barrier function Effects 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- 230000008569 process Effects 0.000 abstract description 9
- 238000009826 distribution Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000002407 reforming Methods 0.000 abstract 2
- 230000005669 field effect Effects 0.000 abstract 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000000463 material Substances 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Abstract
The invention provides a manufacturing method of a double-groove type silicon carbide MOSFET (metal oxide semiconductor field effect transistor). A barrier layer is formed on a drift layer of a silicon carbide substrate, a through hole is formed by etching the barrier layer, and ion implantation is carried out on the drift layer through the through hole to form an interlayer; reforming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and etching the drift layer through the through hole to form a groove region; oxidizing the groove region to form a first insulating layer and a second insulating layer; depositing polycrystalline silicon to form a first polycrystalline silicon layer and a second polycrystalline silicon layer; reforming the barrier layer, etching, and performing ion implantation to form a first source region, a second source region, a third source region, a fourth source region and a polysilicon gate; forming a barrier layer again, etching and depositing metal to form a source metal layer; removing the barrier layer, and depositing metal on the silicon carbide substrate to form a drain metal layer; the process is simple, the internal current distribution is more uniform, the heat concentration is avoided, and the reliability of the device is improved.
Description
Technical Field
The invention relates to a manufacturing method of a double-groove type silicon carbide MOSFET.
Background
Silicon carbide (SiC) materials for SiC devices have received much attention and research due to their excellent physical properties. The high-temperature high-power electronic device has the advantages of high input impedance, high switching speed, high working frequency, high temperature and high pressure resistance and the like, and is widely applied to the aspects of switching regulated power supplies, high-frequency heating, automobile electronics, power amplifiers and the like.
However, due to the excellent material properties of SiC, the current density of the device is higher and higher, which puts new demands on the heat distribution inside the device, which requires more uniform distribution of current channels, less heat concentration and faster heat dissipation in the device. Meanwhile, because SiC is a compound semiconductor material, the process characteristics of the SiC are difficult to control, the device needs to be controlled as far as possible while the gate oxide and gate control capability are solved, the structure is simple, the process is simple, the mechanism of the device is easy to analyze, and the manufacturing reliability is higher.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a manufacturing method of a double-groove type silicon carbide MOSFET, which has a simple process, enables internal current distribution to be more uniform, avoids heat concentration and improves device reliability.
The invention is realized by the following steps: a manufacturing method of a double-groove type silicon carbide MOSFET specifically comprises the following steps:
and 7, removing the barrier layer, and depositing metal on the silicon carbide substrate to form a drain metal layer.
Further, the pinch-off layer in step 1 includes a first pinch-off region, a second pinch-off region, and a third pinch-off region.
The invention has the advantages that:
the MOSFET adopts a self-alignment process, and adopts one-time ion implantation for manufacturing a polysilicon gate and all source regions of the MOSFET, so that the process steps are reduced; the two groove type grids are arranged, so that the current inside the MOSFET is distributed more uniformly, heat concentration is avoided, and the reliability of the device is improved; the corner layer of the grid is wrapped by the pinch-off layer of the MOSFET, so that the problem of electric field concentration at the corner of the grid is solved, other insulating layers are not additionally arranged, and the process steps are saved.
Drawings
The invention will be further described with reference to the following examples with reference to the accompanying drawings.
FIG. 1 is a first flowchart of a method for fabricating a double trench silicon carbide MOSFET in accordance with the present invention.
FIG. 2 is a flow chart of a method of fabricating a double trench silicon carbide MOSFET according to the present invention.
Fig. 3 is a flow chart of a method for manufacturing a double-trench silicon carbide MOSFET according to the present invention.
Fig. 4 is a flow chart of a method of manufacturing a double-trench silicon carbide MOSFET according to the present invention.
Fig. 5 is a flow chart of a method for manufacturing a double trench silicon carbide MOSFET of the present invention.
Fig. 6 is a flow chart of a method of manufacturing a double trench silicon carbide MOSFET according to a sixth aspect of the present invention.
Fig. 7 is a flow chart of a method for manufacturing a double-trench silicon carbide MOSFET according to the present invention.
Fig. 8 is a schematic diagram of a dual trench silicon carbide MOSFET of the present invention.
Detailed Description
Referring to fig. 1 to 8, a method for manufacturing a dual trench silicon carbide MOSFET according to the present invention includes the following steps:
and 7, removing the barrier layer a, and depositing metal on the silicon carbide substrate 1 to form a drain metal layer 8.
According to the overall manufacturing process of the MOSFET, the integration process and the self-alignment process of the first insulating layer 4, the second insulating layer 5 and the pinch-off layer 3 reduce two times of ion implantation, and the cost of the MOSFET is controlled; the device has simple internal partition, and better control on the uncertainty of mechanism analysis and process control of the device.
As shown in fig. 8, the MOSFET obtained by the above manufacturing method includes:
a silicon carbide substrate 1 having a silicon carbide layer,
the drift layer 2 is arranged on the upper side surface of the silicon carbide substrate 1, and a first protruding part 21 and a second protruding part 22 are arranged on the drift layer 2;
the interlayer fault 3 is arranged on the drift layer 2, and a first source region 31, a second source region 32, a third source region 33 and a fourth source region 34 are arranged on the interlayer fault 3;
a first insulating layer 4, wherein the first insulating layer 4 is arranged on the interlayer 3, the bottom of the first insulating layer 4 is connected to the first protruding portion 21, the side surface of the first insulating layer 4 is connected with the interlayer 3, the first source region 31 and the second source region 32, and a first polysilicon layer 41 is arranged in the first insulating layer 4;
the second insulating layer 5 is arranged on the interlayer fault 3, the bottom of the second insulating layer 5 is connected to the second protruding portion 22, the side face of the second insulating layer 5 is connected with the interlayer fault 3, the third source region 33 and the fourth source region 34, and a second polycrystalline silicon layer 51 is arranged in the second insulating layer 5;
a source metal layer 6, the source metal layer 6 being connected to the first source region 31, the second source region 32, the third source region 33, and the fourth source region 34;
a polysilicon gate 7, wherein the polysilicon gate 7 is respectively connected with the first polysilicon layer 41 and the second polysilicon layer 51;
and a drain metal layer 8, wherein the drain metal layer 8 is provided on the lower side surface of the silicon carbide substrate 1.
In another preferred embodiment, the pinch-off layer 3 includes a first pinch-off region 35, a second pinch-off region 36 and a third pinch-off region 37, the first pinch-off region 35 is disposed on the drift layer 2 and located on the left side of the first protrusion 21, and the first pinch-off region 35 is provided with a first source region 31; the second pinch-off region 36 is disposed on the drift layer 2 and between the first protruding portion 21 and the second protruding portion 22, and a second source region 32 and a third source region 33 are disposed on the second pinch-off region 36; the third pinch-off region 37 is disposed on the drift layer 2 and located on the right side of the second protruding portion 22, and a fourth source region 34 is disposed on the third pinch-off region 37;
the bottom of the first insulating layer 4 is connected to the first pinch-off region 35, the first protruding portion 21 and the second pinch-off region 36, the left side of the first insulating layer 4 is connected to the first pinch-off region 35 and the first source region 31, and the right side of the first insulating layer 4 is connected to the second pinch-off region 36 and the second source region 32;
the bottom of the second insulating layer 5 is connected to the second pinch-off region 36, the second protrusion 32 and the third pinch-off region 37, the left side of the second insulating layer 5 is connected to the second pinch-off region 36 and the third source region 33, and the right side of the second insulating layer 5 is connected to the third pinch-off region 37 and the fourth source region 34.
The double-groove SiC MOSFET adopting the self-alignment process is provided with two groove type gates, so that the current inside the MOSFET is distributed more uniformly, heat concentration is avoided, and the reliability of the device is improved; the pinch-off layer of the SiC MOSFET wraps the corners of the first polysilicon layer 41 and the second polysilicon layer 51, so that the problem of electric field concentration at the corners is solved, other insulating layers are not newly added, and the process steps are saved.
Although specific embodiments of the invention have been described above, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the appended claims.
Claims (2)
1. A manufacturing method of a double-groove type silicon carbide MOSFET is characterized by comprising the following steps:
step 1, forming a barrier layer on a drift layer of a silicon carbide substrate, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer through the through hole to form an interlayer fault;
step 2, forming a barrier layer on the drift layer again, etching the barrier layer to form a through hole, and etching the drift layer through the through hole to form a groove region;
step 3, oxidizing the groove area to form a first insulating layer and a second insulating layer;
step 4, depositing polycrystalline silicon in the first insulating layer and the second insulating layer to form a first polycrystalline silicon layer and a second polycrystalline silicon layer;
step 5, forming a barrier layer again, etching the barrier layer to form a through hole, and performing ion implantation through the through hole pair to form a first source region, a second source region, a third source region, a fourth source region and a polysilicon gate;
step 6, forming the barrier layer again, etching the barrier layer to form a through hole, and depositing metal through the through hole to form a source metal layer;
and 7, removing the barrier layer, and depositing metal on the silicon carbide substrate to form a drain metal layer.
2. The method of claim 1, wherein the pinch-off layer in step 1 comprises a first pinch-off region, a second pinch-off region, and a third pinch-off region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211002970.6A CN115084247A (en) | 2022-08-22 | 2022-08-22 | Manufacturing method of double-groove type silicon carbide MOSFET |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211002970.6A CN115084247A (en) | 2022-08-22 | 2022-08-22 | Manufacturing method of double-groove type silicon carbide MOSFET |
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| CN115084247A true CN115084247A (en) | 2022-09-20 |
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| CN202211002970.6A Pending CN115084247A (en) | 2022-08-22 | 2022-08-22 | Manufacturing method of double-groove type silicon carbide MOSFET |
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|---|---|---|---|---|
| JP2000188397A (en) * | 1998-12-22 | 2000-07-04 | Nissan Motor Co Ltd | Semiconductor device and its manufacture |
| EP1052690A2 (en) * | 1999-05-10 | 2000-11-15 | Intersil Corporation | Process or forming MOS-gated devices having self-aligned trenches |
| US20010003367A1 (en) * | 1998-06-12 | 2001-06-14 | Fwu-Iuan Hshieh | Trenched dmos device with low gate charges |
| US6373098B1 (en) * | 1999-05-25 | 2002-04-16 | Fairchild Semiconductor Corporation | Trench-gated device having trench walls formed by selective epitaxial growth and process for forming device |
| US20040232481A1 (en) * | 2003-05-20 | 2004-11-25 | Robert Herrick | Structure and method for forming a trench MOSFET having self-aligned features |
| CN103187291A (en) * | 2011-12-29 | 2013-07-03 | 立新半导体有限公司 | Method of preparing trench semiconductor power discrete device |
| US20160276464A1 (en) * | 2014-07-25 | 2016-09-22 | Su Zhou Oriental Semiconductor Co.,Ltd | Power mos transistor and manufacturing method therefor |
| CN105990434A (en) * | 2014-09-12 | 2016-10-05 | 株式会社东芝 | Semiconductor device and manufacturing method thereof |
| CN106298920A (en) * | 2015-05-29 | 2017-01-04 | 北大方正集团有限公司 | The manufacture method of the field effect transistor in contactless hole and the field effect transistor in contactless hole |
| US20190348524A1 (en) * | 2018-05-09 | 2019-11-14 | Mitsubishi Electric Corporation | Silicon carbide semiconductor device, power converter, and method of manufacturing silicon carbide semiconductor device |
-
2022
- 2022-08-22 CN CN202211002970.6A patent/CN115084247A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010003367A1 (en) * | 1998-06-12 | 2001-06-14 | Fwu-Iuan Hshieh | Trenched dmos device with low gate charges |
| JP2000188397A (en) * | 1998-12-22 | 2000-07-04 | Nissan Motor Co Ltd | Semiconductor device and its manufacture |
| EP1052690A2 (en) * | 1999-05-10 | 2000-11-15 | Intersil Corporation | Process or forming MOS-gated devices having self-aligned trenches |
| US6238981B1 (en) * | 1999-05-10 | 2001-05-29 | Intersil Corporation | Process for forming MOS-gated devices having self-aligned trenches |
| US6373098B1 (en) * | 1999-05-25 | 2002-04-16 | Fairchild Semiconductor Corporation | Trench-gated device having trench walls formed by selective epitaxial growth and process for forming device |
| US20040232481A1 (en) * | 2003-05-20 | 2004-11-25 | Robert Herrick | Structure and method for forming a trench MOSFET having self-aligned features |
| CN103187291A (en) * | 2011-12-29 | 2013-07-03 | 立新半导体有限公司 | Method of preparing trench semiconductor power discrete device |
| US20160276464A1 (en) * | 2014-07-25 | 2016-09-22 | Su Zhou Oriental Semiconductor Co.,Ltd | Power mos transistor and manufacturing method therefor |
| CN105990434A (en) * | 2014-09-12 | 2016-10-05 | 株式会社东芝 | Semiconductor device and manufacturing method thereof |
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| US20190348524A1 (en) * | 2018-05-09 | 2019-11-14 | Mitsubishi Electric Corporation | Silicon carbide semiconductor device, power converter, and method of manufacturing silicon carbide semiconductor device |
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Application publication date: 20220920 |