CN115084246B - Manufacturing method of silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of reducing gate charges - Google Patents
Manufacturing method of silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of reducing gate charges Download PDFInfo
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- CN115084246B CN115084246B CN202211002968.9A CN202211002968A CN115084246B CN 115084246 B CN115084246 B CN 115084246B CN 202211002968 A CN202211002968 A CN 202211002968A CN 115084246 B CN115084246 B CN 115084246B
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 36
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 230000005669 field effect Effects 0.000 title abstract description 4
- 239000004065 semiconductor Substances 0.000 title abstract description 4
- 230000004888 barrier function Effects 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 33
- 238000000151 deposition Methods 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims abstract description 4
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 claims 2
- 230000005684 electric field Effects 0.000 abstract description 10
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 2
- 150000004706 metal oxides Chemical class 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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Abstract
The invention provides a method for manufacturing a silicon carbide MOSFET (metal oxide semiconductor field effect transistor) capable of reducing gate charges, which comprises the following steps: forming a barrier layer on the drift layer of the silicon carbide substrate, and etching to form a groove; oxidizing the groove to form an insulating layer; depositing an insulating medium layer in the insulating layer; a barrier layer is formed on the drift layer again, and the barrier layer is etched to form a through hole and form a clamping groove; depositing polycrystalline silicon on the clamping grooves to form a grid polycrystalline silicon layer; forming a barrier layer on the drift layer again, etching, and performing ion implantation to form a source region; forming a barrier layer on the drift layer again, etching the barrier layer to form a through hole, depositing metal, and forming a source metal layer and a gate metal layer; removing all the barrier layers, and depositing metal on the silicon carbide substrate to form a drain metal layer; the high-quality insulating medium layer can effectively resist voltage, solves the problem of electric field concentration at the bottom of the traditional trench gate, increases the thickness of the insulating layer and reduces the gate capacitance.
Description
Technical Field
The invention relates to a method for manufacturing a silicon carbide MOSFET (metal oxide semiconductor field effect transistor) capable of reducing gate charges.
Background
Silicon carbide (SiC) materials for SiC devices have received much attention and research due to their excellent physical properties. The high-temperature high-power electronic device has the advantages of high input impedance, high switching speed, high working frequency, high temperature and high pressure resistance and the like, and is widely applied to the aspects of switching regulated power supplies, high-frequency heating, automobile electronics, power amplifiers and the like.
Oxidation preparation of SiO by SiC material 2 The quality is poor, the voltage resistance is low, and the silicon dioxide grown by the method is used as a gate dielectric to meet the gate control capability, so that the electric field concentration problem at the bottom of the trench type gate is serious, and the breakdown problem of the bottom gate dielectric needs to be solved. The actual longitudinal conductive channels of the trench gate SiC MOSFET are mainly distributed on the left and right sides, the gate polysilicon inside the trench gate SiC MOSFET does not contribute to the formation of the conductive channels, and the charge distribution area is larger, which results in a slow increase in gate voltage.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method for manufacturing a silicon carbide MOSFET for reducing gate charge; the high-quality insulating medium layer can effectively resist voltage, solves the problem of electric field concentration at the bottom of the traditional trench gate, increases the thickness of the insulating layer and reduces the gate capacitance.
The invention is realized by the following steps: a method of fabricating a silicon carbide MOSFET with reduced gate charge, comprising the steps of:
step 8, forming a barrier layer on the drift layer again, etching the barrier layer to form a through hole, depositing metal and forming a grid metal layer;
and 9, removing all the barrier layers, and depositing metal on the silicon carbide substrate to form a drain metal layer.
Furthermore, the grid polycrystalline silicon layer is in an inverted concave shape, and the insulating medium layer is in a convex shape.
Further, the insulating layer is silicon dioxide.
The invention has the advantages that:
1. the MOSFET is of a groove type, and besides a traditional silicon dioxide insulating layer, a high-quality insulating medium layer is additionally arranged in the groove;
2. the insulating medium is arranged at the bottom of the trench gate, the high-quality insulating medium layer can effectively resist voltage, the problem of electric field concentration at the bottom of the traditional trench gate is solved, meanwhile, the thickness of the insulating layer is increased, and the gate capacitance is reduced;
3. in the gate-shaped groove gate SiC MOSFET groove for reducing gate charges, the high-quality insulating dielectric layer is used for controlling and separating the gates of the symmetrical source electrodes at the left side and the right side, so that the current and the electric field are concentrated at the position where the side wall is close to the silicon dioxide insulating layer, and better gate control capability is realized.
Drawings
The invention will be further described with reference to the following examples with reference to the accompanying drawings.
Fig. 1 is a flow chart of a method of manufacturing a heterojunction diode integrated planar-gate silicon carbide MOSFET of the present invention.
Fig. 2 is a flow chart of a method of fabricating a planar gate silicon carbide MOSFET integrated with a heterojunction diode according to the present invention.
Fig. 3 is a flow chart of a method for manufacturing a heterojunction diode integrated planar gate silicon carbide MOSFET of the present invention.
Fig. 4 is a flow chart of a method of fabricating a planar gate silicon carbide MOSFET integrated with a heterojunction diode according to the present invention.
Fig. 5 is a flow chart of a method of fabricating a planar gate silicon carbide MOSFET integrated with a heterojunction diode according to the present invention.
Fig. 6 is a flow chart of a method of fabricating a planar gate silicon carbide MOSFET integrated with a heterojunction diode according to the invention.
Fig. 7 is a flow chart of a method of fabricating a planar gate silicon carbide MOSFET integrated with a heterojunction diode according to the invention.
Fig. 8 is a flow chart of a method of fabricating a planar gate silicon carbide MOSFET integrated with a heterojunction diode according to the invention.
Figure 9 is a flow chart diagram nine of a method of fabricating a planar gate silicon carbide MOSFET incorporating a heterojunction diode in accordance with the present invention.
Fig. 10 is a schematic diagram of a planar gate silicon carbide MOSFET integrated with a heterojunction diode according to the present invention.
Detailed Description
As shown in fig. 1 to 10, a method for manufacturing a silicon carbide MOSFET with reduced gate charge according to the present invention includes the steps of:
step 8, forming a barrier layer a on the drift layer 2 again, etching the barrier layer a to form a through hole, depositing metal and forming a grid metal layer 6;
and 9, removing all the barrier layers a, and depositing metal on the silicon carbide substrate 1 to form a drain metal layer 7.
As shown in fig. 10, the MOSFET obtained by the above manufacturing method includes:
a silicon carbide substrate 1 having a silicon carbide layer,
the drift layer 2 is arranged on the upper side surface of the silicon carbide substrate 1; a groove 21 is arranged on the drift layer 2, and a source region 22 is arranged on the drift layer 2;
the insulating layer 3 is arranged in the groove 21, an insulating medium layer 31 is arranged in the insulating layer 3, and a clamping groove 32 is formed between the insulating medium layer 31 and the insulating layer 3; the side wall of the insulating layer 3 is connected with the source region 22, the insulating medium layer 31 is in a convex shape, and the insulating layer 3 is made of silicon dioxide;
the grid polycrystalline silicon layer 4 is arranged in the clamping groove 32, and the grid polycrystalline silicon layer 4 is in an inverted concave shape;
the source metal layer 5, the source metal layer 5 is connected to the source region 22, the source metal layer 5 can also be connected to the drift layer 2, and the conductive area is increased;
a gate metal layer 6, the gate metal layer 6 being connected to the gate polysilicon layer 5;
and a drain metal layer 7, the drain metal layer 7 being connected to the lower side face of the silicon carbide substrate 1.
The MOSFET is of a trench type, a high-quality insulating medium layer 31 is additionally arranged in the trench except a traditional silicon dioxide insulating layer 3, the insulating medium layer 31 is generated by deposition, the quality is higher, the reliability of a grid metal layer 6 is improved, the high-quality insulating medium layer 31 can effectively resist voltage, the problem of electric field concentration at the bottom of a traditional trench grid is solved, the thickness of the insulating layer is increased, and the grid capacitance is reduced.
The insulating medium layer 31 increases the thickness of a voltage-resistant layer at the bottom of the trench gate, and increases the thickness of a bottom insulating layer, so that the bottom capacitance of the trench gate is reduced, an electric field is weakened, and the problem of electric field concentration is structurally reduced.
The gate control of the symmetrical source electrodes 22 at the left side and the right side is separated through the high-quality insulating medium layer 31 and the insulating layer 3, the current and the electric field are concentrated at the position of the side wall close to the silicon dioxide insulating layer, and better gate control capability is realized; the high-quality insulating medium layer 31 increases the control capability of the trench type gate, the high-quality insulating medium at the bottom reduces the problem of electric field concentration at the bottom, and the parasitic capacitance of the gate is also reduced.
While specific embodiments of the invention have been described, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, as equivalent modifications and variations as will be made by those skilled in the art in light of the spirit of the invention are intended to be included within the scope of the appended claims.
Claims (3)
1. A method of fabricating a silicon carbide MOSFET for reducing gate charge, comprising the steps of:
step 1, forming a barrier layer on a drift layer of a silicon carbide substrate, etching the barrier layer to form a through hole, and etching the drift layer through the through hole to form a groove;
step 2, oxidizing the groove to form an insulating layer;
step 3, depositing an insulating medium layer in the insulating layer;
step 4, a blocking layer is formed on the drift layer again, the blocking layer is etched to form a through hole, a clamping groove is formed, the insulating layer is arranged in the groove, an insulating medium layer is arranged in the insulating layer, the clamping groove is arranged between the insulating medium layer and the insulating layer, the through hole is located right above the clamping groove, and the insulating medium layer is in a convex shape;
step 5, depositing polycrystalline silicon on the clamping grooves to form a grid polycrystalline silicon layer;
step 6, forming a barrier layer on the drift layer again, etching the barrier layer to form a through hole, and performing ion implantation to form a source region, wherein the source region is arranged in the drift layer; the side wall of the insulating layer is connected with the source region;
step 7, forming a barrier layer on the drift layer again, etching the barrier layer to form a through hole, depositing metal and forming a source metal layer; the source metal layer is connected to the source region;
step 8, forming a barrier layer on the drift layer again, etching the barrier layer to form a through hole, depositing metal and forming a grid metal layer; the grid metal layer is connected to the grid polycrystalline silicon layer;
and 9, removing all the barrier layers, and depositing metal on the silicon carbide substrate to form a drain metal layer.
2. The method of claim 1, wherein the gate polysilicon layer is in the shape of an inverted dimple.
3. The method of claim 1, wherein the insulating layer is silicon dioxide.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211002968.9A CN115084246B (en) | 2022-08-22 | 2022-08-22 | Manufacturing method of silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of reducing gate charges |
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| CN202211002968.9A CN115084246B (en) | 2022-08-22 | 2022-08-22 | Manufacturing method of silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of reducing gate charges |
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| KR101920717B1 (en) * | 2013-01-14 | 2018-11-21 | 삼성전자주식회사 | Semiconductor device including dual parallel channel structure and method of fabricating the same |
| CN105161533A (en) * | 2015-07-02 | 2015-12-16 | 电子科技大学 | Silicon carbide VDMOS device and manufacturing method |
| JP6907233B2 (en) * | 2016-02-02 | 2021-07-21 | アーベーベー・シュバイツ・アーゲーＡＢＢ Ｓｃｈｗｅｉｚ ＡＧ | Power semiconductor device |
| CN114496761B (en) * | 2022-04-06 | 2022-06-17 | 泰科天润半导体科技（北京）有限公司 | Manufacturing method of circular gate longitudinal MOSFET power device |
| CN114744023A (en) * | 2022-04-25 | 2022-07-12 | 泰科天润半导体科技（北京）有限公司 | Manufacturing method of U-shaped gate groove type SiC MOSFET |
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