CN115376923A - Manufacturing method of asymmetric groove type silicon carbide MOSFET - Google Patents

Manufacturing method of asymmetric groove type silicon carbide MOSFET Download PDF

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Publication number
CN115376923A
CN115376923A CN202210935428.XA CN202210935428A CN115376923A CN 115376923 A CN115376923 A CN 115376923A CN 202210935428 A CN202210935428 A CN 202210935428A CN 115376923 A CN115376923 A CN 115376923A
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layer
region
barrier layer
hole
pinch
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张瑜洁
张长沙
李佳帅
何佳
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Global Power Technology Co Ltd
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Global Power Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

The invention provides a manufacturing method of an asymmetric groove type silicon carbide MOSFET, which comprises the steps of forming a barrier layer on a drift layer of a silicon carbide substrate, etching the barrier layer to form a through hole, and carrying out ion implantation on the drift layer through the through hole to form a masking layer; reforming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer through the through hole to form a conductive region; removing the barrier layer, and performing ion implantation to form a pinch-off region; reforming the barrier layer, etching the barrier layer and the pinch-off region to form a gate region, oxidizing the gate region and forming a gate insulating layer; depositing a gate electrode on the gate insulating layer; reforming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the pinch-off region through the through hole to form a source region; and through metal deposition, a source metal layer, a grid metal layer and a drain metal layer are respectively formed, so that the switching speed of the device is increased, and the on-resistance is reduced.

Description

Manufacturing method of asymmetric groove type silicon carbide MOSFET
Technical Field
The invention relates to a manufacturing method of an asymmetric groove type silicon carbide MOSFET.
Background
Silicon carbide (SiC) materials for SiC devices have received much attention and research due to their excellent physical properties. The high-temperature high-power electronic device has the advantages of high input impedance, high switching speed, high working frequency, high temperature and high pressure resistance and the like, and is widely applied to the aspects of switching voltage-stabilized power supplies, high-frequency heating, automobile electronics, power amplifiers and the like.
However, because the SiC critical breakdown field strength is very high and the gate oxide quality is poor, in the trench SiC MOSFET, the gate oxide bears a large voltage, and the electric field strength is very large, so the problem of the overlarge electric field strength at the bottom of the gate needs to be solved. Meanwhile, the reduction of the on-resistance is the constant pursuit of the power MOSFET, and each method for reducing the on-resistance is emphasized; since the switching speed is an important requirement for miniaturization of power electronic devices, increasing the switching speed is also an important trend in the development of device characteristics.
The traditional groove type SiC MOSFET is of a symmetrical structure, the gate oxide position of the traditional groove type SiC MOSFET needs to bear large voltage, the electric field intensity is very high, and the problem of gate oxide reliability needs to be solved by aiming at design. Meanwhile, due to the symmetrical structure, the gate control area is large, and the gate capacitance and the gate charge are both large, which means that the switching speed of the device is slow. This situation requires a targeted reduction in gate area to increase device switching speed. At the same time, there is no way to reduce the on-resistance of the device.
Disclosure of Invention
The invention aims to provide a manufacturing method of an asymmetric groove type silicon carbide MOSFET, which can improve the switching speed of a device and reduce the on-resistance.
The invention is realized by the following steps: a method for manufacturing an asymmetric trench type silicon carbide MOSFET comprises the following steps:
step 1: forming a barrier layer on the drift layer of the silicon carbide substrate, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer through the through hole to form a masking layer;
step 2: reforming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer through the through hole to form a conductive region;
and step 3: removing the barrier layer, and performing ion implantation to form a pinch-off region;
and 4, step 4: reforming the barrier layer, etching the barrier layer and the pinch-off region to form a gate region, oxidizing the gate region and forming a gate insulating layer;
and 5: depositing a gate electrode on the gate insulating layer;
step 6: reforming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the pinch-off region through the through hole to form a source region;
and 8: reforming the barrier layer, etching the barrier layer to form a source region metal through hole, and depositing the source region metal through hole to the source region to form a source electrode metal layer;
and step 9: reforming the barrier layer, etching the gate metal deposition region on the barrier layer, and depositing to form a gate metal layer;
step 10: and removing the barrier layer, and depositing on the silicon carbide substrate to form a drain metal layer.
Further, the step 4 is further specifically: and reforming the barrier layer, etching the barrier layer, the pinch-off region and the masking layer to form a gate region, and oxidizing the gate region to form a gate insulating layer.
Further, the masking layer is of a P + type, the conductive region is of an N + type, and the source region is of an N type.
Furthermore, the pinch-off region is of a P type, the doping concentration of the pinch-off region is smaller than that of the source region, and the doping concentration of the pinch-off region is larger than that of the drift layer.
The invention has the advantages that:
1. the drift regions below and on the left side of the grid are provided with the masking layers, and the masking layers can effectively reduce the electric field intensity below the grid and at the groove corners and improve the grid oxygen reliability;
2. a masking layer in a drift layer on the left side of the grid is connected with a source electrode ground potential to form side grounding, so that the switching speed of the device is improved, the source electrode ground potential is the ground potential when the device works at the source electrode, and the side grounding is that a side masking layer is connected with the source electrode and is connected with the ground potential;
3. and the right part of the gate drift layer extends from the top end of the drift layer to a conductive region with the same thickness as the masking layer, and the region has high doping concentration and can effectively reduce the on-resistance.
Drawings
The invention will be further described with reference to the following examples with reference to the accompanying drawings.
Fig. 1 is a first flowchart of a method of fabricating an asymmetric trench silicon carbide MOSFET of the present invention.
Fig. 2 is a second flow chart of a method of fabricating an asymmetric trench silicon carbide MOSFET of the present invention.
Fig. 3 is a third flowchart of a method of fabricating an asymmetric trench silicon carbide MOSFET according to the present invention.
Fig. 4 is a flow chart diagram of a method of fabricating an asymmetric trench silicon carbide MOSFET of the present invention.
Fig. 5 is a flow chart of a fifth method of fabricating an asymmetric trench silicon carbide MOSFET of the present invention.
Fig. 6 is a sixth flow chart of a method of fabricating an asymmetric trench silicon carbide MOSFET of the present invention.
Fig. 7 is a seventh flow chart of a method of fabricating an asymmetric trench silicon carbide MOSFET of the present invention.
Fig. 8 is a seventh flow chart of a method of fabricating an asymmetric trench silicon carbide MOSFET of the present invention.
Fig. 9 is a seventh flow chart of a method of fabricating an asymmetric trench silicon carbide MOSFET of the present invention.
Fig. 10 is a schematic diagram of an asymmetric trench silicon carbide MOSFET according to the present invention.
Detailed Description
Referring to fig. 1 to 10, a method for fabricating an asymmetric trench silicon carbide MOSFET according to the present invention includes the following steps:
step 1: forming a barrier layer a on the drift layer 2 of the silicon carbide substrate 1, etching the barrier layer a to form a through hole, and performing ion implantation on the drift layer 2 through the through hole to form a masking layer 211;
step 2: reforming the barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation on the drift layer 2 through the through hole to form a conductive region 212;
and step 3: removing the barrier layer a, and performing ion implantation to form a pinch-off region 3;
and 4, step 4: reforming the barrier layer a, etching the barrier layer a and the pinch-off region to form a gate region, oxidizing the gate region and forming a gate insulating layer 31;
and 5: depositing a gate electrode 4 on the gate insulating layer 31;
step 6: reforming the barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation on the pinch-off region 3 through the through hole to form a source region 32;
and 8: reforming the barrier layer a, etching the barrier layer a to form a source region metal through hole, and depositing the source region 32 through the source region metal through hole to form a source electrode metal layer 5;
and step 9: reforming the barrier layer a, etching a gate metal deposition area on the barrier layer a, and depositing to form a gate metal layer 6;
step 10: and removing the barrier layer a, and depositing a drain metal layer 7 on the silicon carbide substrate 1.
The masking layer 211 is P + type, the conductive region 212 is N + type, and the source region 32 is N type; the pinch-off region 3 is P-type, the doping concentration of the pinch-off region 3 is less than that of the source region 32, and the doping concentration of the pinch-off region 3 is greater than that of the drift layer 2.
As shown in fig. 10, the above method results in a MOSFET comprising:
a silicon carbide substrate 1 having a silicon carbide layer,
the drift layer 2 is arranged on the upper side face of the silicon carbide substrate 1, a groove 21 is arranged on the drift layer 2, and a masking layer 211 and a conductive region 212 are arranged in the groove 21;
the pinch-off region 3 is arranged on the upper side surface of the drift layer 2, the bottom surface of the pinch-off region 3 is connected to the conductive region 212 and the masking layer 211, a gate insulating layer 31 is arranged in the pinch-off region 3, the bottom surface of the gate insulating layer 31 is connected to the masking layer 211, a source region 32 is arranged on the pinch-off region 3, the side surface of the source region 32 is connected to one side surface of the gate insulating layer 31, and the gate insulating layer 31 is in a groove shape;
a gate electrode 4, the gate electrode 4 being disposed in the gate insulating layer 31;
a source metal layer 5, the source metal layer 5 being connected to the pinch-off region 3 and a source region 32;
a gate metal layer 6, the gate metal layer 6 being connected to the gate 4;
and a drain metal layer 7, the drain metal layer 7 being connected to the underside of the silicon carbide substrate 1.
The masking layer 211 is P + type, the conductive region 212 is N + type, and the source region 32 is N type; the pinch-off region 3 is of a P type, the doping concentration of the pinch-off region 3 is smaller than that of the source region 32, and the doping concentration of the pinch-off region 3 is larger than that of the drift layer 2; the masking layer 211 is L-shaped, the masking layer 211 and the conductive region 212 form a card slot, and the lower portion of the gate insulating layer 31 is disposed in the card slot.
A P + mask layer 211 is formed at a lower end of the gate insulating layer 31 (typically, an oxide layer, siO 2), and the mask layer 211 reduces an electric field intensity at the lower end of the gate insulating layer 31, thereby improving reliability of the gate insulating layer 31.
A P + masking layer 211 is provided in the drift region 2 on the left side of the gate insulating layer 31 (typically an oxide layer, siO 2), and the masking layer 211 is connected to the source ground potential, which can improve the switching speed of the device.
The N + doped conductive region 212 is in the drift layer 2, and the conductive region 212 serves as a conductive channel of the MOSFET, which can effectively reduce the on-resistance.
The source region 32 is also heavily doped n-type, so that ohmic contact between the source region 32 and the source metal layer 5 is realized.
The pinch-off region 3 is doped p-type, and the doping concentration is lower than that of the source region 32 and higher than that of the drift layer 2.
The masking layer 211 can improve the grid voltage-resistant characteristic and the grid oxygen reliability, and the left masking layer 211 structure of the grid 4 is connected with the source electrode ground, so that the switching speed of the device can be improved. A low-resistance conducting path is constructed in an n-type heavily doped conducting region 212 in a drift layer 2 on the right side of a grid 4, the on-resistance of an MOS can be effectively reduced, a masking layer is connected with a source electrode ground potential, the process mainly realizes the potential reduction of an internal masking layer and only provides a little potential current, the source electrode ground potential is the ground potential when a device works, the side grounding means that a side masking layer is connected with a source electrode, and the ground potential is connected.
Although specific embodiments of the invention have been described above, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the appended claims.

Claims (4)

1. A method for manufacturing an asymmetric trench type silicon carbide MOSFET is characterized in that: the method comprises the following steps:
step 1: forming a barrier layer on the drift layer of the silicon carbide substrate, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer through the through hole to form a masking layer;
and 2, step: reforming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer through the through hole to form a conductive region;
and step 3: removing the barrier layer, and performing ion implantation to form a pinch-off region;
and 4, step 4: reforming the barrier layer, etching the barrier layer and the pinch-off region to form a gate region, oxidizing the gate region and forming a gate insulating layer;
and 5: depositing a gate electrode on the gate insulating layer;
step 6: reforming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation on the pinch-off region through the through hole to form a source region;
and 8: reforming the barrier layer, etching the barrier layer to form a source region metal through hole, and depositing the source region metal through hole to the source region to form a source electrode metal layer;
and step 9: reforming the barrier layer, etching a grid metal deposition area on the barrier layer, and depositing to form a grid metal layer;
step 10: and removing the barrier layer, and depositing on the silicon carbide substrate to form a drain metal layer.
2. The method of claim 1, wherein the step of forming an asymmetric trench silicon carbide MOSFET comprises: the step 4 is further specifically as follows: and reforming the barrier layer, etching the barrier layer, the pinch-off region and the masking layer to form a gate region, and oxidizing the gate region to form a gate insulating layer.
3. The method of claim 1, wherein the step of forming an asymmetric trench silicon carbide MOSFET comprises: the masking layer is of a P + type, the conductive region is of an N + type, and the source region is of an N type.
4. The method of fabricating an asymmetric trench silicon carbide MOSFET as claimed in claim 1 wherein: the pinch-off region is of a P type, the doping concentration of the pinch-off region is smaller than that of the source region, and the doping concentration of the pinch-off region is larger than that of the drift layer.
CN202210935428.XA 2022-08-05 2022-08-05 Manufacturing method of asymmetric groove type silicon carbide MOSFET Pending CN115376923A (en)

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