CN114744023A - Manufacturing method of U-shaped gate groove type SiC MOSFET - Google Patents
Manufacturing method of U-shaped gate groove type SiC MOSFET Download PDFInfo
- Publication number
- CN114744023A CN114744023A CN202210436851.5A CN202210436851A CN114744023A CN 114744023 A CN114744023 A CN 114744023A CN 202210436851 A CN202210436851 A CN 202210436851A CN 114744023 A CN114744023 A CN 114744023A
- Authority
- CN
- China
- Prior art keywords
- layer
- region
- gate
- barrier layer
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 230000004888 barrier function Effects 0.000 claims abstract description 46
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 36
- 230000000873 masking effect Effects 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 24
- 238000005468 ion implantation Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 238000002407 reforming Methods 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 10
- 238000001465 metallisation Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 abstract 1
- 230000005684 electric field Effects 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a manufacturing method of a U-shaped gate groove type SiC MOSFET, which comprises the following steps: forming a drift layer on a silicon carbide substrate, forming a barrier layer on the drift layer, etching the barrier layer, and performing ion implantation to form a conductive region; re-forming the barrier layer, etching the barrier layer, and performing ion implantation to form a masking layer; restoring the region above the masking layer to be the same as the impurity concentration of the drift layer through impurity compensation; etching to form a gate region, oxidizing the gate region and forming a gate insulating layer; depositing a grid electrode; forming a pinch-off region, a source metal layer and a grid metal layer respectively by reforming a barrier layer, etching the barrier layer and implanting ions; and removing all barrier layers, and depositing a drain metal layer on the silicon carbide substrate, so that the on-resistance is reduced, and the reliability of gate oxide is improved.
Description
Technical Field
The invention relates to a manufacturing method of a U-shaped gate groove type SiC MOSFET.
Background
Silicon carbide (SiC) materials for SiC devices have received much attention and research due to their excellent physical properties. The high-temperature high-power electronic device has the advantages of high input impedance, high switching speed, high working frequency, high temperature and high pressure resistance and the like, and is widely applied to the aspects of switching regulated power supplies, high-frequency heating, automobile electronics, power amplifiers and the like.
However, because the SiC critical breakdown field strength is very high and the gate oxide quality is poor, in the U-shaped gate SiC MOSFET, the electric field is concentrated at the bottom of the gate oxide where the angle is the smallest, and the electric field strength is very high, so the problem of too high electric field strength at the bottom of the U-shaped gate needs to be solved. Meanwhile, the reduction of the on-resistance is a constant pursuit of the power MOSFET, and each method for reducing the on-resistance should be emphasized.
Disclosure of Invention
The invention aims to provide a manufacturing method of a U-shaped gate groove type SiC MOSFET, which reduces the on-resistance and improves the gate oxide reliability.
The invention is realized by the following steps: a manufacturing method of a U-shaped gate groove type SiC MOSFET comprises the following steps:
step 1: forming a drift layer on a silicon carbide substrate, forming a barrier layer on the drift layer, etching the barrier layer to form a through hole of a conductive region, and performing ion implantation on the drift layer through the through hole to form the conductive region;
step 2: reforming the barrier layer, etching the barrier layer to form a masking layer through hole, and performing ion implantation on the drift layer through the masking layer through hole to form a masking layer;
and step 3: ion implantation is carried out through the through holes of the masking layer, and the region above the masking layer is restored to be the same as the impurity concentration of the drift layer through impurity compensation;
and 4, step 4: etching to form a gate region, oxidizing the gate region and forming a gate insulating layer;
and 5: depositing a grid electrode;
step 6: forming a barrier layer on the drift layer again, etching the barrier layer to form a pinch-off region through hole, and performing ion implantation on the drift layer through the pinch-off region through hole to form a pinch-off region;
and 7: forming a barrier layer on the drift layer again, etching the barrier layer to form a source region through hole, and performing ion implantation on the drift layer through the source region through hole to form a source region;
and 8: forming a barrier layer on the drift layer again, etching the barrier layer to form a source region metal through hole, and depositing the source region metal through hole to form a source electrode metal layer;
and step 9: reforming the barrier layer, etching the gate metal deposition region on the barrier layer, and depositing to form a gate metal layer;
step 10: all barrier layers are removed and a drain metal layer is deposited on the silicon carbide substrate.
Further, the gate insulating layer is U-shaped.
Furthermore, the pinch-off region is doped in a p-type mode, and the doping concentration of the pinch-off region is smaller than that of the source region and higher than that of the drift layer.
The invention has the advantages that:
the U-shaped masking layer is arranged below the gate of the U-shaped gate trench type SiC MOSFET device, the masking layer is arranged at the position where the gate oxide angle is sharpest, namely the position where the gate oxide electric field intensity is highest, the masking layer can effectively reduce the electric field intensity at the groove angle and improve the gate oxide reliability;
second, on the left side and the right side of the masking layer, n-type heavily doped conductive regions can construct low-resistance conductive channels after the MOS tube is conducted, and the on-resistance of the MOS can be effectively reduced;
and thirdly, the conducting channel of the device is a high-concentration n-type conducting region, and the conducting channel of the device is narrower, so that the transverse dimension can be further reduced, and the area of a unit cell is reduced.
Drawings
The invention will be further described with reference to the following examples and figures.
Fig. 1 is a first flowchart of a method for manufacturing a U-gate trench SiC MOSFET according to the present invention.
Fig. 2 is a flow chart of a manufacturing method of a U-shaped gate trench SiC MOSFET of the present invention.
Fig. 3 is a flow chart of a manufacturing method of a U-shaped gate trench SiC MOSFET of the present invention.
Fig. 4 is a fourth flowchart of a method for manufacturing a U-gate trench SiC MOSFET of the present invention.
Fig. 5 is a flow chart of a method for manufacturing a U-gate trench SiC MOSFET of the present invention.
Fig. 6 is a flow chart of a method for manufacturing a U-shaped gate trench SiC MOSFET according to a sixth embodiment of the present invention.
Fig. 7 is a flow chart of a method for manufacturing a U-shaped gate trench SiC MOSFET of the present invention.
Fig. 8 is a flow chart of an eighth manufacturing method of a U-gate trench SiC MOSFET of the present invention.
Fig. 9 is a flowchart nine of a method for manufacturing a U-gate trench SiC MOSFET according to the present invention.
Fig. 10 is a flowchart ten of a method for manufacturing a U-gate trench SiC MOSFET according to the present invention.
Fig. 11 is a schematic structural view of a U-gate trench SiC MOSFET of the present invention.
Detailed Description
As shown in fig. 1 to 10, the method for manufacturing a U-gate trench SiC MOSFET of the present invention includes the steps of:
step 1: forming a drift layer 2 on a silicon carbide substrate 1, forming a barrier layer 9 on the drift layer 2, etching the barrier layer 9 to form a conductive region through hole, and performing ion implantation on the drift layer 2 through the through hole to form a conductive region 22;
and 2, step: reforming the barrier layer 9, etching the barrier layer to form a masking layer through hole, and performing ion implantation on the drift layer through the masking layer through hole to form a masking layer 21;
and step 3: ion implantation is carried out through the through holes of the masking layer 21, and the region above the masking layer is restored to be the same as the impurity concentration of the drift layer through impurity compensation;
and 4, step 4: etching to form a gate region, oxidizing the gate region, and forming a gate insulating layer 23, wherein the gate insulating layer 23 is U-shaped;
and 5: depositing a grid electrode 3;
step 6: reforming a barrier layer 9 on the drift layer 2, etching the barrier layer to form a pinch-off region through hole, and performing ion implantation on the drift layer through the pinch-off region through hole to form a pinch-off region 5, wherein the pinch-off region 5 is doped in a p type manner, and the doping concentration of the pinch-off region 5 is less than that of the source region 4 and higher than that of the drift layer 2;
and 7: reforming the barrier layer 9 on the drift layer 2, etching the barrier layer to form a source region through hole, and performing ion implantation on the drift layer 2 through the source region through hole to form a source region 4;
and 8: a barrier layer 9 is formed on the drift layer 2 again, the barrier layer is etched to form a source region metal through hole, and a source region metal layer 6 is formed by depositing the source region metal through hole on the source region;
and step 9: reforming the barrier layer 9, etching a gate metal deposition area on the barrier layer 9, and depositing to form a gate metal layer 7;
step 10: all barrier layers 9 are removed and a drain metal layer 8 is deposited on the silicon carbide substrate 1.
As shown in fig. 11, the U-gate trench SiC MOSFET manufactured by the above manufacturing method includes:
a silicon carbide substrate 1, a silicon carbide substrate,
the drift layer 2 is arranged on the upper side surface of the silicon carbide substrate 1; a masking layer 21, a conductive region 22 and a gate insulating layer 23 are arranged on the drift layer 2, the bottom of the conductive region 22 and the bottom of the masking layer 21 are connected to the drift layer 2, the side surface of the masking layer 21 is connected to the conductive region 22, the side surface of the conductive region 22 is connected to the drift layer 2, a U-shaped groove 24 is arranged on the drift layer 2, the bottom of the U-shaped groove 24 is connected to the top of the masking layer 21, and the gate insulating layer 23 is arranged on the U-shaped groove 24;
a gate 3, the gate 3 being connected to the gate insulating layer 23;
the bottom of the source region 4 is respectively connected with the conductive region 22 and the drift layer 2, one side surface of the source region 4 is connected with the gate insulating layer 23, and the gate insulating layer 23 is U-shaped;
the bottom of the pinch-off region 5 is connected to the drift layer 2, one side face of the pinch-off region 5 is connected to the source region 4, the pinch-off region 5 is doped in a p type, and the doping concentration of the pinch-off region 5 is smaller than that of the source region 4 and higher than that of the drift layer 3;
a source metal layer 6, wherein the source metal layer 6 is connected to the top of the source region 4 and the top of the pinch-off region 5;
a gate metal layer 7, the gate metal layer 7 being connected to the gate 3;
and a drain metal layer 8, wherein the drain metal layer 8 is connected to the lower side surface of the silicon carbide substrate 1.
The masking layer 21 with P + in the minimum angle region is arranged at the lower end of the gate insulating layer 23 (generally, an oxide layer, SiO 2), and the masking layer 21 reduces the electric field intensity at the lower end of the gate dielectric and improves the reliability of the gate insulating layer 23.
The masking layer 21 surrounds the bottom end of the gate insulating layer 23 with the highest electric field, so that the electric field intensity of the gate oxide is effectively reduced, and the reliability of the gate oxide is improved. An n-type heavily doped conductive region is manufactured in a narrow interval below the pinch-off region 5, and a low-resistance conductive path is constructed in the conductive region, so that the on-resistance of the MOS can be effectively reduced.
Although specific embodiments of the invention have been described above, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the appended claims.
Claims (3)
1. A manufacturing method of a U-shaped gate groove type SiC MOSFET is characterized by comprising the following steps:
step 1: forming a drift layer on a silicon carbide substrate, forming a barrier layer on the drift layer, etching the barrier layer to form a through hole of a conductive region, and performing ion implantation on the drift layer through the through hole to form the conductive region;
step 2: reforming the barrier layer, etching the barrier layer to form a masking layer through hole, and performing ion implantation on the drift layer through the masking layer through hole to form a masking layer;
and step 3: ion implantation is carried out through the through holes of the masking layer, and the region above the masking layer is restored to be the same as the impurity concentration of the drift layer through impurity compensation;
and 4, step 4: etching to form a gate region, oxidizing the gate region and forming a gate insulating layer;
and 5: depositing a grid electrode;
step 6: forming a barrier layer on the drift layer again, etching the barrier layer to form a pinch-off region through hole, and performing ion implantation on the drift layer through the pinch-off region through hole to form a pinch-off region;
and 7: forming a barrier layer on the drift layer again, etching the barrier layer to form a source region through hole, and performing ion implantation on the drift layer through the source region through hole to form a source region;
and 8: forming a barrier layer on the drift layer again, etching the barrier layer to form a source region metal through hole, and depositing the source region metal through hole to the source region to form a source electrode metal layer;
and step 9: reforming the barrier layer, etching the gate metal deposition region on the barrier layer, and depositing to form a gate metal layer;
step 10: all barrier layers are removed and a drain metal layer is deposited on the silicon carbide substrate.
2. The method of manufacturing a U-gate trench SiC MOSFET of claim 1 wherein the gate insulating layer is U-shaped.
3. The method of claim 1, wherein the pinch-off region is doped p-type, and the doping concentration of the pinch-off region is less than the doping concentration of the source region and higher than the doping concentration of the drift layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210436851.5A CN114744023A (en) | 2022-04-25 | 2022-04-25 | Manufacturing method of U-shaped gate groove type SiC MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210436851.5A CN114744023A (en) | 2022-04-25 | 2022-04-25 | Manufacturing method of U-shaped gate groove type SiC MOSFET |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114744023A true CN114744023A (en) | 2022-07-12 |
Family
ID=82283569
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210436851.5A Pending CN114744023A (en) | 2022-04-25 | 2022-04-25 | Manufacturing method of U-shaped gate groove type SiC MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114744023A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115000016A (en) * | 2022-08-08 | 2022-09-02 | 泰科天润半导体科技（北京）有限公司 | Manufacturing method of silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of improving current capacity |
| CN115084246A (en) * | 2022-08-22 | 2022-09-20 | 泰科天润半导体科技（北京）有限公司 | Manufacturing method of silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of reducing gate charges |
| CN115631998A (en) * | 2022-12-21 | 2023-01-20 | 泰科天润半导体科技（北京）有限公司 | Manufacturing method of shielded gate trench type silicon carbide MOSFET |
| CN115863398A (en) * | 2023-02-06 | 2023-03-28 | 苏州锴威特半导体股份有限公司 | Silicon carbide MOSFET and manufacturing method thereof |
-
2022
- 2022-04-25 CN CN202210436851.5A patent/CN114744023A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115000016A (en) * | 2022-08-08 | 2022-09-02 | 泰科天润半导体科技（北京）有限公司 | Manufacturing method of silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of improving current capacity |
| CN115000016B (en) * | 2022-08-08 | 2022-11-04 | 泰科天润半导体科技（北京）有限公司 | Manufacturing method of silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of improving current capacity |
| CN115084246A (en) * | 2022-08-22 | 2022-09-20 | 泰科天润半导体科技（北京）有限公司 | Manufacturing method of silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of reducing gate charges |
| CN115631998A (en) * | 2022-12-21 | 2023-01-20 | 泰科天润半导体科技（北京）有限公司 | Manufacturing method of shielded gate trench type silicon carbide MOSFET |
| CN115863398A (en) * | 2023-02-06 | 2023-03-28 | 苏州锴威特半导体股份有限公司 | Silicon carbide MOSFET and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114744023A (en) | Manufacturing method of U-shaped gate groove type SiC MOSFET | |
| KR20110065379A (en) | Method of forming an insulated gate field effect transistor device having a shield electrode structure | |
| WO2019228069A1 (en) | Lateral semiconductor device having shallow trench isolation structure arranged in staggered and interdigital manner | |
| CN115376924A (en) | Manufacturing method of trench type silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) with low forward conduction voltage drop of body diode | |
| CN114512535B (en) | Manufacturing method of double-channel SiC transverse LDMOS power device | |
| CN114496761B (en) | Manufacturing method of circular gate longitudinal MOSFET power device | |
| CN115831758A (en) | Manufacturing method of silicon carbide UMOSFET integrated with Schottky | |
| CN115360096A (en) | Manufacturing method of planar gate silicon carbide MOSFET integrated with heterojunction diode | |
| CN108538909A (en) | Hetero-junctions vertical double-diffusion metal-oxide-semiconductor field effect transistor and preparation method thereof with charge compensation block | |
| CN114759079A (en) | Manufacturing method of JBS (junction-junction) integrated groove type SiC transistor | |
| CN114744029A (en) | Manufacturing method of P-type SiC LDMOS power device | |
| CN114999922B (en) | Manufacturing method of silicon carbide MOSFET with voltage-resistant structure | |
| CN115376923A (en) | Manufacturing method of asymmetric groove type silicon carbide MOSFET | |
| CN217485451U (en) | U-shaped gate groove type SiC MOSFET | |
| CN115084221A (en) | Manufacturing method of low-grid-drain capacitance ladder-type grid groove type power device | |
| CN115148799A (en) | RF LDMOS device and manufacturing method thereof | |
| CN113410299B (en) | High-voltage-resistance n-channel LDMOS device and preparation method thereof | |
| CN218215312U (en) | Asymmetric groove type silicon carbide MOSFET | |
| CN115000016B (en) | Manufacturing method of silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of improving current capacity | |
| CN218274606U (en) | Silicon carbide MOSFET capable of improving current capacity | |
| CN218274611U (en) | Low body diode forward conduction voltage drop's ditch slot type carborundum MOSFET | |
| CN217485454U (en) | Low-grid-leakage capacitance ladder-type grid groove type power device | |
| CN116779537B (en) | Method for manufacturing semiconductor structure and semiconductor structure | |
| CN217485453U (en) | Groove type SiC transistor integrated with JBS | |
| US12002892B2 (en) | Semiconductor device with embedded Schottky diode and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |