CN217485453U

CN217485453U - Groove type SiC transistor integrated with JBS

Info

Publication number: CN217485453U
Application number: CN202220963571.5U
Authority: CN
Inventors: 张瑜洁; 何佳; 李佳帅; 张长沙
Original assignee: Liuyang Taike Tianrun Semiconductor Technology Co ltd
Current assignee: Liuyang Taike Tianrun Semiconductor Technology Co ltd
Priority date: 2022-04-25
Filing date: 2022-04-25
Publication date: 2022-09-23
Anticipated expiration: 2032-04-25

Abstract

The utility model provides an integrated JBS's ditch slot type SiC transistor, include: the drift layer is arranged on the upper end surface of the silicon carbide substrate; a masking layer, a Schottky metal layer and a grid insulating layer are arranged on the drift layer; the top of the masking layer is connected to the bottom of the Schottky metal layer, and the masking layer is connected to the gate insulating layer; the grid is arranged in the grid insulating layer; the bottom of the source region is respectively connected with the drift layer and the Schottky metal layer, and the side face of the source region is connected with the grid insulation layer; the source metal layer is connected to the source region; the grid metal layer is connected to the grid; and the drain electrode metal layer is connected to the lower end face of the silicon carbide substrate, a JBS structure is adopted, the low starting voltage of gold half contact is achieved, the high voltage withstanding characteristic of a PN junction is achieved, and the conduction loss of a body diode is reduced on the basis of no loss voltage withstanding characteristic.

Description

Groove type SiC transistor integrated with JBS

Technical Field

The utility model relates to an integrated JBS's slot type SiC transistor.

Background

Silicon carbide (SiC) materials for SiC devices have received much attention and research due to their excellent physical properties. The high-temperature high-power electronic device has the advantages of high input impedance, high switching speed, high working frequency, high temperature and high pressure resistance and the like, and is widely applied to the aspects of switching regulated power supplies, high-frequency heating, automobile electronics, power amplifiers and the like.

However, because the SiC critical breakdown field strength is very high and the gate oxide quality is poor, in the trench gate type SiC MOSFET, the gate oxide is easily broken down, especially at the trench corners, the electric field is concentrated, and the electric field strength is very high, so the problem of the overlarge electric field strength at the trench corners needs to be solved. Meanwhile, the body diode has follow current in practical application for a long time, and the body diode of the traditional device has high turn-on voltage due to the characteristics of SiC materials, so that large loss is caused.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model lies in providing an integrated JBS's ditch slot type SiC transistor, has adopted the JBS structure, and the low opening voltage of existing gold half contact has the high withstand voltage characteristic of PN junction again, has reduced the body diode conduction loss on the basis of not losing withstand voltage characteristic.

The utility model discloses a realize like this: an integrated JBS trench SiC transistor comprising:

a silicon carbide substrate,

the drift layer is arranged on the upper end surface of the silicon carbide substrate; a masking layer, a Schottky metal layer and a grid electrode insulating layer are arranged on the drift layer; the top of the masking layer is connected to the bottom of the Schottky metal layer, and the masking layer is connected to the gate insulating layer;

the grid electrode is arranged in the grid electrode insulating layer;

the bottom of the source region is respectively connected with the drift layer and the Schottky metal layer, and the side face of the source region is connected with the grid insulation layer;

a source metal layer connected to the source region;

a gate metal layer connected to the gate;

and the drain metal layer is connected to the lower end face of the silicon carbide substrate.

Furthermore, the masking layer is of a P + type, and the cross section of the masking layer is of an L type.

The utility model has the advantages of:

the trench type SiC MOSFET device is provided with a masking layer at a trench corner below a grid, the masking layer is arranged at a gate oxide trench corner, namely the highest gate oxide electric field intensity position, and the masking layer can effectively reduce the electric field intensity at the trench corner and improve the gate oxide reliability;

secondly, a metal semiconductor foundation is constructed above the masking layer, a Schottky junction is constructed, and the conduction voltage drop can be reduced during the conduction period of the MOS diode, so that the power consumption of the body diode is reduced;

thirdly, the basic parasitic pn junction diode of the device also participates in the conduction and can maintain the reverse voltage resistance;

and fourthly, the Schottky junction and the pn junction existing in the original device structure form a JBS diode, and the bipolar degradation effect is eliminated due to the formation of the diode.

Drawings

The invention will be further described with reference to the following examples with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a JBS-integrated trench SiC transistor according to the present invention.

Fig. 2 is a flow chart of a method for manufacturing a JBS-integrated trench SiC transistor according to the present invention.

Fig. 3 is a flow chart of a method for manufacturing a JBS-integrated trench SiC transistor according to the present invention.

Fig. 4 is a flow chart of a third method for manufacturing a trench SiC transistor integrated with JBS according to the present invention.

Fig. 5 is a fourth flowchart of a method for manufacturing a JBS-integrated trench SiC transistor according to the present invention.

Fig. 6 is a flow chart of a method for manufacturing a JBS-integrated trench SiC transistor according to a fifth embodiment of the present invention.

Fig. 7 is a flow chart of a sixth method for manufacturing a JBS-integrated trench SiC transistor according to the present invention.

Fig. 8 is a flow chart of a method for manufacturing a JBS-integrated trench SiC transistor according to the present invention.

Fig. 9 is a flow chart eight illustrating a method for manufacturing a JBS-integrated trench SiC transistor according to the present invention.

Fig. 10 is a flowchart nine illustrating a method for manufacturing a JBS-integrated trench SiC transistor according to the present invention.

Fig. 11 is a flowchart ten illustrating a method for manufacturing a JBS-integrated trench SiC transistor according to the present invention.

Detailed Description

As shown in fig. 1, the utility model relates to an integrated JBS's ditch slot type SiC transistor includes:

a silicon carbide substrate 1, a silicon carbide substrate,

the drift layer 2 is arranged on the upper end face of the silicon carbide substrate 1; a masking layer 21, a Schottky metal layer 22 and a gate insulating layer 23 are arranged on the drift layer 2; the top of the masking layer 21 is connected to the bottom of the schottky metal layer 22, the masking layer 21 is connected to the gate insulating layer 23, the masking layer 21 is P + type, and the cross section of the masking layer 21 is that the top surface of the L-type schottky metal layer 22 is flush with the top surface of the drift layer 3;

a gate 3, wherein the gate 3 is disposed in the gate insulating layer 23;

the bottom of the source region 4 is respectively connected with the drift layer 2 and the Schottky metal layer 22, and the side surface of the source region 4 is connected with the gate insulating layer 23;

a source metal layer 5, wherein the source metal layer 5 is connected to the source region 4;

a gate metal layer 6, the gate metal layer 6 being connected to the gate 3;

and a drain metal layer 7, wherein the drain metal layer 7 is connected to the lower end face of the silicon carbide substrate 1.

As shown in fig. 2 to 11, the method for manufacturing the transistor includes the following steps:

step 1: forming a drift layer 2 on a silicon carbide substrate 1, then forming a barrier layer 24 on the drift layer 2, etching the barrier layer 24 to form a masking layer through hole, and performing ion implantation on the drift layer through the through hole to form a masking layer 21;

step 2: reforming the barrier layer 24 on the drift layer 2, and etching the barrier layer 24 and the drift layer 2 to form a gate region 25;

and step 3: oxidizing the gate region 25 and etching to form a gate insulating layer 23;

and 4, step 4: depositing a gate electrode 3 on the gate insulating layer 23;

and 5: reforming the barrier layer 24, and etching the barrier layer 24 to form a Schottky metal region deposition window;

and 6: depositing a Schottky metal layer 22;

and 7: depositing SiC material with the same concentration as the source region on the Schottky metal layer 22;

and step 8: reforming the barrier layer 24, etching the barrier layer to form a source region, and implanting ions to form a source region 4;

and step 9: depositing source region metal on the source region 4 to form a source metal layer 5;

step 10: reforming the barrier layer 24, etching a gate metal deposition area on the barrier layer, depositing to form a gate metal layer 6, and removing the barrier layer;

step 11: a drain metal layer 7 is deposited on the silicon carbide substrate 1.

The masking layer 21 is of a P + type, and the cross section of the masking layer 21 is of an L type.

The P + masking layer 21 is surrounded at the two side trench corners of the gate insulating layer 23 (typically, an oxide layer, SiO2), and the masking layer 21 reduces the electric field intensity at the trench corners of the gate dielectric, thereby improving the reliability of the gate insulating layer 23.

A schottky metal layer 22 is formed over the masking layer 21, with the schottky metal layer 22 being in contact with the masking layer 21 below and in contact with the source region 4 above and in contact with the masking layer 21 to form a gold half contact to form a schottky diode (i.e., SBD).

Between the source region 4 and the drift layer 2 a pn junction diode is formed, which together with the SBD forms a parasitic JBS.

The masking layer 21 surrounds the groove corner of the gate insulating layer 23, so that the electric field intensity of the gate oxide is effectively reduced, and the reliability of the gate oxide is improved. A schottky metal layer 22 is deposited between the source region 4 and the masking layer 21, the schottky metal layer 22 forming an ohmic contact with the source region 4 and a gold half contact with the masking layer 21 to form a low turn-on voltage schottky diode that can conduct through the JBS before the transistor is turned off, reducing body diode turn-on losses. Meanwhile, the reverse voltage-resistant characteristic of the pn junction is not lost, and high voltage-resistant characteristic can still be realized.

Although specific embodiments of the invention have been described herein, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, as equivalent modifications and variations within the spirit of the invention are intended to be covered by the appended claims.

Claims

1. A JBS-integrated trench-type SiC transistor, comprising:

a silicon carbide substrate,

the grid electrode is arranged in the grid electrode insulating layer;

a source metal layer connected to the source region;

a gate metal layer connected to the gate;

2. The JBS-integrated trench-type SiC transistor of claim 1, wherein: the masking layer is of a P + type, and the cross section of the masking layer is of an L type.