CN218274607U - Silicon carbide MOSFET for reducing gate charge - Google Patents

Abstract

The utility model provides a reduce carborundum MOSFET of grid charge includes: the drift layer is arranged on the upper side surface of the silicon carbide substrate; a groove is arranged on the drift layer, and a source region is arranged on the drift layer; the insulating layer is arranged in the groove, an insulating medium layer is arranged in the insulating layer, and a clamping groove is formed between the insulating medium layer and the insulating layer; the side wall of the insulating layer is connected with the source region; the grid polycrystalline silicon layer is arranged in the clamping groove; a source metal layer connected to the source region; a gate metal layer connected to the gate polysilicon layer; and a drain metal layer connected to an underside of the silicon carbide substrate; the high-quality insulating medium layer can effectively resist voltage, solves the problem of electric field concentration at the bottom of the traditional trench gate, increases the thickness of the insulating layer and reduces the gate capacitance.

Description

Silicon carbide MOSFET for reducing gate charge

Technical Field

The utility model relates to a reduce carborundum MOSFET of grid charge.

Background

Silicon carbide (SiC) materials for SiC devices have received much attention and research due to their excellent physical properties. The high-temperature high-power electronic device has the advantages of high input impedance, high switching speed, high working frequency, high temperature and high pressure resistance and the like, and is widely applied to the aspects of switching regulated power supplies, high-frequency heating, automobile electronics, power amplifiers and the like.

Oxidation of SiC material to prepare SiO ₂ The quality is poor, the voltage resistance is low, and the silicon dioxide grown by the method is used as a gate dielectric to meet the gate control capability, so that the electric field concentration problem at the bottom of the trench type gate is serious, and the breakdown problem of the bottom gate dielectric needs to be solved. The actual longitudinal conductive channels of the trench gate SiC MOSFET are mainly distributed on the left and right sides, the gate polysilicon inside the trench gate SiC MOSFET does not contribute to the formation of the conductive channels, and the charge distribution area is larger, which results in a slow increase in gate voltage.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model lies in providing a reduce carborundum MOSFET of bars charge, and this high quality dielectric layer can be effectively withstand voltage, concentrates the problem with the electric field of tradition slot gate bottom and solves, has increased insulating layer thickness simultaneously, has reduced the gate capacitance.

The utility model discloses a realize like this: a silicon carbide MOSFET for reducing gate charge, comprising:

a silicon carbide substrate is arranged on the substrate,

the drift layer is arranged on the upper side surface of the silicon carbide substrate; a groove is arranged on the drift layer, and a source region is arranged on the drift layer;

the insulating layer is arranged in the groove, an insulating medium layer is arranged in the insulating layer, and a clamping groove is formed between the insulating medium layer and the insulating layer; the side wall of the insulating layer is connected with the source region;

the grid polycrystalline silicon layer is arranged in the clamping groove;

a source metal layer connected to the source region;

a gate metal layer connected to the gate polysilicon layer;

and a drain metal layer connected to an underside of the silicon carbide substrate.

Furthermore, the grid polycrystalline silicon layer is in an inverted concave shape, and the insulating medium layer is in a convex shape.

Further, the insulating layer is silicon dioxide.

The utility model has the advantages that:

1. the MOSFET is of a groove type, and besides a traditional silicon dioxide insulating layer, a high-quality insulating medium layer is additionally arranged in the groove;

2. the insulating medium layer is arranged at the bottom of the trench gate, the high-quality insulating medium layer can effectively resist voltage, the problem of electric field concentration at the bottom of the traditional trench gate is solved, meanwhile, the thickness of the insulating layer is increased, and the gate capacitance is reduced;

3. according to the gate-shaped trench gate SiCMOS for reducing gate charges, the high-quality insulating dielectric layers are arranged in the trenches of the gate-shaped trench gate SiCMOS for reducing gate charges, the gates of the symmetrical source electrodes on the left side and the right side are controlled and separated, the current and the electric field are concentrated on the position where the side wall is close to the silicon dioxide insulating layer, and better gate control capability is achieved.

Drawings

The invention will be further described with reference to the following examples with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of a planar gate silicon carbide MOSFET integrated with a heterojunction diode according to the present invention.

Fig. 2 is a flow chart of a method for manufacturing a planar gate silicon carbide MOSFET integrated with a heterojunction diode according to the present invention.

Fig. 3 is a flow chart of a method for manufacturing a planar gate silicon carbide MOSFET integrated with a heterojunction diode according to the present invention.

Fig. 4 is a flow chart of a method for manufacturing a planar gate silicon carbide MOSFET integrated with a heterojunction diode according to the present invention.

Fig. 5 is a fourth flowchart illustrating a method of fabricating a planar gate silicon carbide MOSFET integrated with a heterojunction diode according to the present invention.

Fig. 6 is a flow chart of a method for manufacturing a planar gate silicon carbide MOSFET integrated with a heterojunction diode according to the present invention.

Fig. 7 is a flow chart of a method of fabricating a heterojunction diode integrated planar gate silicon carbide MOSFET of the present invention.

Fig. 8 is a flow chart of a method for manufacturing a planar gate silicon carbide MOSFET integrated with a heterojunction diode according to the present invention.

Fig. 9 is a flow chart of a method eight of fabricating a planar gate silicon carbide MOSFET integrated with a heterojunction diode according to the present invention.

Fig. 10 is a flow chart of a method for fabricating a planar gate silicon carbide MOSFET integrated with a heterojunction diode according to the present invention.

Detailed Description

As shown in fig. 1, the present invention provides a silicon carbide MOSFET for reducing gate charge, comprising:

a silicon carbide substrate (1) having a silicon carbide,

the drift layer 2 is arranged on the upper side surface of the silicon carbide substrate 1; a groove 21 is arranged on the drift layer 2, and a source region 22 is arranged on the drift layer 2;

the insulating layer 3 is arranged in the groove 21, an insulating medium layer 31 is arranged in the insulating layer 3, and a clamping groove 32 is formed between the insulating medium layer 31 and the insulating layer 3; the side wall of the insulating layer 3 is connected with the source region 22, the insulating medium layer 31 is in a convex shape, and the insulating layer 3 is made of silicon dioxide;

the grid polycrystalline silicon layer 4 is arranged in the clamping groove 32, and the grid polycrystalline silicon layer 4 is in an inverted concave shape;

the source metal layer 5, the source metal layer 5 is connected to the source region 22, the source metal layer 5 can also be connected to the drift layer 2, and the conductive area is increased;

a gate metal layer 6, the gate metal layer 6 being connected to the gate polysilicon layer 5;

and a drain metal layer 7, the drain metal layer 7 being connected to the lower side face of the silicon carbide substrate 1.

The MOSFET is of a trench type, a high-quality insulating medium layer 31 is additionally arranged in the trench except a traditional silicon dioxide insulating layer 3, the insulating medium layer 31 is generated by deposition, the quality is higher, the reliability of a grid metal layer 6 is improved, the high-quality insulating medium layer 31 can effectively resist voltage, the problem of electric field concentration at the bottom of a traditional trench grid is solved, the thickness of the insulating layer is increased, and the grid capacitance is reduced.

The insulating medium layer 31 increases the thickness of a voltage-resistant layer at the bottom of the trench type gate, and increases the thickness of a bottom insulating layer, so that the bottom capacitance of the trench type gate becomes small, the electric field becomes weak, and the problem of electric field concentration is structurally reduced.

The gate control of the symmetrical source electrodes 22 at the left side and the right side is separated through the high-quality insulating medium layer 31 and the insulating layer 3, the current and the electric field are concentrated at the position of the side wall close to the silicon dioxide insulating layer, and better gate control capability is realized; the high-quality insulating dielectric layer 31 increases the control capability of the trench-type gate, and the high-quality insulating dielectric at the bottom reduces the problem of electric field concentration at the bottom and also reduces the parasitic capacitance of the gate.

As shown in fig. 1 to 10, the method for manufacturing the MOSFET includes the following steps:

step 1, forming a barrier layer a on a drift layer 2 of a silicon carbide substrate 1, etching the barrier layer a to form a through hole, and etching the drift layer 2 through the through hole to form a groove 21;

step 2, oxidizing the groove 21 to form an insulating layer 3, wherein the insulating layer 3 is silicon dioxide;

step 3, depositing an insulating medium layer 31 in the insulating layer 3, wherein the insulating medium layer 31 is in a convex shape;

step 4, forming a barrier layer a on the drift layer 2 again, and etching the barrier layer a to form a through hole to form a clamping groove 32;

step 5, depositing polycrystalline silicon on the clamping groove 32 to form a grid polycrystalline silicon layer 4, wherein the grid polycrystalline silicon layer 4 is in an inverted concave shape;

step 6, forming a barrier layer a on the drift layer 2 again, etching the barrier layer a to form a through hole, and performing ion implantation to form a source region 22;

step 7, forming a barrier layer a on the drift layer 2 again, etching the barrier layer a to form a through hole, depositing metal, and forming a source metal layer 5;

step 8, forming a barrier layer a on the drift layer 2 again, etching the barrier layer a to form a through hole, depositing metal and forming a grid metal layer 6;

and 9, removing all the barrier layers a, and depositing metal on the silicon carbide substrate 1 to form a drain metal layer 7.

Although specific embodiments of the present invention have been described, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the claims appended hereto.

Claims (3)

1. A silicon carbide MOSFET for reducing gate charge, comprising:

a silicon carbide substrate is arranged on the substrate,

the drift layer is arranged on the upper side face of the silicon carbide substrate; a groove is arranged on the drift layer, and a source region is arranged on the drift layer;

the insulating layer is arranged in the groove, an insulating medium layer is arranged in the insulating layer, and a clamping groove is formed between the insulating medium layer and the insulating layer; the side wall of the insulating layer is connected with the source region;

the grid polycrystalline silicon layer is arranged in the clamping groove;

a source metal layer connected to the source region;

a gate metal layer connected to the gate polysilicon layer;

and a drain metal layer connected to an underside of the silicon carbide substrate.

2. The silicon carbide MOSFET of claim 1, wherein the gate polysilicon layer is inverted-concave and the insulating dielectric layer is convex.

3. The silicon carbide MOSFET of claim 1, wherein the insulating layer is silicon dioxide.

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