CN115831758A

CN115831758A - Manufacturing method of silicon carbide UMOSFET integrated with Schottky

Info

Publication number: CN115831758A
Application number: CN202310104836.5A
Authority: CN
Inventors: 李昀佶; 张长沙; 李佳帅; 何佳
Original assignee: Global Power Technology Co Ltd
Current assignee: Global Power Technology Co Ltd
Priority date: 2023-02-13
Filing date: 2023-02-13
Publication date: 2023-03-21

Abstract

The invention provides a manufacturing method of integrated Schottky silicon carbide UMOSFET, which comprises the following steps: forming a barrier layer on the drift layer of the silicon carbide substrate, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer through the through hole to form a masking layer; reforming the barrier layer, and etching the barrier layer and the drift layer to form a groove; oxidizing the groove to form an insulating layer; depositing in the insulating layer to form a grid; forming a barrier layer again, etching, and performing ion implantation to form a source region; reforming the barrier layer, etching, depositing metal and forming a Schottky metal layer; reforming the barrier layer, etching, depositing metal and forming a source metal layer; reforming the barrier layer, etching the barrier layer to form a through hole, depositing metal on the grid electrode to form a grid electrode metal layer; removing the barrier layer, and depositing metal on the silicon carbide substrate to form a drain metal layer; the electric field intensity of the grid electrode of the part is reduced, the problem of grid breakdown is solved, and the reverse recovery characteristic and the follow current characteristic are optimized.

Description

Manufacturing method of silicon carbide UMOSFET integrated with Schottky

Technical Field

The invention relates to a manufacturing method of a silicon carbide UMOSFET integrated with Schottky.

Background

Silicon carbide (SiC) materials for SiC devices have received much attention and research due to their excellent physical properties. The main application fields include the aspects of switching regulated power supplies, high-frequency heating, automobile electronics, power amplifiers and the like.

However, because the gate critical breakdown field strength of the silicon carbide VDMOS device is extremely high and the gate oxide quality is relatively poor, in the trench gate type silicon carbide MOSFET, the gate oxide is easily broken down, and particularly, at the trench corners, the electric field is concentrated and the electric field strength is extremely high, so that the problem of the overlarge electric field strength at the trench corners needs to be solved. Meanwhile, in practical application, the body diode always has a freewheeling condition, while the body diode of the traditional device has a high starting voltage due to the characteristics of the SiC material, so that large loss is caused.

Disclosure of Invention

The invention aims to provide a manufacturing method of a Schottky integrated silicon carbide UMOSFET, which reduces the electric field intensity of a grid electrode of the Schottky integrated silicon carbide UMOSFET, solves the problem of grid breakdown and optimizes reverse recovery characteristics and follow current characteristics.

The invention is realized by the following steps: a manufacturing method of integrated Schottky silicon carbide UMOSFET specifically comprises the following steps:

step 1, forming a barrier layer on a drift layer of a silicon carbide substrate, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer through the through hole to form a masking layer;

step 2, forming a barrier layer on the drift layer again, and etching the barrier layer and the drift layer to form a groove;

step 3, oxidizing the groove to form an insulating layer, wherein the insulating layer is in a shape of a Chinese character 'ao';

step 4, depositing in the insulating layer to form a grid;

step 5, forming the barrier layer again, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer to form a source region;

step 6, forming the barrier layer again, etching the barrier layer to form a through hole, depositing metal on the drift layer to form a Schottky metal layer;

step 7, forming the barrier layer again, etching the barrier layer to form a through hole, depositing metal on the source region, and forming a source metal layer;

step 8, forming the barrier layer again, etching the barrier layer to form a through hole, depositing metal on the grid electrode to form a grid electrode metal layer;

and 9, removing the barrier layer, and depositing metal on the silicon carbide substrate to form a drain metal layer.

Further, the masking layer is in a shape of Chinese character 'ao', and the step 2 specifically includes: and reforming the barrier layer on the drift layer, and etching the barrier layer, the drift layer and the masking layer to form a trench.

The invention has the advantages that:

the UMOSFET builds a masking layer below the grid, and the masking layer wraps the lower part and the lower corner of the grid junction insulating layer, so that the electric field intensity of the grid of the part can be reduced, and the grid breakdown problem is solved;

a parasitic Schottky diode is constructed on a source electrode of the UMOSFET, the metal of the parasitic diode and the metal of the source electrode are made of the same material and can be connected together, a Schottky metal layer of the integrated Schottky UMOSFET is arranged on the periphery of a device and is far away from a grid metal layer, the normal conduction characteristic of the device is not affected, only the Schottky metal layer is added, and the reverse recovery characteristic and the follow current characteristic are optimized.

Drawings

The invention will be further described with reference to the following examples with reference to the accompanying drawings.

Fig. 1 is a first flow chart of a method of fabricating an integrated schottky silicon carbide UMOSFET in accordance with the present invention.

Fig. 2 is a flow chart of a method of fabricating an integrated schottky silicon carbide UMOSFET according to the present invention.

Fig. 3 is a flow chart three of a method for fabricating an integrated schottky silicon carbide UMOSFET in accordance with the present invention.

Fig. 4 is a flow chart of a method of fabricating an integrated schottky silicon carbide UMOSFET of the present invention.

Fig. 5 is a flow chart of a method of fabricating an integrated schottky silicon carbide UMOSFET in accordance with the present invention.

Fig. 6 is a flow chart of a method of fabricating an integrated schottky silicon carbide UMOSFET in accordance with the present invention.

Fig. 7 is a flow chart seven of a method of fabricating an integrated schottky silicon carbide UMOSFET in accordance with the present invention.

Fig. 8 is a flow chart eight of a method of fabricating an integrated schottky silicon carbide UMOSFET in accordance with the present invention.

Fig. 9 is a schematic diagram of an integrated schottky silicon carbide UMOSFET of the present invention.

Description of the preferred embodiment

Referring to fig. 1 to 9, a method for manufacturing a schottky-integrated silicon carbide UMOSFET specifically includes the following steps:

step 1, forming a barrier layer a on a drift layer 2 of a silicon carbide substrate 1, etching the barrier layer a to form a through hole, performing ion implantation on the drift layer 2 through the through hole to form a masking layer 21, and directly forming the masking layer 21 in the drift layer 2 by controlling the energy of the ion implantation;

step 2, forming a barrier layer a on the drift layer 2 again, and etching the barrier layer a, the drift layer 2 and the masking layer 21 to form a groove 23, wherein the masking layer 21 is in a shape of Chinese character 'ao';

step 3, oxidizing the groove 23 to form an insulating layer 3, wherein the insulating layer 3 is in a shape of a Chinese character 'ao';

step 4, depositing polysilicon in the insulating layer 3 to form a gate 31;

step 5, forming the barrier layer a again, etching the barrier layer a to form a through hole, and performing ion implantation on the drift layer 2 to form a source region 22;

step 6, forming the barrier layer a again, etching the barrier layer a to form a through hole, depositing metal on the drift layer 2, and forming the Schottky metal layer 4;

step 7, forming the barrier layer a again, etching the barrier layer a to form a through hole, depositing metal on the source region 22, and forming a source metal layer 5;

step 8, forming a barrier layer a again, etching the barrier layer a to form a through hole, depositing metal on the grid 31, and forming a grid metal layer 6;

and 9, removing the barrier layer a, and depositing metal on the silicon carbide substrate 1 to form a drain metal layer 7.

Referring to fig. 9, the structure of the UMOSFET includes:

a silicon carbide substrate 1;

the drift layer 2 is provided with the upper side surface of the silicon carbide substrate 1; a masking layer 21, a source region 22 and a trench 23 are arranged on the drift layer 2, the trench 23 is arranged above the masking layer 21, and the masking layer 21 is in a shape of a Chinese character 'ao';

the insulating layer 3 is arranged in the groove 23, the bottom of the insulating layer 3 is connected to the masking layer 21, the side wall of the insulating layer 3 is connected to the source region 22, and a grid electrode 31 is arranged in the insulating layer 3;

a Schottky metal layer 4, wherein the bottom of the Schottky metal layer 4 is connected to the drift layer 2;

a source metal layer 5, wherein the bottom of the source metal layer 5 is connected to the source region 22;

a gate metal layer 6, the gate metal layer 6 being connected to the gate 31;

and a drain metal layer 7, the drain metal layer 7 being connected to the lower side of the silicon carbide substrate 1.

The P + masking layer 21 is surrounded under the insulating layer (generally, an oxide layer, siO 2) and at the left and right groove corners, the masking layer 21 reduces the electric field intensity of the gate dielectric at the groove corners and the bottom of the gate dielectric, the reliability of the insulating layer 3 is improved, and the schottky metal layer 4 is arranged to realize the parasitic of the schottky diode; the source region 22 and the drift layer 2 are respectively arranged below the source metal layer 5 and the Schottky metal layer 4, the parasitic Schottky diode is arranged on the periphery of the device and is far away from the grid metal layer 6, the conductive channel around the grid metal layer 6 is not affected, the normal conduction characteristic of the device is not affected, only the parasitic Schottky diode is added, and the reverse recovery characteristic and the follow current characteristic are optimized. The parasitic Schottky diode has reduced on-voltage and improved follow current characteristics. The reverse recovery is caused by carriers, and the Schottky contact has only one type of carriers, so that the reverse recovery characteristic is improved.

Although specific embodiments of the invention have been described above, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the appended claims.

Claims

1. A manufacturing method of integrated Schottky silicon carbide UMOSFET is characterized by comprising the following steps:

step 4, depositing in the insulating layer to form a grid;

2. The method for manufacturing the integrated schottky sic UMOSFET of claim 1, wherein the masking layer is in a shape of a Chinese character 'ao', and the step 2 specifically comprises: and reforming the barrier layer on the drift layer, and etching the barrier layer, the drift layer and the masking layer to form a trench.