CN109461774B - HEMT device containing high dielectric coefficient dielectric block - Google Patents
HEMT device containing high dielectric coefficient dielectric block Download PDFInfo
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- CN109461774B CN109461774B CN201811293318.8A CN201811293318A CN109461774B CN 109461774 B CN109461774 B CN 109461774B CN 201811293318 A CN201811293318 A CN 201811293318A CN 109461774 B CN109461774 B CN 109461774B
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- 230000004888 barrier function Effects 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000005684 electric field Effects 0.000 description 14
- 229910002704 AlGaN Inorganic materials 0.000 description 11
- 230000005533 two-dimensional electron gas Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 239000004047 hole gas Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000779 depleting effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
Abstract
An HEMT device containing a high dielectric coefficient dielectric block belongs to the technical field of semiconductors. The two-dimensional conductive channel is formed at the interface between the barrier layer and the buffer layer; the source electrode and the drain electrode are respectively arranged on two sides of the HEMT device and are in ohmic contact with the two-dimensional conductive channel; a grid electrode is arranged between the source electrode and the drain electrode, and the grid electrode is positioned on the barrier layer and forms Schottky contact with the barrier layer; the area between the grid and the drain on the barrier layer is provided with a plurality of high dielectric coefficient dielectric blocks, the high dielectric coefficient dielectric blocks are respectively connected with the grid and extend along the grid leakage direction, the grid and the high dielectric coefficient dielectric blocks form a comb-finger-shaped structure, the high dielectric coefficient dielectric blocks are not directly connected with the drain, and the dielectric coefficient of the high dielectric coefficient dielectric blocks is larger than that of the barrier layer. The HEMT device provided by the invention has the characteristic of high breakdown voltage, and can meet the application of high working voltage and output power.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a High Electron Mobility Transistor (HEMT), in particular to a HEMT device containing a high dielectric coefficient dielectric block.
Background
In the field of radio frequency and power integrated circuits, the frequency, voltage resistance, on-resistance and other characteristics of devices are important performance indexes for determining circuit characteristics, and at present, along with the continuous improvement of the integration level of power integrated circuits, the requirements of the power integrated circuits on various characteristics of circuits and devices are higher and higher. In a radio frequency power device, because an HEMT (high electron mobility transistor) device has the characteristics of ultra high speed, low power consumption and low noise (especially at low temperature) compared with other power devices, the HEMT device greatly meets special requirements on applications such as ultra high speed computers, signal processing, satellite communication and the like, and thus the HEMT device is widely regarded.
The rapid development of radio frequency and power integrated circuits also increasingly requires power devices capable of meeting higher frequency and larger voltage withstanding characteristics. As a new generation of microwave and millimeter wave devices, HEMT devices exhibit unparalleled advantages in terms of frequency, gain, and efficiency. After more than 10 years of development, HEMTs have excellent microwave and millimeter wave characteristics, and have become the main devices of microwave and millimeter wave low noise amplifiers in the fields of satellite communication, radio astronomy, electronic strategy and the like of 2-100 GHz. For a conventional HEMT device, a schematic perspective structure of the HEMT device is shown in fig. 1, and a buffer layer and a barrier layer are sequentially arranged from a substrate to the top, and the buffer layer and the barrier layer form two-dimensional electron gas or two-dimensional hole gas. Wherein the grid electrode is positioned above the barrier layer to form a Schottky contact with the barrier layer, and the source electrode and the drain electrode form ohmic contact with the two-dimensional electron gas or the two-dimensional hole gas in the heterojunction 4. The HEMT controls current by controlling the concentration of a two-dimensional electron gas or a two-dimensional hole gas in a heterojunction through a schottky barrier under a gate. Since the two-dimensional electron gas or the two-dimensional hole gas is spatially separated from the impurity center in the barrier layer, it is not affected by scattering of ionized impurities, and thus its mobility is high. However, in the device operating state, since the electric field distribution between the gate and the drain is concentrated, an electric field peak is easily generated in this region, thereby causing a decrease in breakdown electric field, limiting the maximum output power of the HEMT device.
Disclosure of Invention
Aiming at the defect of low breakdown voltage of the traditional HEMT, the invention provides the HEMT device containing the high-dielectric-coefficient dielectric block, which can effectively improve the breakdown voltage of the HEMT device, so that the HEMT device provided by the invention can meet the application of higher working voltage and output power.
The technical scheme of the invention is as follows:
an HEMT device containing a high dielectric coefficient dielectric block comprises a substrate 1, a buffer layer 2, a barrier layer 3, a grid 4, a source 5 and a drain 6, wherein the buffer layer 2 and the barrier layer 3 are sequentially arranged on the substrate 1, and a two-dimensional conductive channel 9 is formed at the contact interface of the barrier layer 3 and the buffer layer 2;
the source electrode 5 and the drain electrode 6 are respectively arranged on two sides of the HEMT device and form ohmic contact with the two-dimensional conducting channel 9;
the grid electrode 4 is arranged between the source electrode 5 and the drain electrode 6, and the grid electrode 4 is positioned on the barrier layer 3 and forms Schottky contact with the barrier layer 3;
a plurality of high-dielectric-coefficient dielectric blocks 7 are arranged in the region, located between the grid 4 and the drain 6, of the barrier layer 3, the high-dielectric-coefficient dielectric blocks 7 are respectively connected with the grid 4 and extend along the grid leakage direction, the grid 4 and the high-dielectric-coefficient dielectric blocks 7 form a comb-finger-shaped structure, the high-dielectric-coefficient dielectric blocks 7 are not in direct contact with the drain 6, and the dielectric coefficient of the high-dielectric-coefficient dielectric blocks 7 is larger than that of the barrier layer 3.
Specifically, the insulating medium 8 is filled between the plurality of high-permittivity medium blocks 7.
Specifically, the high-k dielectric block 7 is connected to the gate 4 through a dielectric layer.
Specifically, the insulating medium 8 extends towards the drain electrode 6, and the region between the high-permittivity dielectric block 7 and the drain electrode 6 is partially or completely filled with the insulating medium 8.
The working principle of the invention is as follows:
because the electric field lines always tend to pass through the material with higher dielectric constant, and the dielectric constant of the high-dielectric-coefficient dielectric block 7 is larger than that of the barrier layer 3, when higher leakage voltage is applied to the HEMT device, a large number of electric field lines enter the high-dielectric-coefficient dielectric block 7 from the barrier layer 3, a large number of interface negative charges are induced at the interface between the barrier layer 3 and the high-dielectric-coefficient dielectric block 7 by the interface electric field, and the interface negative charges have depletion effect on the channel two-dimensional electron gas in the two-dimensional conductive channel 9; and because the interface negative charge surface density can be increased along with the increase of the drain voltage, the two-dimensional electron gas below the interface negative charge surface density is gradually depleted to form a depletion region, and the newly formed depletion region can be used as a voltage-withstanding region to play a role in improving the breakdown voltage.
The invention has the beneficial effects that: the HEMT device provided by the invention has the characteristic of high breakdown voltage, and can meet the application of high working voltage and output power; meanwhile, the capacitor has the characteristics of small on-resistance and small introduced additional capacitance; the drain voltage of the invention has little influence on the electric field distribution near the drain.
Drawings
Fig. 1 is a schematic perspective view of a conventional HEMT device.
Fig. 2 is a schematic diagram of an implementation structure of a HEMT device including high-k dielectric blocks according to the present invention, in which a plurality of high-k dielectric blocks 7 are uniformly distributed and extend along a gate-drain direction.
Fig. 3 is a schematic diagram of an implementation structure of the HEMT device including the high-k dielectric blocks according to the present invention, in which insulating dielectrics 8 are filled between the high-k dielectric blocks 7.
Fig. 4 is a schematic diagram of an implementation structure of the HEMT device including the high-k dielectric block according to the present invention, in which the insulating dielectric 8 extends toward the drain 6 without contacting the drain 6.
Fig. 5 is a schematic diagram of an implementation structure of the HEMT device including the high-k dielectric block according to the present invention, in which the insulating dielectric 8 extends toward the drain 6 and contacts the drain 6.
Fig. 6 is a schematic perspective view of a depletion region formed below a plurality of high-k dielectric blocks 7 in an HEMT device according to the present invention.
Fig. 7 is a schematic perspective view of a lateral expansion of depletion regions under a plurality of high-k dielectric blocks 7 in an HEMT device according to the present invention.
Fig. 8 is a cross-sectional view of forming a GaN buffer layer 10 over a substrate 1 in an embodiment.
Fig. 9 is a cross-sectional view of an AlGaN barrier layer 11 formed over the GaN buffer layer 10 in the embodiment.
Fig. 10 is a cross-sectional view of the source electrode 5 and the drain electrode 6 formed in ohmic contact with the GaN buffer layer 10 in the example.
Fig. 11 is a cross-sectional view of the gate 4 formed over the AlGaN barrier layer 11 in this embodiment.
Fig. 12 is a schematic perspective view of an embodiment in which a high-k dielectric is covered on the AlGaN barrier layer 11 in the region between the gate 4 and the drain 6.
FIG. 13 is a schematic perspective view of the embodiment in which a plurality of high-k dielectric blocks 7 are formed by etching a high-k dielectric.
Reference numerals: the dielectric constant-temperature-resistant GaN-based high-k dielectric material comprises a substrate 1, a buffer layer 2, a barrier layer 3, a grid 4, a source electrode 5, a drain electrode 6, a dielectric block with a high dielectric coefficient 7, an insulating dielectric 8, a two-dimensional conductive channel 9, a GaN buffer layer 10 and an AlGaN barrier layer 11.
Detailed Description
The technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.
The invention provides a HEMT device containing a high dielectric coefficient dielectric block, which comprises a substrate 1, a buffer layer 2, a barrier layer 3, a grid 4, a source 5 and a drain 6, wherein the buffer layer 2 and the barrier layer 3 are sequentially arranged on the substrate 1, and a two-dimensional conductive channel 9 is formed at the contact interface of the barrier layer 3 and the buffer layer 2; the source electrode 5 and the drain electrode 6 are respectively arranged on two sides of the HEMT device and form ohmic contact with the two-dimensional conductive channel 9; a grid 4 is arranged between the source 5 and the drain 6, and the grid 4 is positioned on the barrier layer 3 and forms Schottky contact with the barrier layer 3; a plurality of high-permittivity dielectric blocks 7 are arranged in a region, located between the gate 4 and the drain 6, of the barrier layer 3, one end of each high-permittivity dielectric block 7 is connected with the gate 4, the other end of each high-permittivity dielectric block 7 extends in the gate-drain direction, and the plurality of high-permittivity dielectric blocks 7 and the gate 4 form a comb-finger-shaped structure, as shown in fig. 2, wherein the connection mode of the high-permittivity dielectric blocks 7 and the gate 4 includes direct connection or indirect connection through a thin dielectric layer.
The permittivity of the high permittivity dielectric block 7 needs to be larger than the permittivity of the barrier layer 3 so that the electric field lines in the barrier layer 3 can enter the high permittivity dielectric block 7. And because the plurality of high-permittivity dielectric blocks 7 and the grid electrode 4 form a comb-finger structure, the high-permittivity dielectric blocks 7 do not completely cover the whole area between the grid electrode 4 and the drain electrode 6 above the barrier layer 3, so that the uncovered area is not influenced by the high-permittivity dielectric blocks 7, the on-resistance is reduced, and the introduced additional capacitance is reduced.
In some embodiments, the plurality of high-k dielectric blocks 7 may be filled with an insulating dielectric 8, as shown in fig. 3, the insulating dielectric 8 may be connected to the gate 4 directly or through a thin dielectric layer; the insulating dielectric 8 may extend in the direction of the drain 6, as shown in fig. 4 and 5; the high-k dielectric block 7 is not directly connected with the drain electrode 6, no dielectric may be disposed between the high-k dielectric block 7 and the drain electrode 6 as shown in fig. 2 or the extended insulating dielectric 8 may not contact the drain electrode 6 as shown in fig. 4, or the insulating dielectric 8 may be extended to be connected with the drain electrode 6 as shown in fig. 5 so that the high-k dielectric block 7 and the drain electrode 6 are indirectly connected through the insulating dielectric 8; since the high-k dielectric block 7 is not in direct contact with the drain 6, the influence of the drain 6 on the electric field distribution in the vicinity of the drain 6 can be reduced.
The operation of the present invention will be described in detail with reference to fig. 6 and 7.
For a conventional HEMT device, when a high voltage is applied to the drain, the voltage drops mainly near the gate edge due to the difficulty of fully depleting the drift region between the gate and drain, which results in a large electric field peak causing the device to break down.
Because the high-dielectric-coefficient dielectric block 7 is arranged between the grid 4 and the drain 6, the dielectric coefficient of the high-dielectric-coefficient dielectric block 7 is larger than that of the barrier layer 3, and electric field lines always tend to penetrate through a material with a higher dielectric constant, when a drain of the HEMT device provided by the invention applies higher leakage voltage, a large number of electric field lines enter the high-dielectric-coefficient dielectric block 7 from the barrier layer 3, a large number of interface negative charges are induced at the interface of the two layers of materials, namely the barrier layer 3 and the high-dielectric-coefficient dielectric block 7, by the interface electric field, and the negative charges can exhaust two-dimensional electron gas in a channel.
And the interface negative charge surface density is increased along with the increase of the leakage voltage, so that the two-dimensional electron gas below the high-dielectric-coefficient dielectric block 7 is gradually depleted to form a depletion layer, as shown in FIG. 6. When the drain voltage is sufficiently high, the depletion regions below the respective high-k dielectric blocks 7 laterally expand, so that the two-dimensional electron gas below the regions between the respective high-k dielectric blocks 7 is also depleted, and thus the depletion regions below the respective high-k dielectric blocks 7 are connected into one piece to form a large depletion region having an approximately rectangular shape, as shown in fig. 7. The newly formed depletion region can play a role of a voltage-resistant region, and the voltage which is originally concentrated and falls on the edge of the grid electrode is greatly expanded due to the direct or indirect connection of the high-dielectric-coefficient dielectric block 7 and the grid electrode 3, so that the electric field peak of a drift region between grid electrodes and drain electrodes is effectively inhibited, the breakdown voltage of the device is improved, and the voltage resistance of the device is greatly improved.
As shown in fig. 8 to 13, a method for manufacturing a HEMT device of the present invention is provided, and this embodiment will describe in detail a manufacturing process of a GaN-based HEMT device in this embodiment, taking a GaN-based HEMT device not filled with an insulating medium 8 as an example, with reference to the accompanying drawings, and includes the following steps:
And 3, performing mesa etching to manufacture an active region of the device, then preparing a source electrode 5 and a drain electrode 6 on the surface of the mesa, and enabling the source electrode 5 and the drain electrode 6 to form ohmic contact with the two-dimensional conductive channel 9 at the interface of the GaN buffer layer 10 and the AlGaN barrier layer 11 respectively, as shown in FIG. 10.
And 6, carrying out graphical etching on the high-dielectric-coefficient dielectric blocks 7 to the surface of the AlGaN barrier layer 11, so that a plurality of high-dielectric-coefficient dielectric blocks 7 which are uniformly distributed and extend along the gate-drain direction are formed above the AlGaN barrier layer 11, the high-dielectric-coefficient dielectric blocks 7 are not directly connected with the drain electrode 6, and the subsequent process is consistent with the conventional HEMT manufacturing process, thereby finally obtaining the GaN-based HEMT device of the embodiment, as shown in FIG. 13.
Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (3)
1. An HEMT device containing a high dielectric coefficient dielectric block comprises a substrate (1), a buffer layer (2), a barrier layer (3), a grid (4), a source electrode (5) and a drain electrode (6), wherein the buffer layer (2) and the barrier layer (3) are sequentially arranged on the substrate (1), and a two-dimensional conductive channel (9) is formed at the contact interface of the barrier layer (3) and the buffer layer (2);
the source electrode (5) and the drain electrode (6) are respectively arranged on two sides of the HEMT device and are in ohmic contact with the two-dimensional conducting channel (9);
the grid electrode (4) is arranged between the source electrode (5) and the drain electrode (6), and the grid electrode (4) is positioned on the barrier layer (3) and forms Schottky contact with the barrier layer (3);
the grid-connected type high-dielectric-coefficient capacitor is characterized in that a plurality of high-dielectric-coefficient dielectric blocks (7) are arranged in a region, located between a grid (4) and a drain (6), on the barrier layer (3), the high-dielectric-coefficient dielectric blocks (7) are respectively connected with the grid (4) and extend along the grid leakage direction, the grid (4) and the high-dielectric-coefficient dielectric blocks (7) form a comb-finger-shaped structure, the high-dielectric-coefficient dielectric blocks (7) are not in direct contact with the drain (6), and the dielectric coefficient of the high-dielectric-coefficient dielectric blocks (7) is larger than that of the barrier layer (3).
2. The HEMT device with high-k dielectric blocks according to claim 1, wherein said plurality of high-k dielectric blocks (7) are filled with an insulating dielectric (8).
3. The HEMT device with a high-k dielectric block according to claim 2, wherein said insulating dielectric (8) extends in the direction of said drain (6), the region between said high-k dielectric block (7) and the drain (6) being partially or completely filled with the insulating dielectric (8).
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| CN201811293318.8A CN109461774B (en) | 2018-11-01 | 2018-11-01 | HEMT device containing high dielectric coefficient dielectric block |
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| CN201811293318.8A CN109461774B (en) | 2018-11-01 | 2018-11-01 | HEMT device containing high dielectric coefficient dielectric block |
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| CN110071172B (en) * | 2019-04-28 | 2022-03-18 | 苏州汉骅半导体有限公司 | Semiconductor device and method for manufacturing the same |
| CN110660851A (en) * | 2019-10-08 | 2020-01-07 | 电子科技大学 | High-voltage n-channel HEMT device |
| CN110649097B (en) * | 2019-10-08 | 2021-04-02 | 电子科技大学 | High-voltage p-channel HFET device |
| CN110649096B (en) * | 2019-10-08 | 2021-06-04 | 电子科技大学 | High-voltage n-channel HEMT device |
| CN110660843A (en) * | 2019-10-08 | 2020-01-07 | 电子科技大学 | High-voltage p-channel HEMT device |
| CN113257910B (en) * | 2021-05-11 | 2023-01-03 | 华南师范大学 | Comb-type gate structure HEMT radio frequency device and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101017854A (en) * | 2006-12-31 | 2007-08-15 | 电子科技大学 | GaN base transistor with high electronic transfer rate |
| CN105185827A (en) * | 2015-09-08 | 2015-12-23 | 东南大学 | AlGaN/GaN high-electron-mobility power semiconductor device |
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| US7566917B2 (en) * | 2004-09-28 | 2009-07-28 | Sharp Kabushiki Kaisha | Electronic device and heterojunction FET |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101017854A (en) * | 2006-12-31 | 2007-08-15 | 电子科技大学 | GaN base transistor with high electronic transfer rate |
| CN105185827A (en) * | 2015-09-08 | 2015-12-23 | 东南大学 | AlGaN/GaN high-electron-mobility power semiconductor device |
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