CN105161533A - Silicon carbide VDMOS device and manufacturing method - Google Patents
Silicon carbide VDMOS device and manufacturing method Download PDFInfo
- Publication number
- CN105161533A CN105161533A CN201510388838.7A CN201510388838A CN105161533A CN 105161533 A CN105161533 A CN 105161533A CN 201510388838 A CN201510388838 A CN 201510388838A CN 105161533 A CN105161533 A CN 105161533A
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- pbase
- contact zone
- source region
- upper strata
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 44
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 238000005516 engineering process Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- 229920005591 polysilicon Polymers 0.000 claims description 22
- 239000012535 impurity Substances 0.000 claims description 21
- 238000005468 ion implantation Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 238000000407 epitaxy Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 11
- 230000005684 electric field Effects 0.000 abstract description 9
- 239000000377 silicon dioxide Substances 0.000 abstract description 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 9
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Abstract
The invention belongs to the semiconductor technology and particularly relates to a silicon carbide VDMOS device and a manufacturing method. The silicon carbide VDMOS device comprises a silicon carbide N type heavily-doped substrate, a silicon carbide N-epitaxial layer above the silicon carbide N type heavily-doped substrate, Pbase regions arranged at the upper portion of the silicon carbide N-epitaxial layer, a source electrode formed by a silicon carbide P+ contact region in the Pbase regions and an N+ source region, groove poly-silicon in a JFET region denting between the Pbase regions, a silicon dioxide medium denting between the poly-silicon in the JFET region and a semi-conductor, and a P+ region surrounding periphery of the silicon dioxide medium in the JFET region. According to the silicon carbide VDMOS device, a groove gate is arranged, a gate-oxide electric field is optimized, and reliability of the device is improved.
Description
Technical field
The invention belongs to power semiconductor technologies, relate to vertical DMOS field-effect transistor (VDMOSFET) device architecture specifically, especially a kind of high reliability carborundum VDMOS device and preparation method thereof.
Background technology
Carborundum (SiliconCarbide) material relies on the features such as critical breakdown electric field is high, thermal conductivity is high, hot carrier saturation drift velocity is high, Radiation hardness is strong, greatly extend the energy-handling capability of power device, meet that power electronics of future generation equipment is more high-power to power device, more small size and the requirement that more works under mal-condition, be just progressively applied to various power electronic system field.
Compared with the semiconductor material with wide forbidden band such as gallium nitride (GaN), SiC material can directly generate silicon dioxide (SiO by thermal oxidation
2), this advantage makes SiC become the ideal material making high-power MOSFET device.But, SiC/SiO
2interface charge compare Si/SiO
2approximately high two orders of magnitude, especially SiC-SiO
2interface, near the high interface state density of conduction band edge, can make MOSFET channel electron mobility very low.In addition, because SiC is compared to SiO
2have higher dielectric constant, according to the continuity of electric displacement vector, the electric field in gate medium silicon dioxide is about 2.5 times in carborundum.For carborundum VDMOS device, device is critical puncture time, JFET district can reach 1.5-2MV/cm usually near the electric field strength of grid oxygen, therefore, electric field strength in gate oxide will be easy to reach the minimum electric field affecting grid oxygen reliability, thus cause semi-conducting material and grid metal to inject electronics to gate medium, produce Fowler-Nordheim (FN) tunnelling current, cause becoming during medium puncturing (time-dependentdielectric-breakdown, TDDB), carborundum VDMOS device is made to face very serious gate medium integrity problem.
Summary of the invention
To be solved by this invention, be exactly for the problems referred to above, propose a kind of high reliability carborundum VDMOS device and preparation method thereof.
For achieving the above object, the present invention adopts following technical scheme:
A kind of carborundum VDMOS device, as shown in Figure 2, comprise set gradually from bottom to top metal leakage pole 11, N
+substrate 10 and N
-epitaxial loayer 9; Described N
-one end, epitaxial loayer 9 upper strata has a Pbase district 7, and its upper strata other end has the 2nd Pbase district 71; In a described Pbase district 7, there is a separate N
+source region 6 and a P
+contact zone 5; In described 2nd Pbase district 71, there is the 2nd separate N
+source region 61 and the 2nd P
+contact zone 51; A described N
+source region 6 and a P
+contact zone 5 upper surface has the first metal source 3; Described 2nd N
+source region 61 and the 2nd P
+contact zone 51 upper surface has the second metal source 31; Between described first metal source 3 and the second metal source 31, there is grid structure; Described grid structure is made up of gate oxide 4, the polysilicon gate 2 being positioned at gate oxide 4 upper surface and the gate electrode 1 that is positioned at polysilicon gate 2 upper surface; N between a described Pbase district 7 and the 2nd Pbase district 71
-epitaxial loayer 9 upper strata has groove, described groove and N
-between epitaxial loayer 9, there is P
+district 8, described gate oxide 4 is arranged in part and the P of groove
+district 8 connects, and described polysilicon gate 2 is filled in a groove; A wherein Pbase district 7 and the 2nd Pbase district 71, a N
+source region 6 and the 2nd N
+source region 61, a P
+contact zone 5 and the 2nd P
+contact zone 51, first metal source 3 and the second metal source 31 are all symmetricly set on the 2nd N
-epitaxial loayer 8 center line both sides.
A manufacture method for carborundum VDMOS device, is characterized in that, comprises the following steps:
The first step: adopt epitaxy technique, at silicon carbide N
+substrate 10 upper surface generates N
-epitaxial loayer 9;
Second step: adopt ion implantation technology, at N
-one end, epitaxial loayer 9 upper strata implanting p-type semiconductor impurities forms a Pbase district 7, and floor other end implanting p-type semiconductor impurities forms the 2nd Pbase district 71 thereon;
3rd step; Adopt ion implantation technology, form a P in upper strata, a Pbase district 7 implanting p-type semiconductor impurities
+contact zone 5, forms the 2nd P in the 2nd upper strata, Pbase district 71 implanting p-type semiconductor impurities
+contact zone 51;
4th step: adopt ion implantation technology, injects N type semiconductor impurity on a upper strata, Pbase district 7 and forms a N
+source region 6, injects N type semiconductor impurity on the 2nd upper strata, Pbase district 71 and forms the 2nd N
+source region 61; A described P
+contact zone 5 and a N
+source region 6 is separate, described 2nd P
+contact zone 51 and the 2nd N
+source region 61 is separate;
5th step: adopt ion implantation technology, the N between a Pbase district 7 and the 2nd Pbase district 71
-epitaxial loayer 9 upper strata implanting p-type semiconductor impurities generates P
+district (8), then at P
+district etches groove in (8);
6th step: P in a groove
+the device surface growth gate oxide 4 of surface, district (8) and groove both sides, at gate oxide 4 upper surface depositing polysilicon, forms polysilicon gate 2 through etching;
7th step: at a N
+source region 6 and a P
+contact zone 5 upper surface generates the first metal source 3; At the 2nd N
+source region 61 and the 2nd P
+contact zone 51 upper surface generates the second metal source 31; Polysilicon gate 2 generates gate electrode 1.
Beneficial effect of the present invention is, by introducing notched gates in carborundum VDMOS device, optimizing carborundum VDMOS device oxide field, improve the reliability of device.
Accompanying drawing explanation
Fig. 1 is Conventional silicon carbide VDMOS device structural representation;
Fig. 2 is carborundum VDMOS device structural representation provided by the invention;
Fig. 3 is at silicon carbide N
+substrate forms N
-silicon carbide epitaxial layers schematic diagram;
Fig. 4 is at the second silicon carbide N
-epitaxial loayer forms Liang Ge Pbase district schematic diagram by ion implantation;
Fig. 5 forms P respectively by ion implantation in Liang Ge Pbase district
+p in the JFET districts that contact zone and two Pbase interval are formed
+district's schematic diagram;
Fig. 6 forms N respectively by ion implantation in Liang Ge Pbase district
+source region schematic diagram;
Fig. 7 is the carborundum P in JFET district
+district carries out partial etching and forms groove schematic diagram;
Fig. 8 grows one deck gate medium silicon dioxide at semiconductor surface, and depositing polysilicon, etch polysilicon forms gate shapes schematic diagram;
Fig. 9 is forming drain electrode, gate electrode and source electrode schematic diagram respectively;
Figure 10 is a kind of high reliability carborundum VDMOS device structure provided by the invention and Conventional silicon carbide VDMOS device structure oxide field distributed simulation comparison diagram.
Embodiment
Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:
A kind of carborundum VDMOS device of the present invention, as shown in Figure 2, comprise set gradually from bottom to top metal leakage pole 11, N
+substrate 10 and N
-epitaxial loayer 9; Described N
-one end, epitaxial loayer 9 upper strata has a Pbase district 7, and its upper strata other end has the 2nd Pbase district 71; In a described Pbase district 7, there is a separate N
+source region 6 and a P
+contact zone 5; In described 2nd Pbase district 71, there is the 2nd separate N
+source region 61 and the 2nd P
+contact zone 51; A described N
+source region 6 and a P
+contact zone 5 upper surface has the first metal source 3; Described 2nd N
+source region 61 and the 2nd P
+contact zone 51 upper surface has the second metal source 31; Between described first metal source 3 and the second metal source 31, there is grid structure; Described grid structure is made up of gate oxide 4, the polysilicon gate 2 being positioned at gate oxide 4 upper surface and the gate electrode 1 that is positioned at polysilicon gate 2 upper surface; N between a described Pbase district 7 and the 2nd Pbase district 71
-epitaxial loayer 9 upper strata has groove, described groove and N
-between epitaxial loayer 9, there is P
+district (8), described gate oxide 4 is arranged in part and the P of groove
+district (8) connects, and described polysilicon gate 2 is filled in a groove; A wherein Pbase district 7 and the 2nd Pbase district 71, a N
+source region 6 and the 2nd N
+source region 61, a P
+contact zone 5 and the 2nd P
+contact zone 51, first metal source 3 and the second metal source 31 are all symmetricly set on the 2nd N
-epitaxial loayer 8 center line both sides.
A manufacture method for carborundum VDMOS device, is characterized in that, comprises the following steps:
The first step: adopt epitaxy technique, at silicon carbide N
+substrate 10 upper surface generates N
-epitaxial loayer 9, as shown in Figure 3;
Second step: adopt ion implantation technology, at N
-one end, epitaxial loayer 9 upper strata implanting p-type semiconductor impurities forms a Pbase district 7, and floor other end implanting p-type semiconductor impurities forms the 2nd Pbase district 71 thereon, as shown in Figure 4;
3rd step; Adopt ion implantation technology, form a P in upper strata, a Pbase district 7 implanting p-type semiconductor impurities
+contact zone 5, forms the 2nd P in the 2nd upper strata, Pbase district 71 implanting p-type semiconductor impurities
+contact zone 51, as shown in Figure 5;
4th step: adopt ion implantation technology, injects N type semiconductor impurity on a upper strata, Pbase district 7 and forms a N
+source region 6, injects N type semiconductor impurity on the 2nd upper strata, Pbase district 71 and forms the 2nd N
+source region 61; A described P
+contact zone 5 and a N
+source region 6 is separate, described 2nd P
+contact zone 51 and the 2nd N
+source region 61 is separate, as shown in Figure 6;
5th step: adopt ion implantation technology, the N between a Pbase district 7 and the 2nd Pbase district 71
-epitaxial loayer 9 upper strata implanting p-type semiconductor impurities generates P
+district (8), then at P
+district etches groove in (8), as shown in Figure 7;
6th step: P in a groove
+the device surface growth gate oxide 4 of surface, district (8) and groove both sides, at gate oxide 4 upper surface depositing polysilicon, forms polysilicon gate 2 through etching, as shown in Figure 8;
7th step: at a N
+source region 6 and a P
+contact zone 5 upper surface generates the first metal source 3; At the 2nd N
+source region 61 and the 2nd P
+contact zone 51 upper surface generates the second metal source 31; Polysilicon gate 2 generates gate electrode 1, as shown in Figure 9.
The present invention by carborundum VDMOS device polysilicon is made groove-like, and introduces the P be centered around around recessed JFET district silica dioxide medium
+district, by producing and the rightabout electric field of oxide field, reduce oxide field, in addition, the polysilicon of fluted body also has the effect reducing oxide field, Figure 10 is carborundum VDMOS device structure and the Conventional silicon carbide VDMOS device structure oxide field distributed simulation comparison diagram of a kind of high reliability provided by the invention, abscissa is the distance apart from JFET center, ordinate is oxide field size (electric field being arranged in the grid oxygen of JFET district genesis analysis is identical), simulation result shows, adopt carborundum VDMOS device structure of the present invention, electric field in grid oxygen can be reduced to 1.5MV/cm from 3.7MV/cm, the oxide field achieving 2.2MV/cm reduces, reduce 60%.
Claims (2)
1. a carborundum VDMOS device, comprise set gradually from bottom to top metal leakage pole (11), N
+substrate (10) and N
-epitaxial loayer (9); Described N
-epitaxial loayer (9) one end, upper strata has a Pbase district (7), and its upper strata other end has the 2nd Pbase district (71); In a described Pbase district (7), there is a separate N
+source region (6) and a P
+contact zone (5); In described 2nd Pbase district (71), there is the 2nd separate N
+source region (61) and the 2nd P
+contact zone (51); A described N
+source region (6) and a P
+contact zone (5) upper surface has the first metal source (3); Described 2nd N
+source region (61) and the 2nd P
+contact zone (51) upper surface has the second metal source (31); Between described first metal source (3) and the second metal source (31), there is grid structure; Described grid structure is made up of gate oxide (4), the polysilicon gate (2) being positioned at gate oxide (4) upper surface and the gate electrode (1) that is positioned at polysilicon gate (2) upper surface; N between a described Pbase district (7) and the 2nd Pbase district (71)
-epitaxial loayer (9) upper strata has groove, described groove and N
-epitaxial loayer has P between (9)
+district (8), described gate oxide (4) is arranged in part and the P of groove
+district (8) connects, and described polysilicon gate (2) is filled in a groove.
2. a manufacture method for carborundum VDMOS device, is characterized in that, comprises the following steps:
The first step: adopt epitaxy technique, at silicon carbide N
+substrate (10) upper surface generates N
-epitaxial loayer (9);
Second step: adopt ion implantation technology, at N
-epitaxial loayer (9) one end, upper strata implanting p-type semiconductor impurities forms a Pbase district (7), and floor other end implanting p-type semiconductor impurities forms the 2nd Pbase district (71) thereon;
3rd step; Adopt ion implantation technology, form a P in Pbase district (7) upper strata implanting p-type semiconductor impurities
+contact zone (5), forms the 2nd P in the 2nd Pbase district (71) upper strata implanting p-type semiconductor impurities
+contact zone (51);
4th step: adopt ion implantation technology, injects N type semiconductor impurity on Pbase district (7) upper strata and forms a N
+source region (6), injects N type semiconductor impurity on the 2nd Pbase district (71) upper strata and forms the 2nd N
+source region (61); A described P
+contact zone (5) and a N
+source region (6) is separate, described 2nd P
+contact zone (51) and the 2nd N
+source region (61) is separate;
5th step: adopt ion implantation technology, the N between a Pbase district (7) and the 2nd Pbase district (71)
-epitaxial loayer (9) upper strata implanting p-type semiconductor impurities generates P
+district (8), then at P
+district etches groove in (8);
6th step: P in a groove
+device surface growth gate oxide (4) of surface, district (8) and groove both sides, at gate oxide (4) upper surface depositing polysilicon, forms polysilicon gate (2) through etching;
7th step: at a N
+source region (6) and a P
+contact zone (5) upper surface generates the first metal source (3); At the 2nd N
+source region (61) and the 2nd P
+contact zone (51) upper surface generates the second metal source (31); Polysilicon gate (2) generates gate electrode (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510388838.7A CN105161533A (en) | 2015-07-02 | 2015-07-02 | Silicon carbide VDMOS device and manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510388838.7A CN105161533A (en) | 2015-07-02 | 2015-07-02 | Silicon carbide VDMOS device and manufacturing method |
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| Publication Number | Publication Date |
|---|---|
| CN105161533A true CN105161533A (en) | 2015-12-16 |
Family
ID=54802347
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|---|---|---|---|
| CN201510388838.7A Pending CN105161533A (en) | 2015-07-02 | 2015-07-02 | Silicon carbide VDMOS device and manufacturing method |
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Cited By (8)
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| CN107527803A (en) * | 2017-08-24 | 2017-12-29 | 中国科学院上海微系统与信息技术研究所 | The preparation method of SiC device gate dielectric layer and SiC device structure |
| CN109103237A (en) * | 2018-06-20 | 2018-12-28 | 中国电子科技集团公司第五十五研究所 | The single cell structure and preparation method of a kind of highly doped silicon carbide MOSFET of area JFET T-type |
| CN109411546A (en) * | 2018-10-31 | 2019-03-01 | 秦皇岛京河科学技术研究院有限公司 | SiC groove MOS device and preparation method thereof |
| CN109801959A (en) * | 2019-01-24 | 2019-05-24 | 泰科天润半导体科技（北京）有限公司 | A kind of SiC base DMOSFET device and preparation method thereof |
| US10593641B2 (en) | 2016-01-22 | 2020-03-17 | Sj Semiconductor (Jiangyin) Corporation | Package method and package structure of fan-out chip |
| CN113314613A (en) * | 2021-05-31 | 2021-08-27 | 电子科技大学 | Silicon carbide MOSFET device with avalanche charge transition buffer layer and preparation method |
| CN115084246A (en) * | 2022-08-22 | 2022-09-20 | 泰科天润半导体科技（北京）有限公司 | Manufacturing method of silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of reducing gate charges |
| CN116759461A (en) * | 2023-08-18 | 2023-09-15 | 深圳市冠禹半导体有限公司 | High-temperature-stability power MOSFET device and preparation method thereof |
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| CN113314613A (en) * | 2021-05-31 | 2021-08-27 | 电子科技大学 | Silicon carbide MOSFET device with avalanche charge transition buffer layer and preparation method |
| CN115084246A (en) * | 2022-08-22 | 2022-09-20 | 泰科天润半导体科技（北京）有限公司 | Manufacturing method of silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of reducing gate charges |
| CN116759461A (en) * | 2023-08-18 | 2023-09-15 | 深圳市冠禹半导体有限公司 | High-temperature-stability power MOSFET device and preparation method thereof |
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