WO2019101009A1

WO2019101009A1 - Preparation method for sic-based umosfet, and sic-based umosfet

Info

Publication number: WO2019101009A1
Application number: PCT/CN2018/115869
Authority: WO
Inventors: 何志
Original assignee: 重庆伟特森电子科技有限公司; 北京品捷电子科技有限公司
Priority date: 2017-11-27
Filing date: 2018-11-16
Publication date: 2019-05-31
Also published as: CN107785438A

Abstract

Provided are a preparation method for an SiC-based UMOSFET, and an SiC-based UMOSFET. The SiC-based UMOSFET comprises: an epitaxial slice comprising an N+ type 4H-SiC substrate (1) and an N- type epitaxial layer (2) which is homogenously grown on the front of the N+ type 4H-SiC substrate (1); a P-doped layer (3) formed on an upper surface of the N-type epitaxial layer (2); an N+ type ion implantation layer (4) formed in the P-doped layer (3); a gate electrode trench (5) penetrating through the P-doped layer (3) and the N+ type ion implantation layer (4); an oxide layer (7) covering the bottom and side walls of the gate electrode trench (5); a polycrystalline silicon gate electrode (8) formed in the gate electrode trench (5) and covering the oxide layer (7); a dielectric layer (9) covering the polycrystalline silicon gate electrode (8) and part of an area of the N+ type ion implantation layer (4); a source electrode metal layer (11) covering the upper surfaces of the dielectric layer (9) and the P-doped layer (3) and covering an area, which is not covered by the dielectric layer (9), of the N+ type ion implantation layer (4); and a drain electrode metal layer (12) formed on the back of the N+ type 4H-SiC substrate (1). The thickness of the oxide layer at the bottom of the gate electrode trench of the SiC-based UMOSFET is increasesd, which reduces the electric field strength of the oxide layer at the bottom of the gate electrode trench and the capacitance between a gate electrode and a drain electrode.

Description

Method for preparing SiC-based UMOSFET and SiC-based UMOSFET

Technical field

The present invention relates to the field of semiconductor device technology. More specifically, it relates to a method of fabricating a SiC-based UMOSFET (U-shaped Metal-Oxide-Semiconductor Field-Effect Transistor) and a SiC-based UMOSFET.

Background technique

SiC is a wide bandgap semiconductor material with high saturation electron mobility, high breakdown electric field strength, and high thermal conductivity. It is especially suitable for high voltage, high current, high temperature, high radiation and other environments.

As a switching device, a MOSFET-Metal-Oxide-Semiconductor Field-Effect Transistor is a IGBT-Insulated Gate Bipolar Transistor of the same electrical grade. Higher operating frequency and lower power consumption. Therefore, SiC-based MOSFETs are widely used in inverters, photovoltaics, wind power, rail trains, aerospace, DC high-voltage power transmission, etc., and with the continuous improvement of electrical grades, the application advantages of SiC-based semiconductor devices become more prominent.

SiC-based MOSFETs as switching devices are mainly classified into two types, one is planar and the other is trench. The planar MOSFET is formed by implanting ions on the SiC epitaxial layer to form a P-doped region and an N+ region, directly growing an oxide layer on the surface of the epitaxial layer by high-temperature thermal growth, and then depositing a layer of polysilicon on the oxide layer and polysilicon. A gate is formed after the patterning process. The trench MOSFET is trenched on the epitaxial layer, and the polysilicon gate wrapped by the dielectric layer is placed therein.

Since the trench type SiC-based MOSFET improves the density of the conductive channel by placing the conductive channel vertically, the JFET (Junction Field-Effect Transistor) region in the planar MOSFET is eliminated, thereby realizing Lower on-resistance is favored. However, since SiC epitaxial growth is usually based on the Si crystal plane, the Si crystal plane has the slowest oxidation rate in each crystal plane of SiC, and therefore the oxide layer at the bottom of the trench after the high temperature thermal oxidation of the trench on the epitaxial layer The thickness is significantly thinner than the sidewalls of the trench, which makes the gate oxide layer at the bottom of the trench easily break down due to excessive electric field in the device when the high voltage is blocked, thereby causing the entire semiconductor device to fail. At the same time, the gate oxide layer at the bottom of the trench with a thin thickness causes the gate-drain capacitance to be high, and the frequency response characteristics of the semiconductor device may be deviated.

Therefore, there is a need to provide a SiC-based UMOSFET having high reliability and low gate-drain capacitance.

Summary of the invention

A first technical problem to be solved by the present invention is to provide a method of fabricating a SiC-based UMOSFET.

A second technical problem to be solved by the present invention is to provide a SiC-based UMOSFET.

In order to solve the above first technical problem, the invention adopts the following technical solutions:

A method for preparing a SiC-based UMOSFET, the method comprising the steps of:

S1: selecting an epitaxial wafer having an N-type epitaxial layer grown on the front surface of the N+ type 4H-SiC substrate;

S2: performing P-type doping or P-type epitaxial growth on the N-type epitaxial layer to form a P-doped layer;

S3: depositing a first dielectric mask layer on the P-doped layer, forming an ion implantation window on the first dielectric mask layer by photolithography, so that the P-doped layer located at the ion implantation window is exposed;

S4: performing N+-type ion implantation on the exposed P-doped layer through the ion implantation window, then peeling off the first dielectric mask layer, and performing a first annealing treatment to form an N+-type ion implantation layer in the P-doped layer. The upper surface of the N+ type ion implantation layer coincides with the upper surface of the P doped layer, and the thickness of the N+ type ion implantation layer is smaller than the P doped layer;

S5: depositing a second dielectric mask layer on the surface of the P-doped layer, and forming a gate trench window on the second dielectric mask layer by photolithography, so that the N+-type ions located at the gate trench window The injection layer is bare;

S6: sequentially etching the exposed N+ type ion implantation layer and the P doped layer under the N+ type ion implantation layer to the upper surface of the N-type epitaxial layer through the gate trench window to form a gate trench And the P doped layer and the N+ type ion implantation layer are both divided into two parts by the gate trench;

S7: performing oxygen ion implantation on the N-type epitaxial layer at the bottom of the gate trench, forming an oxygen ion implantation layer in the N-type epitaxial layer at the bottom of the gate trench, and then peeling off the second dielectric mask layer;

S8: performing thermal oxidation treatment so that the oxygen ion implantation layer is oxidized, forming an oxide layer at the bottom of the gate trench and the sidewall thereof, and the thickness of the oxide layer at the bottom of the gate trench is greater than or equal to the sidewall of the gate trench Oxide layer

S9: depositing a polysilicon layer on the surface of the bump in the gate trench and on both sides thereof, so that the polysilicon layer just fills the gate trench;

S10: the polysilicon layer in the gate trench is covered by the photoresist by photolithography, and the polysilicon layer on the convex surface on both sides of the gate trench is exposed, and then the gate trench is convex on both sides of the trench The polysilicon layer is removed, and the polysilicon layer remaining in the gate trench forms a polysilicon gate;

S11: depositing a dielectric layer on the surface of the polysilicon gate and the land on both sides of the gate trench;

S12: the dielectric layer above the gate trench is covered by the photoresist by photolithography, and a part of the dielectric layer on the convex surface of the gate trench is exposed, and then the gate trench is convex on both sides of the trench. Part of the dielectric layer is removed such that the P-doped layer and the partial N+-type ion implantation layer on each side of the gate trench are exposed, and a source contact region is formed on each side of the gate trench;

S13: depositing a source metal layer on the surface of the dielectric layer and the source contact region, depositing a drain metal layer on the back side of the N+ type 4H-SiC substrate, and then performing a second annealing treatment to obtain a SiC-based UMOSFET.

Preferably, the steps S9-S11 are replaced by the following steps:

S9': depositing a polysilicon layer on the surface of the bump in the gate trench and on both sides thereof, so that the polysilicon layer in the gate trench is filled and overflows;

S10': then etching the polysilicon layer on the land surface above the gate trench and on both sides thereof, so that a continuous and flat surface is left above the gate trench and on the convex surfaces on both sides thereof Polysilicon layer

S11': the polysilicon layer remaining on the land surface above and above the gate trench is oxidized to form a dielectric layer by oxidation treatment, and the unoxidized polysilicon remaining in the gate trench The layer forms a polysilicon gate.

As a further improvement of the technical solution, in the step S4, the implantation concentration of the N+ type ions in the N+ type ion implantation layer is 1×10 ¹⁸ cm ⁻³ to 1×10 ²¹ cm ⁻³ , and the implantation depth of the N+ type ions is 10 nm to 1000 nm. .

As a further improvement of the technical solution, in the step S7, the implantation depth of oxygen ions in the oxygen ion implantation layer is 30 nm to 1000 nm, and the implantation concentration of oxygen ions is 1×10 ¹⁸ cm ⁻³ to 1×10 ²² cm ⁻³ .

As a further improvement of the technical solution, in the step S8, the temperature of the thermal oxidation treatment is 600 ° C to 2000 ° C.

Preferably, in the step S8, the thickness of the oxide layer at the bottom of the gate trench is 40 nm to 1000 nm; and the thickness of the oxide layer of the sidewall of the gate trench is 20 nm to 1000 nm.

As a further improvement of the technical solution, the first dielectric mask layer and the second dielectric mask layer are both a hard mask layer or a soft mask layer; the hard mask layer is made of SiO ₂ , Si ₃ N ₄ , AlN or a mixture thereof; the soft mask layer is a photoresist.

In order to solve the above second technical problem, the present invention adopts the following technical solutions:

A SiC-based UMOSFET prepared by the above preparation method, the SiC-based UMOSFET comprising:

An epitaxial wafer comprising an N+ type 4H-SiC substrate and an N-type epitaxial layer grown homogenously on the front side of the N+ type 4H-SiC substrate;

a P-doped layer formed on the upper surface of the N-type epitaxial layer;

An N+ type ion implantation layer is formed in the P doped layer, an upper surface of the N+ type ion implantation layer is overlapped with an upper surface of the P doped layer, and a thickness of the N+ type ion implantation layer is smaller than a P doped layer;

a gate trench penetrating through the P doped layer and the N+ type ion implantation layer, and the gate trench depth is greater than the thickness of the P doped layer, such that the bottom of the gate trench is embedded in the N-type epitaxial layer;

An oxide layer covering the bottom and sidewalls of the gate trench;

a polysilicon gate formed in the gate trench and covering the oxide layer;

a dielectric layer covering a polysilicon gate and a partial region of the N+ type ion implantation layer;

a source metal layer covering the upper surface of the dielectric layer and the P-doped layer and covering an area of the N+ type ion implantation layer not covered by the dielectric layer;

A drain metal layer is formed on the back side of the N+ type 4H-SiC substrate.

As a further improvement of the technical solution, the N+ type ion implantation layer has an implantation concentration of 1×10 ¹⁸ cm ⁻³ to 1×10 ²¹ cm ⁻³ , and the N+ ion implantation depth is 10 nm to 1000 nm.

As a further improvement of the technical solution, the thickness of the oxide layer at the bottom of the gate trench is 40 nm to 1000 nm; and the thickness of the oxide layer of the sidewall of the gate trench is 20 nm to 1000 nm.

Any range recited in the present invention includes any value between the end value and the end value, and any subrange of any value between the end value or the end value.

Unless otherwise specified, each of the raw materials in the present invention can be obtained by commercially available purchase, and the apparatus used in the present invention can be carried out by using conventional equipment in the art or by referring to the prior art in the related art.

Compared with the prior art, the present invention has the following beneficial effects:

Compared with the prior art, the method for fabricating the SiC-based UMOSFET of the present invention amorphizes the SiC in the N-type epitaxial layer by performing oxygen ion implantation on the N-type epitaxial layer at the bottom of the gate trench. An oxygen ion implantation layer is formed in the N-type epitaxial layer at the bottom of the pole trench, and the thickness of the oxide layer at the bottom of the gate trench is greater than the thickness of the oxide layer of the sidewall of the gate trench by oxidation, thereby reducing the oxide layer at the bottom of the gate trench The electric field strength and the capacitance between the gate and drain ultimately improve the reliability and frequency response characteristics of the UMOSFET device.

DRAWINGS

The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

1 is a flow chart of a method for fabricating a SiC-based UMOSFET according to an embodiment of the present invention;

2-14 are schematic diagrams showing steps of a method for fabricating a SiC-based UMOSFET according to an embodiment of the present invention;

FIG. 15 is a partial schematic diagram of a method of fabricating a SiC-based UMOSFET according to another embodiment of the present invention.

Detailed ways

In order to more clearly illustrate the invention, the invention will be further described in conjunction with the preferred embodiments. It should be understood by those skilled in the art that the following detailed description is intended to be illustrative and not restrictive.

As shown in FIG. 1 , the embodiment provides a method for preparing a SiC-based UMOSFET, and the preparation method includes the following steps:

S1: an epitaxial wafer having an N-type epitaxial layer 2 grown on the front surface of the N+ type 4H-SiC substrate 1 is selected (the epitaxial wafer includes an N+ type 4H-SiC substrate 1 and an N-type epitaxial layer 2), as shown in the figure. 2;

S2: performing P-type doping or P-type epitaxial growth on the N-type epitaxial layer 2 to form a P-doped layer 3, as shown in FIG. 3;

S3: depositing a first dielectric mask layer M1 on the P-doped layer 3, forming an ion implantation window L1 on the first dielectric mask layer M1 by photolithography, so that the P-doping at the ion implantation window L1 is performed. Layer 3 is bare, as shown in Figure 4;

S4: N+-type ion implantation is performed on the exposed P-doped layer 3 through the ion implantation window L1, and then the first dielectric mask layer M1 is stripped, and then subjected to a first annealing treatment to form an N+ type in the P-doped layer 3. The ion implantation layer 4, the upper surface of the N+ type ion implantation layer 4 coincides with the upper surface of the P doped layer 3, and the thickness of the N+ type ion implantation layer 4 is smaller than that of the P doped layer 3, as shown in FIG. 5; The first annealing treatment is a high temperature annealing treatment, and the first annealing treatment is performed to activate ions implanted into the P doped layer 3; the N+ type ion implantation layer 4 is preferably located in an intermediate portion of the P doped layer 3;

S5: depositing a second dielectric mask layer M2 on the surface of the P-doped layer 3 (including the N+-type ion implantation layer 4 therein), and forming a gate trench on the second dielectric mask layer M2 by photolithography The slot window L2 causes the N+ type ion implantation layer 4 located at the gate trench window to be exposed, as shown in FIG. 6;

S6: sequentially etching the exposed N+ type ion implantation layer 4 and the P doped layer 3 under the N+ type ion implantation layer 4 to the upper surface of the N-type epitaxial layer 2 via the gate trench window L2. The gate trench 5 is formed, and both the P doped layer 3 and the N+ type ion implantation layer 4 are divided into two portions by the gate trench 5 as shown in FIG. 7; the gate trench 5 is preferably located in the P doped layer 3 And an intermediate region of the N+ type ion implantation layer 4;

S7: performing oxygen ion implantation on the N-type epitaxial layer 2 at the bottom of the gate trench 5, forming an oxygen ion implantation layer 6 in the N-type epitaxial layer 2 at the bottom of the gate trench 5, and then masking the second dielectric The film layer M2 is peeled off, as shown in FIG. 8; in this step, oxygen ion implantation causes the SiC in the N-type epitaxial layer 2 to be amorphized;

S8: performing thermal oxidation treatment so that the oxygen ion implantation layer 6 is oxidized, forming an oxide layer 7 at the bottom of the gate trench 5 and its sidewall, and the thickness of the oxide layer at the bottom of the gate trench 5 is greater than or equal to the gate. The oxide layer on the sidewall of the trench 5 is as shown in FIG. 9; in this step, the thermal oxidation treatment also forms a thin oxide layer on the convex surface on both sides of the gate trench 5 (not shown) Shown), ignored here;

S9: depositing a polysilicon layer 8 on the surface of the land in the gate trench 5 and on both sides thereof, so that the polysilicon layer 8 just fills the gate trench 5 (ie, the surface of the polysilicon layer 8 in the gate trench 5) Just flush with the surface of the land on both sides of the gate trench 5, as shown in FIG. 10;

S10: the polysilicon layer 8 in the gate trench 5 is covered by the photoresist by photolithography, and the polysilicon layer 8 on the convex surface of the gate trench 5 is exposed, and then the gate trench 5 is etched. The polysilicon layer 8 on the side convex mesa is removed, and the polysilicon layer 8 remaining in the gate trench 5 forms a polysilicon gate, as shown in FIG. 11;

S11: depositing a dielectric layer 9 on the surface of the polysilicon gate and the land on both sides of the gate trench 5, as shown in FIG. 12;

S12: the dielectric layer 9 above the gate trench 5 is covered by the photoresist by photolithography, and a part of the dielectric layer 9 on the convex surface of the gate trench 5 is exposed, and then the gate trench 5 is etched. A portion of the dielectric layer 9 on both sides of the land is removed, such that the P-doped layer 3 and the portion of the N+-type ion implantation layer 4 on each side of the gate trench 5 are exposed, and a source contact is formed on each side of the gate trench 5. Zone 10, as shown in Figure 13;

S13: depositing a source metal layer 11 on the surface of the dielectric layer 9 and the source contact region 10, depositing a drain metal layer 12 on the back surface of the N+ type 4H-SiC substrate 1, and then performing a second annealing treatment to obtain SiC-based UMOSFET, as shown in Figure 14.

In a preferred embodiment of the embodiment, the above steps S9-S11 are replaced by the following steps (the remaining steps are unchanged):

Step S9' is: depositing a polysilicon layer 8 on the surface of the land in the gate trench 5 and on both sides thereof, so that the polysilicon layer 8 in the gate trench 5 is filled and overflows (ie, in the gate trench 5). The upper surface of the polysilicon layer 8 exceeds the surface of the land on both sides of the gate trench 5);

Step S10' is: then etching the polysilicon layer 8 on the land surface above the gate trench 5 and on both sides thereof, so that a continuous and flat polysilicon layer is left on the land surface of the gate trench 5 and on both sides of the land surface. 8, as shown in Figure 15;

Step S11' is: the polysilicon layer 8 remaining on the land surface on the gate trench 5 and on both sides of the gate trench 5 is oxidized to form the dielectric layer 9 by the oxidation treatment, and the unoxidized polysilicon remaining in the gate trench 5 is formed. Layer 8 forms a polysilicon gate as shown in FIG.

In a preferred embodiment of the present embodiment, in the above step S1, the N-type epitaxial layer 2 is formed based on Si-plane epitaxial growth of SiC.

In a preferred embodiment of the present embodiment, in the above step S2, the P-doping layer 3 has a P-type doping concentration of 1×10 ¹⁵ cm ⁻³ to 1×10 ¹⁸ cm ⁻³ .

In a preferred embodiment of the present embodiment, in the step S4, the implantation concentration of the N+ type ions in the N+ type ion implantation layer 4 is 1×10 ¹⁸ cm ⁻³ to 1×10 ²¹ cm ⁻³ , and the implantation depth of the N+ type ions is 10 nm to 1000 nm.

In a preferred embodiment of the present embodiment, in the above step S7, the oxygen ion implantation depth in the oxygen ion implantation layer 6 is 30 nm to 1000 nm, and the oxygen ion implantation concentration is 1 x 10 ¹⁸ cm ^-3 to 1 x 10 ²² cm ^{-3 .} .

In a preferred embodiment of the present embodiment, in the above step S8, the temperature of the thermal oxidation treatment is 600 ° C to 2000 ° C.

In a preferred embodiment of the present embodiment, in the above step S8, the thickness of the oxide layer at the bottom of the gate trench 5 is 40 nm to 1000 nm; and the thickness of the oxide layer on the sidewall of the gate trench 5 is 20 nm to 1000 nm.

In a preferred embodiment of the embodiment, the first dielectric mask layer M1 and the second dielectric mask layer M2 are both a hard mask layer or a soft mask layer. The material of the hard mask layer is SiO ₂ , Si ₃ N ₄ , AlN or a mixture thereof; the soft mask layer is a photoresist.

As shown in FIG. 14, the embodiment provides a SiC-based UMOSFET prepared by the above preparation method, and the SiC-based UMOSFET includes:

An epitaxial wafer comprising an N+ type 4H-SiC substrate 1 and an N-type epitaxial layer 2 grown homogenously on the front side of the N+ type 4H-SiC substrate 1;

a P-doped layer 3 formed on the upper surface of the N-type epitaxial layer 2;

An N+ type ion implantation layer 4 is formed in the P doped layer 3, an upper surface of the N+ type ion implantation layer 4 coincides with an upper surface of the P doped layer 3, and a thickness of the N+ type ion implantation layer 4 is smaller than a P doping layer. Layer 3; the N+ type ion implantation layer 4 is preferably located in an intermediate region of the P doped layer 3;

a gate trench 5 through which the gate trench 5 penetrates the doped layer 3 and the N+ type ion implantation layer 4, and the depth of the gate trench 5 is greater than the thickness of the P doped layer 3, so that the bottom of the gate trench 5 is embedded N-type epitaxial layer 2;

An oxide layer 7 covering the bottom and sidewalls of the gate trench 5;

a polysilicon gate formed in the gate trench 5 and covering the oxide layer 7;

a dielectric layer 9, covering a polysilicon gate and a partial region of the N+ type ion implantation layer 4;

a source metal layer 11 covering the upper surfaces of the dielectric layer 9 and the P doped layer 3 and covering a region of the N+ type ion implantation layer 4 not covered by the dielectric layer 9;

A drain metal layer 12 is formed on the back surface of the N+ type 4H-SiC substrate 1.

In a preferred embodiment of the present embodiment, the N-type epitaxial layer 2 is formed based on Si crystal facet epitaxial growth of SiC.

In a preferred embodiment of the present embodiment, the P-doped layer 3 has a P-type doping concentration of 1 x 10 ¹⁵ cm ^-3 to 1 x 10 ¹⁸ cm ^-3 .

In a preferred embodiment of the present embodiment, the implantation concentration of the N+ type ions in the N+ type ion implantation layer 4 is 1×10 ¹⁸ cm ⁻³ to 1×10 ²¹ cm ⁻³ , and the implantation depth of the N+ ions is 10 nm to 1000 nm.

In a preferred embodiment of the present embodiment, the oxygen ion implantation layer 6 has an implantation depth of oxygen ions of 30 nm to 1000 nm and an oxygen ion implantation concentration of 1 x 10 ¹⁸ cm ^-3 to 1 x 10 ²² cm ^-3 .

In a preferred embodiment of the present embodiment, the thickness of the oxide layer at the bottom of the gate trench 5 is 40 nm to 1000 nm; and the thickness of the oxide layer of the sidewall of the gate trench 5 is 20 nm to 1000 nm.

It is apparent that the above-described embodiments of the present invention are merely illustrative of the present invention and are not intended to limit the embodiments of the present invention. Other variations or modifications of the various forms may be made by those skilled in the art in light of the above description. It is not possible to exhaust all implementations here. Obvious changes or variations that come within the scope of the invention are still within the scope of the invention.

Claims

A method for preparing a SiC-based UMOSFET, characterized in that the preparation method comprises the following steps:

S1: an epitaxial wafer having an N-type epitaxial layer (2) grown on the front surface of the N+ type 4H-SiC substrate (1) is selected;

S2: P-type doping or P-type epitaxial growth of the N-type epitaxial layer (2) to form a P-doped layer (3);

S3: depositing a first dielectric mask layer on the P-doped layer (3), forming an ion implantation window on the first dielectric mask layer by photolithography, so that the P-doped layer located at the ion implantation window ( 3) bare;

S4: performing N+-type ion implantation on the exposed P-doped layer (3) through the ion implantation window, then peeling off the first dielectric mask layer, and performing a first annealing treatment to form a P-doped layer (3). The N+ type ion implantation layer (4), the upper surface of the N+ type ion implantation layer (4) coincides with the upper surface of the P doped layer (3), and the thickness of the N+ type ion implantation layer (4) is smaller than that of the P doped layer ( 3);

S5: depositing a second dielectric mask layer on the upper surface of the P-doped layer (3), and forming a gate trench window on the second dielectric mask layer by photolithography, so as to be located at the gate trench window N+ type ion implantation layer (4) is exposed;

S6: sequentially etching the exposed N+ type ion implantation layer (4) and the P doped layer (3) under the N+ type ion implantation layer (4) through the gate trench window to be lower than the N-type epitaxial layer a gate trench (5) is formed on the upper surface of (2), and the P-doped layer (3) and the N+-type ion implantation layer (4) are both divided into two portions by the gate trench (5);

S7: performing oxygen ion implantation on the N-type epitaxial layer (2) at the bottom of the gate trench (5), and forming an oxygen ion implantation layer in the N-type epitaxial layer (2) at the bottom of the gate trench (5) (6), then peeling off the second dielectric mask layer;

S8: performing thermal oxidation treatment so that the oxygen ion implantation layer (6) is oxidized, forming an oxide layer (7) at the bottom of the gate trench (5) and its sidewall, and oxidizing the bottom of the gate trench (5) The thickness of the layer is greater than or equal to the oxide layer of the sidewall of the gate trench (5);

S9: depositing a polysilicon layer (8) on the surface of the bump in the gate trench (5) and on both sides thereof, so that the polysilicon layer (8) just fills the gate trench (5);

S10: the polysilicon layer (8) in the gate trench (5) is covered by the photoresist by photolithography, and the polysilicon layer (8) on the convex surface on both sides of the gate trench (5) is exposed, and then engraved The etch removes the polysilicon layer (8) on the land on both sides of the gate trench (5), and the polysilicon layer (8) remaining in the gate trench (5) forms a polysilicon gate;

S11: depositing a dielectric layer (9) on the surface of the pad on both sides of the polysilicon gate and the gate trench (5);

S12: the dielectric layer (9) above the gate trench (5) is covered by the photoresist by photolithography, and a part of the dielectric layer (9) on the convex surface on both sides of the gate trench (5) is exposed, and then passes through Etching removes a portion of the dielectric layer (9) on the land surface on both sides of the gate trench (5) such that the P-doped layer (3) and the partial N+-type ion implantation layer on each side of the gate trench (5) 4) bare, forming a source contact region (10) on each side of the gate trench (5);

S13: depositing a source metal layer (11) on the surface of the dielectric layer (9) and the source contact region (10), and depositing a drain metal layer on the back side of the N+ type 4H-SiC substrate (1) (12) Then, a second annealing treatment is performed to obtain a SiC-based UMOSFET.
The method of fabricating a SiC-based UMOSFET according to claim 1, wherein the steps S9-S11 are replaced by the following steps:

S9': depositing a polysilicon layer (8) on the surface of the land in the gate trench (5) and on both sides thereof, so that the polysilicon layer (8) in the gate trench (5) is filled Post overflow

S10': then etching the polysilicon layer (8) above the gate trench (5) and on the convex surfaces on both sides thereof so as to be convex above the gate trench (5) and on both sides thereof a continuous, flat layer of the polysilicon (8) is left on the mesa;

S11': the polysilicon layer (8) remaining above the gate trench (5) and on both sides of the land surface is oxidized to form a dielectric layer (9) by oxidation treatment, leaving the gate The unoxidized polysilicon layer (8) within the trench (5) forms a polysilicon gate.
The method for fabricating a SiC-based UMOSFET according to claim 1 or 2, wherein in the step S4, the implantation concentration of the N+ type ions in the N+ type ion implantation layer (4) is 1×10 18 cm -3 to 1x10 21 cm -3 , the implantation depth of the N+ type ions is 10 nm to 1000 nm.
The method for fabricating a SiC-based UMOSFET according to claim 1 or 2, wherein in the step S7, the oxygen ion implantation layer (6) has an implantation depth of oxygen ions of 30 nm to 1000 nm, and oxygen ion implantation The concentration is 1x10 18 cm -3 to 1x10 22 cm -3 .
The method of manufacturing a SiC-based UMOSFET according to claim 1 or 2, wherein in the step S8, the temperature of the thermal oxidation treatment is 600 ° C to 2000 ° C.
The method for fabricating a SiC-based UMOSFET according to claim 1 or 2, wherein in the step S8, the thickness of the oxide layer at the bottom of the gate trench (5) is 40 nm to 1000 nm; The oxide layer on the sidewall of the trench (5) has a thickness of 20 nm to 1000 nm.
The method for fabricating a SiC-based UMOSFET according to claim 1 or 2, wherein the first dielectric mask layer and the second dielectric mask layer are both a hard mask layer or a soft mask layer; The material of the hard mask layer is SiO 2 , Si 3 N 4 , AlN or a mixture thereof; the soft mask layer is a photoresist.
A SiC-based UMOSFET prepared by the preparation method according to any one of claims 1 to 7, characterized in that the SiC-based UMOSFET comprises:

An epitaxial wafer comprising an N+ type 4H-SiC substrate (1), and an N-type epitaxial layer (2) grown homogenously on the front side of the N+ type 4H-SiC substrate (1);

a P-doped layer (3) formed on the upper surface of the N-type epitaxial layer (2);

An N+ type ion implantation layer (4) is formed in the P doped layer (3), an upper surface of the N+ type ion implantation layer (4) coincides with an upper surface of the P doped layer (3), and an N+ type ion implantation The thickness of the layer (4) is smaller than the P doped layer (3);

a gate trench (5) penetrating the doped layer (3) and the N+ type ion implantation layer (4), and the gate trench (5) has a depth greater than a thickness of the P doped layer (3), such that the gate trench The bottom of the groove (5) is embedded with an N-type epitaxial layer (2);

An oxide layer (7) covering the bottom and sidewalls of the gate trench (5);

a polysilicon gate formed in the gate trench (5) and covering the oxide layer (7);

a dielectric layer (9) covering a polysilicon gate and a partial region of the N+ type ion implantation layer (4);

a source metal layer (11) covering the upper surface of the dielectric layer (9) and the P-doped layer (3) and covering a region of the N+ type ion implantation layer (4) not covered by the dielectric layer (9);

A drain metal layer (12) is formed on the back surface of the N+ type 4H-SiC substrate (1).
The SiC-based UMOSFET according to claim 8, wherein an implantation concentration of the N+ type ions in the N+ type ion implantation layer (4) is 1 x 10 18 cm -3 to 1 x 10 21 cm -3 , and an implantation depth of the N+ ions It is from 10 nm to 1000 nm.
The SiC-based UMOSFET according to claim 8, wherein the oxide layer at the bottom of the gate trench (5) has a thickness of 40 nm to 1000 nm; and the oxide layer of the sidewall of the gate trench (5) The thickness is from 20 nm to 1000 nm.