CN111180316A - Silicon carbide thick bottom oxide layer groove MOS preparation method - Google Patents
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- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title description 29
- 229910010271 silicon carbide Inorganic materials 0.000 title description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 31
- 229920005591 polysilicon Polymers 0.000 claims abstract description 25
- 230000001590 oxidative effect Effects 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 46
- 229920002120 photoresistant polymer Polymers 0.000 claims description 45
- 239000002184 metal Substances 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims description 4
- 229910052906 cristobalite Inorganic materials 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 229910052682 stishovite Inorganic materials 0.000 claims description 4
- 229910052905 tridymite Inorganic materials 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- 230000003647 oxidation Effects 0.000 abstract description 6
- 230000005684 electric field Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/048—Making electrodes
- H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
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Abstract
A preparation method of a thick bottom oxide layer groove MOS comprises the following steps: 1 etching the upper surface of a semiconductor epitaxial layer to form a groove; 2 depositing polysilicon or amorphous silicon on the upper surface of the epitaxial layer and the inner wall of the trench; 3, oxidizing the polycrystalline silicon or amorphous silicon at the bottom of the groove at high temperature to form a first thickness medium layer, and oxidizing the upper surface of the epitaxial layer and the side wall of the groove at high temperature to form a second thickness medium layer, wherein the thickness of the second thickness medium layer is smaller than that of the first thickness medium layer; and 4, forming a gate of the MOS at the part which is not filled in the groove. The preparation method has the following advantages: the preparation of thick oxide layer is realized through the polycrystalline silicon or amorphous silicon of oxidation ditch groove bottom to make the oxide layer thickness of MOS structure ditch groove bottom obviously thicker than the lateral wall, and then effectively reduced electric field strength wherein, improved SiC ditch groove MOSFET's reliability, simultaneously, help reducing the gate leakage electric capacity of ditch groove type MOSFET device, thereby reduce the dynamic loss of device, improve the switching speed of device.
Description
Technical Field
The invention relates to a method for preparing an MOS (metal oxide semiconductor), in particular to a method for preparing a silicon carbide thick bottom oxide layer groove MOS.
Background
Modern electronic technology puts forward new requirements on semiconductor materials such as high voltage, high frequency, high power, high temperature, radiation resistance and the like, while the wide-bandgap third-generation semiconductor material SiC has the advantages of wide forbidden band, high critical breakdown field strength, high saturated electron mobility, high melting point, high thermal conductivity and the like, and is an ideal material for preparing power electronic devices. In the SiC switch device, the SiC MOSFET has the advantages of high switching speed, high voltage resistance, low power consumption and the like, the SiC MOSFET is mainly divided into a planar type and a groove type, because a vertical channel adopted by a groove type device has higher electron mobility and does not have JFET effect, compared with the planar SiC MOSFET, the groove type SiC MOSFET can realize lower on-resistance, and therefore the groove type SiC MOSFET has wider development prospect.
When the SiC trench MOS structure is prepared by a conventional oxidation process, because the oxidation speeds of all crystal planes of SiC are different, and the oxidation speed of an epitaxial crystal plane (0001) plane (Si plane) is smaller than that of a vertical crystal plane (11-20) plane and a vertical crystal plane (1-100) plane by one order of magnitude, the thickness of an oxide layer grown at the bottom of a trench is far shorter than that of a side wall, the intensity of an electric field is increased due to the fact that the bottom oxide layer is too thin, and when a device is in reverse bias, the thin oxide layer at the bottom of the trench can cause a current tunneling effect due to the fact that the electric field is.
Disclosure of Invention
The invention provides a preparation method of a silicon carbide thick bottom oxide layer groove MOS, which is characterized in that the thickness of a bottom oxide layer of an MOS structure is increased by oxidizing polycrystalline silicon or amorphous silicon at the bottom of a groove, so that the electric field intensity in the groove is effectively reduced, and the reliability of the SiC groove MOSFET is improved.
The invention provides the following technical scheme:
a preparation method of a thick bottom oxide layer groove MOS comprises the following steps:
etching the upper surface of a semiconductor epitaxial layer to form a groove;
depositing a layer of polycrystalline silicon or amorphous silicon on the upper surface of the semiconductor epitaxial layer and the inner wall of the groove;
oxidizing the polycrystalline silicon or amorphous silicon at the bottom of the groove at high temperature to form a first thickness medium layer, and oxidizing the upper surface of the semiconductor epitaxial layer and the side wall of the groove at high temperature to form a second thickness medium layer, wherein the thickness of the second thickness medium layer is smaller than that of the first thickness medium layer;
and step four, forming a gate of the MOS at the part which is not filled in the groove.
Further, the semiconductor epitaxial layer is made of SiC; a dielectric layer of a first thickness and a dielectric layer of a second thicknessThe layers are all SiO2(ii) a The gate electrode is a polysilicon or metal electrode.
Further, the method of step three may be: a1 coating photoresist on the surface of the polysilicon or amorphous silicon formed in the second step, carrying out photoetching development, removing the redundant photoresist and only keeping the photoresist at the bottom of the groove; a2 etching to remove polysilicon or amorphous silicon not contacted with the photoresist; a3 removing the photoresist at the bottom of the trench; a4 oxidizing the polysilicon or amorphous silicon at the bottom of the trench at high temperature to form SiO with a first thickness2An oxide layer; a5 the upper surface of the SiC epitaxial layer and the side wall of the groove are oxidized at high temperature to form SiO with the second thickness2And oxidizing the layer.
Further, the method of step three may also be: b1 completely oxidizing the polysilicon or amorphous silicon formed in the second step into SiO with the first thickness2An oxide layer; first thickness SiO formed by oxidizing B22Coating photoresist on the surface of the oxidation layer, carrying out photoetching development, removing redundant photoresist and only retaining the photoresist at the bottom of the groove; b3 etching to remove the first thickness SiO not contacted with the photoresist2An oxide layer; b4 removing the photoresist at the bottom of the trench; b5, oxidizing the upper surface of the SiC epitaxial layer and the side wall of the groove at high temperature to form SiO with a second thickness2And oxidizing the layer.
Further, a photoetching process is adopted as a mode for forming the groove by etching in the first step, and plasma dry etching is adopted when the groove is formed by etching; the method for depositing the polysilicon or the amorphous silicon in the second step and the method for depositing the polysilicon or the metal in the trench in the fourth step are chemical vapor deposition or physical vapor deposition.
Further, the photoresist is positive; the photoresist is removed by a wet method or a dry method.
The MOS structure formed by the preparation method based on the thick bottom oxide layer groove MOS is characterized in that: the upper surface of the SiC epitaxial layer is provided with a groove; the bottom of the groove is provided with a concave first thickness medium layer and an inverted convex grid which is positioned above the concave first thickness medium layer and matched with the concave first thickness medium layer; and second-thickness dielectric layers are arranged on the side wall of the groove, between the semiconductor substrate and the grid and on the upper surfaces of the semiconductor substrates on two sides of the groove.
By adopting the preparation method, the preparation of the thick oxide layer is realized by oxidizing the polycrystalline silicon or amorphous silicon at the bottom of the groove, so that the thickness of the oxide layer at the bottom of the groove of the MOS structure is obviously thicker than that of the side wall, the electric field intensity in the groove is effectively reduced, the reliability of the MOSFET of the SiC groove is improved, and meanwhile, the increase of the thickness of the oxide layer at the bottom of the groove is beneficial to reducing the gate-drain capacitance of the MOSFET device of the groove, so that the dynamic loss of the device is reduced, and the switching speed of the.
Drawings
FIG. 1 is a block diagram of step one;
FIG. 2 is a structural diagram of step two;
FIG. 3 is a block diagram of step three A1 after applying photoresist;
FIG. 4 is a structural diagram of step three A1 after photoresist at the bottom of the trench is left;
FIG. 5 is a block diagram of step three A2;
FIG. 6 is a block diagram of step three A3;
FIG. 7 is a block diagram of step three B1;
FIG. 8 is a structural view after step three B2 applying a photoresist;
FIG. 9 is a structural diagram after photoresist at the bottom of the trench is left in step three B2;
FIG. 10 is a block diagram of step three B3;
FIG. 11 is a block diagram of step three B4;
FIG. 12 is a block diagram of steps three A4 and B5;
FIG. 13 is a block diagram of the process at step four.
1. A silicon carbide material epitaxial layer; 2. a trench; 3. polycrystalline silicon or amorphous silicon; 4. photoresist; 5. a first thickness dielectric layer; 6. a dielectric layer with a second thickness; 7. gate polysilicon or metal; 8. a silicon carbide material substrate.
Detailed Description
The present invention will be described below with reference to the accompanying drawings and specific examples, which are conventional unless otherwise specified.
Example 1:
a preparation method of a thick bottom oxide layer groove MOS comprises the following steps:
step S1: etching the upper surface of the SiC epitaxial layer 1 to form a groove 2, as shown in FIG. 1;
step S2: growing a layer of polysilicon or amorphous silicon 3 on the upper surface of the SiC epitaxial layer 1 and the inner wall of the trench 2, as shown in FIG. 2;
step S3: the surface of the polycrystalline silicon or amorphous silicon 3 formed in step S2 is coated with a photoresist 4 and lithographically developed, as shown in fig. 3;
step S4: removing the redundant photoresist 3 on the surface of the polysilicon or amorphous silicon 2 and only remaining the photoresist 4 at the bottom of the trench, as shown in fig. 4;
step S5: etching to remove the exposed polysilicon or amorphous silicon 3 as shown in 5;
step S6: removing the photoresist 4 at the bottom of the trench 2, as shown in fig. 6;
step S7: oxidizing the polysilicon or amorphous silicon 3 at the bottom of the trench 2 at high temperature to form SiO with first thickness2An oxide layer 5 for forming SiO with a second thickness on the upper surface of the SiC epitaxial layer 1 and the side wall of the groove 2 by high-temperature oxidation2An oxide layer 6, as shown in fig. 12;
step S8: polysilicon or metal is deposited in the unfilled portion of the trench 2 and patterned to form a gate 7 of MOS structure, as shown in fig. 13.
Further, the method for forming the trench 2 by etching in step S1 adopts a photolithography process, and plasma dry etching is adopted when the trench 2 is formed by etching; the method of depositing the polysilicon or amorphous silicon 3 in step S4 and the polysilicon or metal of the gate 7 in the trench 2 in step S8 is chemical vapor deposition or physical vapor deposition.
Further, the photoresist 4 adopted in the invention is positive photoresist; the photoresist 3 is removed by a wet method or a dry method; the method for removing the exposed polysilicon or amorphous silicon by etching is wet etching or plasma dry etching.
The MOS structure formed by the preparation method based on the thick bottom oxide layer groove MOS is characterized in that: the upper surface of the SiC epitaxial layer 1 is provided with a groove 2; the bottom of the groove 2 is provided with a concave first thickness medium layer 5 and an inverted convex grid 7 which is positioned above the concave first thickness medium layer 5 and matched with the concave first thickness medium layer; and a second thickness dielectric layer 6 is arranged on the side wall of the groove 2, between the semiconductor substrate 1 and the grid 7 and on the upper surface of the semiconductor substrate 1 on two sides of the groove 2.
Example 2:
a preparation method of a thick bottom oxide layer groove MOS comprises the following steps:
step S1: etching the upper surface of the SiC epitaxial layer 1 to form a groove 2 as shown in 1;
step S2: growing a layer of polysilicon or amorphous silicon 2 on the upper surface of the SiC epitaxial layer 1 and the inner wall of the trench 2, as shown in FIG. 2;
step S3: the polycrystalline silicon or amorphous silicon 3 formed in the step S2 is completely oxidized to a first thickness SiO2 An oxide layer 5, as shown in fig. 7;
step S4: SiO in the first thickness2Coating photoresist 4 on the surface of the oxide layer 5 and carrying out photoetching development, as shown in FIG. 8;
step S5: removing SiO with the first thickness2The photoresist 4 on the surface of the oxide layer 5 is redundant and only the photoresist 4 at the bottom of the trench 2 is remained, as shown in fig. 9;
step S6: corroding to remove exposed SiO with first thickness2An oxide layer 5, as shown in fig. 10;
step S7: removing the photoresist 4 at the bottom of the trench 2, as shown in fig. 11;
step S8: oxidizing the upper surface of the SiC epitaxial layer 1 and the part of the side wall of the groove 2 which is not covered by the oxidation layer at high temperature to form SiO with a second thickness2An oxide layer 6, as shown in fig. 12;
step S9: polysilicon or metal is deposited in the unfilled portion of the trench 2 and patterned to form a gate 7 of MOS structure, as shown in fig. 13.
Further, the method for forming the trench 2 by etching in step S1 adopts a photolithography process, and plasma dry etching is adopted when the trench 2 is formed by etching; the method of growing the layer of polysilicon or amorphous silicon 2 in step S4 and depositing the gate 7 polysilicon or metal in the trench 2 in step S9 is chemical vapor deposition or physical vapor deposition.
Further, the photoresist 4 adopted in the invention is positive photoresist; the photoresist 3 is removed by a wet method or a dry method; etching the exposed first thickness SiO2The method of the oxide layer 5 is wet etching or plasma dry etching.
The MOS structure formed by the preparation method based on the thick bottom oxide layer groove MOS is characterized in that: the upper surface of the SiC epitaxial layer 1 is provided with a groove 2; the bottom of the groove 2 is provided with a concave first thickness medium layer 5 and an inverted convex grid 7 which is positioned above the concave first thickness medium layer 5 and matched with the concave first thickness medium layer; and a second thickness medium layer 6 is arranged on the side wall of the groove 2, between the semiconductor epitaxial layer 1 and the grid 7 and on the upper surface of the semiconductor epitaxial layer 1 at two sides of the groove 2.
The above-mentioned embodiments are further described in detail for the purpose of illustrating the invention, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the invention and are not intended to limit the invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit of the invention should be included in the scope of the invention.
Claims (8)
1. A preparation method of a thick bottom oxide layer groove MOS comprises the following steps:
etching the upper surface of a semiconductor epitaxial layer (1) to form a groove (2);
growing a layer of polycrystalline silicon or amorphous silicon (3) on the upper surface of the semiconductor epitaxial layer (1) and the inner wall of the groove (2);
oxidizing the polycrystalline silicon or amorphous silicon (3) at the bottom of the groove (2) at high temperature to form a first thickness dielectric layer (5), oxidizing the upper surface of the semiconductor epitaxial layer (1) and the side wall of the groove (2) at high temperature to form a second thickness dielectric layer (6), wherein the thickness of the second thickness dielectric layer (6) is smaller than that of the first thickness dielectric layer (5);
and step four, forming a gate (7) of the MOS structure at the part which is not filled in the groove (2).
2. The method of claim 1, wherein the method comprises: the method for forming the groove by etching in the first step adopts a photoetching process, and the groove is formed by etching by a plasma dry method; the mode of depositing the polycrystalline silicon or the amorphous silicon (3) in the second step and the polycrystalline silicon or the metal in the groove (2) in the fourth step is a chemical vapor deposition method or a physical vapor deposition method.
3. The method for preparing a thick bottom oxide layer according to claim 1, wherein: the semiconductor epitaxial layer (1) is made of SiC; the first thickness dielectric layer (5) and the second thickness dielectric layer (6) are both SiO2An oxide layer; the grid (7) is a polysilicon or metal electrode.
4. The method according to any of claims 1 to 3, wherein the method comprises: the method of the third step is as follows: a1 coating photoresist (4) on the surface of the polycrystalline silicon or amorphous silicon (3) formed in the second step, carrying out photoetching development, removing the redundant photoresist (4) and only remaining the photoresist (4) at the bottom of the groove (2); a2 etching to remove polysilicon or amorphous silicon (3) not contacted with the photoresist; a3 removing the photoresist (4) at the bottom of the trench; a4 oxidizing the polysilicon or amorphous silicon (3) at the bottom of the trench (2) at high temperature to form SiO with the first thickness2An oxide layer; a5 the upper surface of the SiC epitaxial layer (1) and the side wall of the groove (2) are oxidized at high temperature to form SiO with the second thickness2And oxidizing the layer.
5. The method according to any of claims 1 to 3, wherein the method comprises: the method of the third step can also be as follows: b1 completely oxidizing the polysilicon or amorphous silicon (3) formed in the second step into SiO with the first thickness2An oxide layer; first thickness SiO formed by oxidizing B22Coating photoresist (4) on the surface of the oxide layer and carrying out photoetching development, removing the redundant photoresist (4) and only reserving the photoresist at the bottom of the groove (2)(4) (ii) a B3 etching to remove SiO in the first thickness not contacted with the photoresist (4)2An oxide layer; b4 removing the photoresist (4) at the bottom of the groove (2); b5, oxidizing the upper surface of the SiC epitaxial layer (1) and the side wall of the groove (2) at high temperature to form SiO with a second thickness2And oxidizing the layer.
6. The method of claim 1 to 5, wherein the method comprises: the photoresist (4) is positive photoresist; the photoresist (4) is removed by a wet or dry method.
7. The method of claim 4, wherein the method comprises: a method for removing the polycrystalline silicon or amorphous silicon (3) which is not contacted with the photoresist (4) in the step A2 by etching is wet etching or plasma dry etching.
8. The method of claim 5, wherein the method comprises: first thickness SiO of B3 not in contact with photoresist (4)2The method of the oxide layer is wet etching or plasma dry etching.
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| CN202010109602.6A CN111180316A (en) | 2020-02-22 | 2020-02-22 | Silicon carbide thick bottom oxide layer groove MOS preparation method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113299748A (en) * | 2021-05-25 | 2021-08-24 | 重庆伟特森电子科技有限公司 | T-gate groove silicon carbide transistor with accumulation type channel structure and manufacturing method thereof |
| CN113506826A (en) * | 2021-06-17 | 2021-10-15 | 重庆伟特森电子科技有限公司 | Groove type silicon carbide transistor and preparation method thereof |
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2020
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