CN111489963B - Preparation method of SiC-MOSFET gate with thick gate oxide layer at corner of trench - Google Patents
Preparation method of SiC-MOSFET gate with thick gate oxide layer at corner of trench Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 50
- 229920005591 polysilicon Polymers 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 24
- 230000003647 oxidation Effects 0.000 claims abstract description 23
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 23
- 229910004298 SiO 2 Inorganic materials 0.000 claims abstract description 21
- 230000001590 oxidative effect Effects 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 28
- 230000008569 process Effects 0.000 claims description 16
- 238000001312 dry etching Methods 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 claims 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 abstract description 36
- 229910010271 silicon carbide Inorganic materials 0.000 abstract description 36
- 230000005684 electric field Effects 0.000 abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 7
- 230000008719 thickening Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0475—Changing the shape of the semiconductor body, e.g. forming recesses
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/048—Making electrodes
- H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Abstract
A preparation method of a SiC-MOSFET gate with a thick gate oxide layer at a groove corner comprises the following steps: 1 etching the upper surface of the epitaxial layer to form a groove; 2 growing polysilicon or amorphous silicon on the upper surface of the epitaxial layer and the inner wall of the trench; 3 depositing SiO which completely covers the upper surface of the epitaxial layer and fills the groove 2 A layer; 4, flattening the upper surface of the epitaxial layer to obtain SiO 2 The upper surface of the layer is flush with the upper surface of the epitaxial layer; 5 etching SiO 2 A layer, wherein the oxide layer at the bottom of the trench is reserved; 6 etching SiO 2 Polysilicon or amorphous silicon above the upper surface level of the layer, and 7 etching the whole SiO at the bottom of the trench 2 A layer; and 8, oxidizing the silicon carbide and the polycrystalline silicon or amorphous silicon exposed on the side wall of the trench at a high temperature to form an oxide layer. By adopting the preparation method of the invention, siO is utilized 2 The polycrystalline silicon or amorphous silicon at the bottom of the oxidation groove plays a role in thickening the oxidation layer at the corner of the groove by replacing photoresist as a mask layer, and the reverse electric field strength bearing capacity at the corner of the groove is increased.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a SiC-MOSFET gate with a thick gate oxide layer at a corner of a groove.
Background
Modern electronic technology puts forward new requirements on semiconductor materials such as high voltage, high frequency, high power, high temperature, radiation resistance and the like, while the wide-bandgap third-generation semiconductor material SiC has the advantages of wide forbidden band, high critical breakdown electric field, high saturated electron mobility, high melting point, high thermal conductivity and the like, and is an ideal material for preparing power electronic devices. In the SiC switch device, the SiC-MOSFET has the advantages of high switching speed, high voltage resistance, low power consumption and the like, the SiC-MOSFET is mainly divided into a planar type and a groove type, and because the groove type device adopts a vertical channel, the electron mobility is higher and the JFET effect does not exist.
However, because the critical breakdown electric field intensity of the silicon carbide is higher, the electric field intensity of a gate oxide layer at the corner of the groove type SiC-MOSFET is often very high, and when the electric field intensity exceeds the range which can be borne by the oxide layer, destructive failure of a device is easily caused.
In the groove type SiC-MOSFET, because the used semiconductor silicon carbide wafer is generally in the (0001) crystal orientation, the oxidation rate of the (0001) crystal plane at the bottom of the device groove is obviously lower than that of the side wall of the groove, and the thickness of the oxide layer at the side wall of the groove is influenced by the threshold voltage and cannot be thickened, so that when the side wall and the bottom of the groove are oxidized simultaneously, the thickness of the oxide layer at the bottom of the groove, including the corner of the groove, is thinner, the defect that the electric field intensity of the gate oxide layer at the corner of the groove type SiC-MOSFET is high is further exposed, and the condition is further worsened.
In view of the above drawbacks, the prior art solutions are mainly as follows: 1. product designers make some compromises and sacrifices in device performance; 2. a special crystal structure is adopted; 3. the local electric field is weakened in a mode of changing the doping concentration at the bottom of the groove; 4. and increasing the oxidation rate of the silicon carbide material at the bottom of the trench by means of ion implantation. These improvements can significantly increase the complexity and cost of the process, and impose significant design constraints.
Disclosure of Invention
The invention aims to provide a preparation method of a SiC-MOSFET gate with a thick gate oxide layer at a groove corner.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
the preparation method of the SiC-MOSFET gate with the thick gate oxide layer at the corner of the trench comprises the following steps:
step S1: carrying out patterning treatment on the SiC epitaxial layer to etch the upper surface of the SiC epitaxial layer to form a groove, wherein the depth range of the groove is 0.3-100um, and the width range of the opening is 0.3-5um;
step S2: growing a layer of polycrystalline silicon or amorphous silicon on the upper surface of the SiC epitaxial layer and the inner wall of the groove formed by the graphical treatment in an isotropic way, wherein the thickness of the polycrystalline silicon or amorphous silicon is 2-800nm;
and step S3: deposition of SiO 2 The layer is made to completely cover the upper surface of the SiC epitaxial layer and is filled with the groove formed by the patterning treatment;
and step S4: the upper surface of the SiC epitaxial layer is flattened by the semiconductor processing technology such as CMP or dry etching, and the amorphous silicon polysilicon or amorphous silicon and SiO in the groove are reserved 2 Layer of SiO so that SiO remains 2 The upper surface of the layer is flush with the upper surface of the SiC epitaxial layer;
step S5: by using high SiO 2 SiO by/Si selection ratio dry etching process 2 Etching, etching part of SiO reserved in step S4 2 Layer of SiO remaining in the trenches to a depth below 2 A layer;
step S6: etching all polycrystalline silicon or amorphous silicon on the upper surface of the SiC epitaxial layer and polycrystalline silicon or amorphous silicon on the side wall part of the groove, which is not covered by the reserved silicon dioxide layer, wherein the polycrystalline silicon or amorphous silicon reserved at the bottom of the groove and on the side wall of the groove forms a concave structure after the etching is finished;
step S7: using SiO with high selectivity 2 Dry or wet etching of Si SiO all at the bottom of the trench remaining in step S5 2 Reserving polycrystalline silicon or amorphous silicon which is formed by the bottom of the groove and the side wall of the groove in the step S6 and is in a concave structure;
step S8: simultaneously oxidizing the SiC exposed on the side wall of the groove and the polysilicon or amorphous silicon reserved in the step S7 at high temperature, and oxidizing the polysilicon or amorphous silicon to form SiO 2 SiO formed by SiC oxidation of layer thickness larger than groove side wall 2 Layer thickness, and trench sidewall SiC oxidation formed SiO 2 The layer thickness is 30-100nm.
In the preparation method of the invention, siO is firstly utilized 2 The photoresist is replaced to be used as a mask layer, so that the phenomenon of photoresist floating generated in the corrosion process of the photoresist is compensated, and meanwhile, the device is prevented from being damaged in the subsequent etching process; then removing redundant polysilicon and amorphous silicon; finally, the remaining polysilicon or amorphous silicon is oxidized together with the silicon carbide. The remained oxidation products of the polysilicon and the amorphous silicon play a role of thickening the oxidation layer at the corner of the grooveThe effect of (2) is not as the gate oxide, and the reverse electric field intensity bearing capacity at the corner of the groove is increased, so that the problem that the gate oxide at the intersection angle of the side wall of the groove type SiC-MOSFET groove and the bottom of the groove bears the reverse electric field intensity too much in the prior art is solved.
Drawings
Fig. 1 is a schematic structural diagram after step S3 is completed.
Fig. 2 is a schematic structural diagram after step S4 is completed.
Fig. 3 is a schematic structural diagram after step S5 is completed.
FIG. 4 is a schematic diagram of a step S6.
Fig. 5 is a schematic structural diagram after step S7 is completed.
Fig. 6 is a schematic structural diagram after step S8 is completed.
Fig. 7 is a schematic structural diagram of the trench type SiC-MOSFET gate in step S5.
Fig. 8 is a schematic structural diagram of the trench type SiC-MOSFET gate in step S8.
1, siC epitaxial layer; 2. polycrystalline silicon or amorphous silicon; 3. deposited SiO 2 A layer; 4. SiO formed by oxidizing polysilicon or amorphous silicon 2 A layer; siO formed by oxidation of SiC 2 A layer; 6. a source region.
Detailed Description
The following describes a method for manufacturing a trench silicon carbide MOSFET gate for improving the reverse electric field strength endurance of a gate oxide layer at a trench corner according to the present invention with reference to the accompanying drawings and the detailed description.
A preparation method of a SiC-MOSFET gate with a thick gate oxide layer at a groove corner comprises the following steps:
step S1: carrying out patterning treatment on the SiC epitaxial layer 1 to etch the upper surface of the SiC epitaxial layer 1 to form a groove, wherein the depth range of the groove is 0.3-100um, and the width range of an opening is 0.3-5um;
wherein, the preferable range of the depth of the groove is 0.5-90um; the more preferable range is 5-70um; preferably in the range of 10-40um;
wherein, the preferred range of the opening width is 0.5-4um; the more preferable range is 1-3um; preferably in the range of 1.5-2um;
the depth and the width of the opening of the groove have influence on the electrical properties of the device such as on-resistance, leakage current, threshold voltage, breakdown voltage and the like, and finally influence the quality of the device.
Step S2: growing a layer of polysilicon or amorphous silicon 2 on the upper surface of the SiC epitaxial layer 1 and the inner wall of the groove formed by the graphical treatment, wherein the thickness of the polysilicon or amorphous silicon 2 is 2-800nm;
and step S3: deposition of SiO 2 A layer 3, which completely covers the upper surface of the SiC epitaxial layer 1 and fills the trench formed by the patterning process, as shown in fig. 1;
and step S4: the upper surface of the SiC epitaxial layer 1 is flattened, and polysilicon or amorphous silicon 2 and SiO in the groove are reserved 2 Layer 3, so that SiO remains 2 The upper surface of layer 3 is flush with the upper surface of the SiC epitaxial layer 1, as shown in fig. 2 in particular;
step S5: by using high SiO 2 SiO by/Si selection ratio dry etching process 2 Etching, namely etching part of SiO reserved in the step S4 2 Layer 3, siO remaining below a certain depth in the covered trench 2 Layer 3, as shown in particular in fig. 3;
step S6: etching all polycrystalline silicon or amorphous silicon 2 on the upper surface of the SiC epitaxial layer 1 and polycrystalline silicon or amorphous silicon 2 on the side wall part of the groove, which is not covered by the reserved silicon dioxide layer, wherein the polycrystalline silicon or amorphous silicon 2 reserved at the bottom of the groove and on the side wall of the groove is in a concave structure after the etching is finished, and is particularly shown in figure 4;
step S7: using SiO with high selectivity 2 Dry or wet etching of Si to leave all SiO at the bottom of the trench in step S5 2 A layer 3, which is the polycrystalline silicon or amorphous silicon 2 in the concave structure formed by the bottom of the trench and the sidewall of the trench in the step S6, and is specifically shown in fig. 5;
step (ii) ofS8: simultaneously oxidizing the SiC exposed on the side wall of the groove and the polysilicon or amorphous silicon 2 reserved in the step S7 at high temperature, and oxidizing the polysilicon or amorphous silicon 2 to form SiO 2 The thickness of the layer 4 is larger than that of SiO formed by SiC oxidation of the side wall of the groove 2 Layer 5 thickness, and trench sidewall SiC oxidation formed SiO 2 The thickness of the layer 5 is 30-100nm, preferably in the range of 35-90nm; more preferably in the range of 40-75nm; preferably in the range of 45-60nm, as shown in FIG. 6.
Further, in step S1, the trench is formed by etching using a photolithography process, wherein the trench is formed by etching using a plasma dry method, and the trench angle is 70 to 90 degrees o 。
Further, in step S2, the polycrystalline silicon or amorphous silicon 2 is grown isotropically by the chemical vapor deposition method on the inner wall of the trench.
Further, in step S4, the method adopted for performing planarization treatment on the upper surface of the SiC epitaxial layer 1 is CMP process or back etching of anisotropic dry etching; endpoint detection may also be used during or/and after the planarization process.
Further, in step S8, polysilicon or amorphous silicon 2 is oxidized to form SiO 2 The thickness of the layer 3 is 30-1500nm, preferably 75-1000nm; more preferably 150-800nm; the best range is 200-500nm, in the preparation method of the invention, the last step is to oxidize the remaining polysilicon or amorphous silicon and silicon carbide together, the oxidation products of the remaining polysilicon and amorphous silicon play a role in thickening the oxidation layer at the corner of the trench, and the reverse electric field strength bearing capacity at the corner of the trench is increased to obtain a device with higher performance 2 Layer 3 thickness, in accordance with preferred, better and best ranges, device performance improves in order and device performance is optimized within the best ranges.
Further, in step S8, the high temperature oxidation is carried out at 600-2000 deg.C to completely oxidize the polysilicon or amorphous silicon 2 to SiO 2 The oxidizing gas of layer 3 is dry oxygen, wet oxygen, NO, N 2 O or NO 2 One or more than one of them.
Further, after the step S8 is completed, all the residual polysilicon or amorphous silicon 2 is oxidized, and after a thick oxide film is formed at the corner of the bottom of the trench, a wet etching process may be used to etch away SiO formed by SiC oxidation on the sidewall of the trench 2 Layer 5, the oxide film thickness at the bottom corners is correspondingly thinned, but still remains. And then, the SiC gate oxidation process is carried out again, and the thickness of the gate oxide film required by the MOSFET channel is grown.
Further, as shown in fig. 7, in step S5, in the structure of the trench type SiC-MOSFET gate, the doping type of the source region 6 is opposite to that of the SiC epitaxial layer 1, and the certain depth refers to the vertical depth H between the upper surface of the SiC epitaxial layer 1 and the lower surface of the source region 6, that is, the SiO remained after etching 2 The upper surface of layer 3 is below the lower surface of source region 6.
Further, in step S8, in the structure of the trench type SiC-MOSFET gate shown in FIG. 8, after the oxidation is completed, the polysilicon or amorphous silicon 2 is oxidized to form SiO 2 Layer 4 below a certain depth H, i.e. in the vertical direction, siO formed by oxidation of polycrystalline or amorphous silicon 2 2 The upper surface of layer 4 is below the lower surface of source region 6.
In the preparation method of the invention, siO is firstly utilized 2 The photoresist is replaced to be used as a mask layer, so that the phenomenon of photoresist floating generated in the corrosion process of the photoresist is compensated, and meanwhile, the device is prevented from being damaged in the subsequent etching process; then removing redundant polysilicon and amorphous silicon; finally, the remaining polysilicon or amorphous silicon is oxidized together with the silicon carbide. The reserved oxidation products of the polycrystalline silicon and the amorphous silicon play a role in thickening the oxidation layer at the corner of the groove, are not used as the gate oxide, increase the reverse electric field strength bearing capacity at the corner of the groove, and solve the problem that the gate oxide at the intersection of the side wall of the groove type SiC-MOSFET groove and the bottom of the groove bears the too high reverse electric field strength in the prior art.
The above-mentioned embodiments are further described in detail for the purpose of illustrating the invention, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the invention and are not intended to limit the invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit of the invention should be included in the scope of the invention.
Claims (6)
1. A preparation method of a SiC-MOSFET gate with a thick gate oxide layer at a groove corner is characterized by comprising the following steps:
step S1: carrying out patterning treatment on the SiC epitaxial layer (1) to etch the upper surface of the SiC epitaxial layer (1) to form a groove, wherein the depth range of the groove is 0.3-100um, and the opening width range is 0.3-5um;
step S2: growing a layer of polycrystalline silicon or amorphous silicon (2) on the upper surface of the SiC epitaxial layer (1) and the inner wall of the groove formed by patterning treatment, wherein the thickness of the polycrystalline silicon or amorphous silicon is 2-800nm;
and step S3: deposition of SiO 2 The layer (3) completely covers the upper surface of the SiC epitaxial layer (1) and is filled with a groove formed through patterning treatment;
and step S4: the upper surface of the SiC epitaxial layer (1) is flattened, and polysilicon or amorphous silicon (2) and SiO in the groove are reserved 2 Layer (3) of SiO remaining 2 The upper surface of the layer (3) is flush with the upper surface of the SiC epitaxial layer (1);
step S5: by using high SiO 2 SiO by/Si selection ratio dry etching process 2 Etching, etching part of SiO reserved in step S4 2 A layer (3) of SiO remaining covering the trench to a depth below 2 A layer (3); step S6: etching all polycrystalline silicon or amorphous silicon (2) on the upper surface of the SiC epitaxial layer (1) and polycrystalline silicon or amorphous silicon (2) on the side wall part of the groove, which is not covered by the reserved silicon dioxide, and forming a concave structure by the polycrystalline silicon or amorphous silicon (2) reserved at the bottom of the groove and the side wall of the groove after the etching is finished;
step S7: using SiO with high selectivity 2 Dry or wet etching of Si SiO all at the bottom of the trench remaining in step S5 2 A layer (3) which retains the polycrystalline silicon or amorphous silicon (2) which is formed by the bottom of the groove and the side wall of the groove in the step S6 and has a concave structure;
step S8: simultaneously oxidizing the SiC exposed on the side wall of the groove and the polysilicon or amorphous silicon (2) reserved in the step S7 at a high temperature, and oxidizing the polysilicon or amorphous silicon (2) to form SiO 2 The thickness of the layer (4) is larger than that of SiO formed by SiC oxidation of the side wall of the groove 2 Layer (5) thickness and trench sidewall SiC oxidation formed SiO 2 The thickness of the layer (5) is 30-100nm.
2. The method of claim 1, wherein the method comprises the steps of: in step S1, the mode of etching to form the groove adopts a photoetching process, plasma dry etching is adopted when the groove is formed by etching, and the groove angle is 70-90 DEG o 。
3. The method of claim 1 for fabricating a SiC-MOSFET gate having a thick gate oxide at a trench corner, wherein: in step S2, the polycrystalline silicon or amorphous silicon (2) is grown isotropically in the trench by chemical vapor deposition.
4. The method of claim 1, wherein the method comprises the steps of: in step S4, the planarization treatment of the upper surface of the SiC epitaxial layer (1) is performed by a CMP process or an anisotropic dry etching etch back.
5. The method of claim 1 for fabricating a SiC-MOSFET gate having a thick gate oxide at a trench corner, wherein: in step S8, polysilicon or amorphous silicon 2 is oxidized to form SiO 2 The thickness of the layer (3) is 30-1500nm.
6. The method of claim 1, wherein the method comprises the steps of: in step S8, the high-temperature oxidation is carried out at 600-2000 ℃, and polycrystalline silicon or amorphous silicon (2) is completely oxidized into SiO 2 Oxidizing gas of layer (3)The body is dry oxygen, wet oxygen, NO, N 2 O or NO 2 One or more than one of them.
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