CN218867114U - Shielding gate groove type power MOSFET device - Google Patents

Abstract

The utility model provides a shielding gate slot type power MOSFET device. The device comprises a semiconductor substrate, a drain metal layer positioned below the semiconductor substrate and a source metal layer positioned on the semiconductor substrate. The semiconductor substrate has a lower surface and an upper surface. The semiconductor substrate is in short circuit with the drain electrode metal layer through the lower surface. The semiconductor substrate is provided with at least one group of trenches extending in parallel at the upper surface, wherein each trench is filled with polysilicon, and an oxide layer is formed between the polysilicon and the corresponding trench wall. The at least one group of trenches includes a gate trench and shield gate trenches located on both sides of the gate trench. The polycrystalline silicon in the shielding grid groove is in short circuit with the source electrode metal layer, and the polycrystalline silicon in the grid groove is not in short circuit with the source electrode metal layer. The thickness of the oxide layer of the shielding grid groove is larger than that of the oxide layer of the grid groove.

Description

Shielding gate groove type power MOSFET device

Technical Field

The utility model relates to a slot type power MOSFET device field particularly, relates to a shielding grid slot type power MOSFET device.

Background

Modern power electronics are moving towards high power density and high efficiency. Silicon carbide (SiC) power devices have been rapidly developed in the field of high-efficiency power conversion in recent years due to their excellent device characteristics such as high voltage, high frequency, high temperature, and high power density. Silicon carbide power MOSFET devices are the fastest growing devices in this field. Structurally, it has both planar and trench types. The groove type power MOSFET device has the advantages of high integration level, low on-resistance, high switching speed, small switching loss and the like, almost comprehensively replaces a plane type power MOSFET device in the fields of low voltage and high voltage, and becomes the mainstream of relevant application. With the wide expansion of application fields and the continuous improvement of equipment performance, people have higher and higher requirements on the reliability of the trench type power MOSFET device. However, trench power MOSFET devices suffer from trench etch defects, which cause the gate oxide of the trench (especially the gate oxide at the bottom of the trench) to be easily broken down, which limits their application in high reliability scenarios.

Conventional trench power MOSFET devices gradually exhibit the disadvantage of insufficient reliability. Conventional devices are typically represented by the Rohm and English-flying related products. They protect the trench bottom gate oxide by early depletion of the deep body junction. The body tie is located below the groove in the longitudinal direction. When the device bears reverse withstand voltage, the depletion layer expands until the depletion layers on two sides of the groove are mutually closed to protect the gate oxide layer of the groove. Thus, the body junction is closer to the bottom of the trench, and the depth of the body junction needs to be precisely controlled during manufacturing. If the depth of the body knot is too small, the surge capacity of the protection weakening device is weakened; if the depth of the body junction is too large, the breakdown voltage of the device is reduced. Moreover, the body junction depletes the accumulation region of the trench, causing the on-resistance of the device to increase.

Accordingly, there is a need in the art to provide a novel gate structure design for trench power MOSFET devices to solve the aforementioned problems.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a novel shielding grid slot type power MOSFET device, its electric field distribution that can optimize reverse off-state grid slot bottom down promotes the anti avalanche ability of device, improves the reliability of device, expands its applied scene.

The utility model discloses a novel shielding bars slot type power MOSFET device solve aforementioned technical problem. Furthermore, the utility model discloses can also solve or alleviate other technical problem that exist among the prior art.

Particularly, the utility model provides a shielded gate slot type power MOSFET device, include the semiconductor substrate, be located drain electrode metal level under the semiconductor substrate and being located source electrode metal level on the semiconductor substrate, the semiconductor substrate has lower surface and upper surface, the semiconductor substrate via the lower surface with drain electrode metal level short circuit, the semiconductor substrate is in upper surface department is formed with parallel extension's at least a set of slot, and every ditch inslot wherein is filled has polycrystalline silicon, be formed with the oxidation layer between polycrystalline silicon and the corresponding ditch groove wall, wherein at least a set of slot includes the grid slot and is located the shielded gate slot of grid slot both sides, shielded gate slot's polycrystalline silicon with source electrode metal level short circuit, grid slot's polycrystalline silicon not with source electrode metal level short circuit, shielded gate slot's oxide layer thickness is greater than the oxide layer thickness of grid slot.

Optionally, according to an embodiment of the present invention, a portion of the upper surface of the semiconductor substrate forms a bulk junction via ion implantation, such that the bottom wall and the sidewall of the shield gate trench are both in direct communication with the bulk junction.

Optionally, according to an embodiment of the present invention, the body junction is shorted with the source metal layer.

Optionally, according to an embodiment of the present invention, a width of the shielding gate trench is greater than a width of the gate trench.

Optionally, according to an embodiment of the present invention, a depth of the shielding gate trench is greater than a depth of the gate trench.

Optionally, according to an embodiment of the present invention, the depth of the shielding gate trench is 2 times to 4 times the depth of the gate trench.

Optionally, according to an embodiment of the present invention, a depth of the shielding gate trench is greater than 4 times a depth of the gate trench.

Optionally, according to an embodiment of the present invention, a depth of the gate trench is in a range between 0.5 micrometers and 1.5 micrometers.

Optionally, according to an embodiment of the present invention, a thickness of the oxide layer of the shield gate trench is in a range between 1000 angstroms and 9000 angstroms, and a thickness of the oxide layer of the gate trench is in a range between 300 angstroms and 600 angstroms.

Optionally, according to an embodiment of the present invention, the semiconductor substrate includes a substrate and an epitaxial layer on the substrate, the substrate is shorted with the drain metal layer via a lower surface of the substrate, and the at least one set of trenches is formed at an upper surface of the epitaxial layer.

Benefits of the provided shielded gate trench power MOSFET device include: the method is characterized in that deeper shielding grid grooves are additionally arranged on two sides of the grid groove, a thick oxide layer is formed in the shielding grid grooves and is in short circuit with a source metal layer, so that when a device is reversely cut off, a body junction is exhausted at the bottom of the shielding grid grooves in advance, the grid oxide layer is protected, meanwhile, the thick oxide layer also provides higher voltage resistance to prevent the shielding grid from being broken down, and therefore the purposes of improving the anti-avalanche capability of the device, improving the reliability of the device and expanding the application scene of the device are achieved.

Drawings

The above and other features of the invention will become apparent with reference to the accompanying drawings, in which:

fig. 1 shows a partial schematic diagram of one embodiment of a shielded gate trench power MOSFET device according to the present invention, with the source metal layer not shown;

fig. 2 showsbase:Sub>A cross-sectional view of the shielded gate trench power MOSFET device of fig. 1 along linebase:Sub>A-base:Sub>A;

fig. 3 shows a partial schematic diagram of another embodiment of a shielded gate trench power MOSFET device according to the present invention, wherein the source metal layer is not shown;

fig. 4 showsbase:Sub>A cross-sectional view of the shielded gate trench power MOSFET device of fig. 3 along linebase:Sub>A-base:Sub>A; and

fig. 5 shows a cross-sectional view of the shielded gate trench power MOSFET device of fig. 3 along line B-B.

In the drawings, the same reference numerals are used to designate the same components or structures.

Parts list

1. Source metal layer

2. Source injection layer

3. Grid polysilicon

4. Polysilicon in shielded gate trench

5. Oxide layer of shielded gate trench

6. And (4) forming a body knot.

Detailed Description

It is easily understood that, according to the technical solution of the present invention, under the spirit of the present invention, a person skilled in the art can propose various alternative structural modes and implementation modes. Therefore, the following detailed description and the accompanying drawings are merely illustrative of the technical solutions of the present invention, and should not be considered as all or limiting the technical solutions of the present invention.

The terms upper, lower, bottom, top and the like in the description, or may be referred to, are defined relative to the structures shown in the drawings, and are relative terms, and thus may be changed according to the position and the use state. Therefore, these and other directional terms should not be construed as limiting terms.

Furthermore, the terms "first," "second," and the like, are used for descriptive and differential purposes only and are not to be construed as indicating or implying relative importance of the respective components.

As used herein, the term "communicate" is to be construed broadly unless otherwise expressly specified or limited. For example, "communication" may be fixed communication, may be detachable communication, or may be integral communication; it may be directly connected or indirectly connected via an intermediate.

As used herein, the term "shorted" means that the resistance of the communication between the two is made low, e.g., slightly greater than zero. It may be directly connected or indirectly connected via a conductor such as a metal.

As used herein, an amount modified by the term "about" or the like is not limited to the precise amount specified, but may be within, for example, 10% error of the precise amount specified.

Referring to fig. 1, there is shown a partial schematic diagram of one embodiment of a shielded gate trench power MOSFET device according to the present invention. Wherein the source metal layer on the semiconductor substrate is not shown in fig. 1 in order to clearly show the arrangement of elements at the upper surface of the semiconductor substrate.

As shown in fig. 1, the shielded gate trench power MOSFET device of the present invention is formed with at least one set of trenches extending in parallel at the upper surface of a semiconductor substrate. The at least one set of trenches may be divided into a gate trench in the middle and a shield gate trench on both sides of the gate trench. The shield gate trench is filled with polysilicon, which constitutes a shield gate, also referred to as a split gate. The polysilicon in the shield gate trench may be shorted to a source metal layer located on the semiconductor substrate. A thick oxide layer may be formed between the polysilicon in the shield gate trench and the trench wall of the corresponding shield gate trench. The gate trench is also filled with polysilicon, which is referred to as gate polysilicon or gate polysilicon. The gate polysilicon corresponds to the gate of the device and is not shorted to the source metal layer. A thin oxide layer may be formed between the gate polysilicon and the trench walls of the respective gate trenches. Furthermore, the body junction in the semiconductor substrate may be shorted to a source metal layer, as will be described further below. In fig. 1, the junction between the source metal layer and the body junction is along the trench extension direction.

The cross-sections of the shielded gate trench power MOSFET device in fig. 1 perpendicular to the direction of extension of the trench at different positions in the direction of extension of the trench are substantially identical. Therefore, only one of the sections need be described. base:Sub>A cross-section alongbase:Sub>A linebase:Sub>A-base:Sub>A perpendicular to the direction of extension of the trench is shown in fig. 2, which will be described further below.

Referring to fig. 2, there is shownbase:Sub>A cross-sectional view of the shielded gate trench power MOSFET device of fig. 1 along linebase:Sub>A-base:Sub>A. As shown in fig. 2, the shielded gate trench type power MOSFET device of the present invention may include a drain metal layer, a semiconductor substrate, and a source metal layer 1 in this order from bottom to top. The drain metal layer is positioned below the semiconductor substrate, the source metal layer 1 is positioned on the semiconductor substrate, and the semiconductor substrate is positioned between the drain metal layer and the source metal layer 1. The semiconductor substrate has a lower surface and an upper surface. The semiconductor substrate may be shorted to the drain metal layer via the lower surface. The semiconductor substrate may be formed with at least one set of trenches extending in parallel at the upper surface. The semiconductor substrate may then be divided into a substrate and an epitaxial layer on the substrate. Like this, the utility model discloses a shielded gate slot type power MOSFET device can include drain electrode metal level, substrate, epitaxial layer and source electrode metal level 1 in proper order from bottom to top. Wherein the material of the substrate and the epitaxial layer may be silicon, silicon carbide, gallium arsenide, gallium nitride, other group V semiconductor materials, group III-V semiconductor materials, or group II-VI semiconductor materials. The materials of the substrate and the epitaxial layer may be the same or different. The drain metal layer and the source metal layer 1 may be made of the same material or different materials. The substrate may be shorted to the drain metal layer via the lower surface, and the at least one set of trenches may be formed at an upper surface of the epitaxial layer. Each of which may be filled with polysilicon, an oxide layer may be formed between the polysilicon and the respective trench wall. In particular, an oxide layer may be formed between the polysilicon and the bottom and sidewalls of the respective trenches.

As shown in fig. 2, the shielded gate trench power MOSFET device of the present invention can form at least one set of trenches extending in parallel at the upper surface of the epitaxial layer via a photolithography process. As described above, a thick oxide layer may be formed between the polysilicon 4 in the shield gate trench and the trench wall of the corresponding shield gate trench. In particular, a thick oxide layer may be formed between the polysilicon 4 within the shield gate trenches and the bottom wall and/or sidewalls of the respective shield gate trenches. Preferably, a thick oxide layer is formed at both the bottom wall and the sidewalls of the shield gate trench. For example, a thick oxide layer is formed at the bottom wall and sidewalls of the shield gate trench by chemical vapor deposition or direct thermal oxygen growth. As described above, a thin oxide layer may be formed between the gate polysilicon 3 and the trench wall of the corresponding gate trench. Specifically, a thin oxide layer may be formed between the gate polysilicon 3 and the bottom wall and the side wall of the corresponding gate trench.

As shown in fig. 2, in the shielded gate trench type power MOSFET of the present invention, the thickness of the oxide layer 5 of the shielded gate trench is greater than the thickness of the oxide layer of the gate trench. Preferably, the thickness of the oxide layer 5 of the shield gate trench is much greater than that of the oxide layer of the gate trench, so as to effectively reduce the electric field intensity at the bottom of the trench and prevent the gate trench from being broken down in advance while protecting the gate trench. The thickness of the oxide layer 5 of the shield gate trench may be approximately in the range between 1000 angstroms and 9000 angstroms. Alternatively, the thickness of the oxide layer 5 of the shield gate trench may be about 5000 angstroms. The oxide layer thickness of the gate trench may be approximately in the range of 300 angstroms to 600 angstroms. Alternatively, the oxide layer thickness of the gate trench may be approximately 450 angstroms. As is well known to those skilled in the art, 1 Angstrom equals 10 ^-10 And (4) rice.

As shown in fig. 2, in the shielded gate trench type power MOSFET device of the present invention, the design size of the shielded gate trench can be larger than that of the gate trench. Specifically, the width of the shield gate trench may be greater than the width of the gate trench, and the depth of the shield gate trench may be greater than the depth of the gate trench. When the groove is etched, the etching speed of the large-size groove is higher than that of the small-size groove, so that the design that the size of the shielding grid groove is larger than that of the grid groove can be just realized. As such, the shield gate trench and the gate trench may be formed via the same etch. In practical production processes, the dimensions of the shield gate trench and the gate trench are also determined with specific reference to the thickness of the thick oxide layer and practical requirements. The depth of the gate trench may be approximately in the range between 0.5 microns and 1.5 microns. Alternatively, the depth of the gate trench may be about 1 micron. The shield gate trench may have a depth that is about 2 to 4 times greater than the depth of the gate trench, or greater than 4 times the depth of the gate trench. Alternatively, the depth of the shield gate trench may be about 3 times the depth of the gate trench. By introducing a deep shield gate trench, better protection of the gate trench can be achieved.

As shown in fig. 2, in the shielded gate trench type power MOSFET device of the present invention, a portion of the upper surface of the semiconductor substrate forms a body junction 6 via ion implantation, so that both the bottom wall and the side wall of the shielded gate trench directly communicate with the body junction 6. The ion implantation may be a P-type implantation or an N-type implantation. The body junction 6 may be shorted to a source metal layer 1 located on the semiconductor substrate. As shown in fig. 2, the body junction 6 and the source metal layer 1 have a source injection layer 2 therebetween, and the body junction 6 may be shorted with the source metal layer 1 via a metal conductor passing through the source injection layer 2.

Referring to fig. 3, there is shown a partial schematic diagram of another embodiment of a shielded gate trench power MOSFET device according to the present invention. Wherein the source metal layer on the semiconductor substrate is not shown in fig. 3 in order to clearly show the arrangement of elements at the upper surface of the semiconductor substrate.

As described above, in fig. 1, the connection portion between the source metal layer and the body junction is along the trench extending direction. In fig. 3, the connection between the source metal layer and the body junction is along a direction perpendicular to the direction in which the trench extends. Thus, unlike fig. 1, the cross-section of the shielded gate trench power MOSFET device in fig. 3 perpendicular to the direction of trench extension has at least two different shapes. The cross-section alongbase:Sub>A linebase:Sub>A-base:Sub>A perpendicular to the direction of extension of the trench is shown in fig. 4 and the cross-section alongbase:Sub>A line B-B perpendicular to the direction of extension of the trench is shown in fig. 5, which will be described further below.

Referring to fig. 4,base:Sub>A cross-sectional view of the shielded gate trench power MOSFET device of fig. 3 along linebase:Sub>A-base:Sub>A is shown. The cross-sectional view shown in fig. 4 does not pass through the connection between the source metal layer 1 and the bulk junction 6. As shown in fig. 4, a source injection layer 2 is provided between the body junction 6 and the source metal layer 1. The polysilicon 4 in the shield gate trench may be shorted to the source metal layer 1 located on the semiconductor substrate. Specifically, the polysilicon 4 in the shield gate trench may be directly connected to the source metal layer 1 on the semiconductor substrate. The gate poly 3 corresponds to the gate of the device and is not shorted to the source metal layer 1. The thickness of the oxide layer 5 of the shield gate trench is greater than the thickness of the oxide layer of the gate trench.

Referring to fig. 5, a cross-sectional view of the shielded gate trench power MOSFET device of fig. 3 along line B-B is shown. Similar to fig. 4, the polysilicon in the shield gate trench may be shorted to a source metal layer located on the semiconductor substrate. Specifically, the polysilicon in the shield gate trench may be directly connected to a source metal layer located on the semiconductor substrate. The gate polysilicon corresponds to the gate of the device and is not shorted to the source metal layer. Unlike fig. 4, the cross-sectional view shown in fig. 5 passes through the connection between the source metal layer and the bulk junction. As shown in fig. 5, the body junction may be shorted to a source metal layer located on the semiconductor substrate. In particular, in the present invention, the body junction may be directly connected to a source metal layer located on the semiconductor substrate. In the prior art, the body junction is floating, and the oxide layer at the sidewall of the shield gate trench is easier to break down. And in the utility model discloses in, body knot and source electrode metal level short circuit surround whole shielding grid slot, so when bearing reverse withstand voltage, the layer of exhausting exhausts the broadening fast to protect the grid slot more effectively, and avoided grid slot bottom to pour into the Jfet effect of introducing.

The utility model discloses a shielded gate slot type power MOSFET device can be prepared through following step.

And step A, feeding a substrate, depositing a hard mask, and then photoetching. Wherein the shield gate trench CD may be about 2 microns and the gate trench CD may be about 1 micron.

And step B, dry etching the hard mask, and then removing the photoresist.

And C, dry etching the groove. Wherein the shield gate trench may be about 1.5 microns to 2 microns deep and the gate trench may be about 1 micron deep.

And D, removing the hard mask by a wet method, and then cleaning the groove.

And E, depositing a thick oxide layer. For example, by chemical vapor deposition, to about 3000 angstroms.

And F, photoetching. And filling the gate trench with photoresist, and opening the shield gate trench upwards. This is easier to achieve using a negative photoresist.

And G, performing P-type implantation. For example, al is used at 1E13 to implant at an angle of about 7 degrees.

And H, removing the photoresist.

And step I, photoetching. And filling the shield grid groove with photoresist, and opening the grid groove upwards. This is easier to achieve using a negative photoresist.

And step J, wet etching is carried out to remove the oxide layer in the grid groove.

And step K, removing the photoresist.

And L, depositing a grid oxide layer. For example, by chemical vapor deposition, up to about 500 angstroms, and using N ₂ And O, annealing treatment.

And M, depositing polysilicon in the shielding gate groove and the gate groove.

And N, carrying out chemical mechanical polishing on the polycrystalline silicon deposited in the step M until the polycrystalline silicon reaches the surface of the thick oxide layer of the shielding grid.

And step O, carrying out back etching treatment on the polycrystalline silicon until the polycrystalline silicon reaches the surface of the grid oxide layer.

And P, carrying out back etching treatment or chemical mechanical polishing on the silicon oxide until the silicon oxide reaches the surface of the silicon carbide.

And step Q, arranging the body junction, the source electrode injection layer, the source electrode metal and the contact hole. Step Q is identical to the standard preparation process and will not be described further.

Those skilled in the art will appreciate that the references to source and drain in this specification are relative concepts, not absolute concepts. In various specific applications, the source may be used as the drain, and the drain may be used as the source. For convenience of understanding the technical solution of the present invention, "source" and "drain" are still used, but not limited to source and drain, but rather denote a first electrode and a second electrode having two different potential poles. When the device is in forward conduction, electrons flow from the source to the drain; when the device is turned on in the reverse direction, electrons flow from the drain to the source.

It will be appreciated by those skilled in the art that the shielded gate trench power MOSFET device of the present invention may be either an N-type device or a P-type device. It will also be appreciated by those skilled in the art that although only one set of parallel extending trenches is shown in the drawings, including one gate trench in the middle and two shield gate trenches of the same size on the left and right sides of the gate trench, respectively, the shield gate trench power MOSFET device of the present invention may have two or more sets of parallel extending trenches and may have at least one shield gate trench of the same size or of a different size on the left and/or right side of the gate trench.

To sum up, compare with traditional device, the utility model discloses a shielded gate slot type power MOSFET device increases darker shielded gate slot in grid slot both sides, forms thick oxide layer and makes it and source metal level short circuit in the shielded gate slot, make when the device is reverse when ending, the body knot exhausts in advance in shielded gate slot bottom, thereby the protection grid oxide layer, thick oxide layer still provides higher compressive capacity in order to prevent that the shielded gate from puncturing simultaneously, thereby realized the anti avalanche ability that promotes the device, improve the reliability of device and expand the purpose of its applied scene.

It should be understood that all of the above preferred embodiments are exemplary and not restrictive, and that various modifications and changes in the specific embodiments described above, which may occur to those skilled in the art upon reading the teachings of the present invention, are intended to be within the scope of the appended claims.

Claims (10)

1. A shielded gate trench type power MOSFET device comprises a semiconductor substrate, a drain metal layer located below the semiconductor substrate and a source metal layer located on the semiconductor substrate, wherein the semiconductor substrate is provided with a lower surface and an upper surface, the semiconductor substrate is in short connection with the drain metal layer through the lower surface, at least one group of trenches extending in parallel are formed on the upper surface of the semiconductor substrate, polycrystalline silicon is filled in each trench, an oxide layer is formed between the polycrystalline silicon and the corresponding trench wall, the shielded gate trench type power MOSFET device is characterized in that the at least one group of trenches comprise a gate trench and shielded gate trenches located on two sides of the gate trench, the polycrystalline silicon in the shielded gate trenches is in short connection with the source metal layer, the polycrystalline silicon in the gate trenches is not in short connection with the source metal layer, and the thickness of the oxide layer of the shielded gate trenches is larger than that of the gate trenches.

2. The shielded gate trench power MOSFET of claim 1 wherein a portion of the upper surface of the semiconductor substrate forms a body junction via ion implantation such that the bottom wall and the sidewalls of the shielded gate trench are both in direct communication with the body junction.

3. The shielded gate trench power MOSFET of claim 2 wherein the body junction is shorted to the source metal layer.

4. The shielded gate trench power MOSFET of claim 1 wherein the width of the shielded gate trench is greater than the width of the gate trench.

5. The shielded gate trench power MOSFET of claim 1 wherein the shield gate trench has a depth greater than the gate trench.

6. The shielded gate trench power MOSFET of claim 5 wherein the depth of the shielded gate trench is from 2 to 4 times the depth of the gate trench.

7. The shielded gate trench power MOSFET of claim 5 wherein the depth of the shielded gate trench is greater than 4 times the depth of the gate trench.

8. The shielded gate trench power MOSFET device of any of claims 1 through 7 wherein the depth of the gate trench is in a range between 0.5 microns and 1.5 microns.

9. The shielded gate trench power MOSFET device of any of claims 1 through 7 wherein the oxide layer thickness of the shielded gate trench is in the range between 1000 angstroms and 9000 angstroms and the oxide layer thickness of the gate trench is in the range between 300 angstroms and 600 angstroms.

10. The shielded gate trench type power MOSFET device of any of claims 1 through 7 wherein the semiconductor die comprises a substrate and an epitaxial layer on the substrate, the substrate being shorted to the drain metal layer via a lower surface thereof, the at least one set of trenches being formed at an upper surface of the epitaxial layer.

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