CN116705604A - Double-groove MOSFET device and preparation method for improving voltage endurance capacity thereof - Google Patents

Double-groove MOSFET device and preparation method for improving voltage endurance capacity thereof Download PDF

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Publication number
CN116705604A
CN116705604A CN202310613457.9A CN202310613457A CN116705604A CN 116705604 A CN116705604 A CN 116705604A CN 202310613457 A CN202310613457 A CN 202310613457A CN 116705604 A CN116705604 A CN 116705604A
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groove
trench
source
oxide layer
mosfet device
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吴龙江
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Shenzhen Sirius Semiconductor Co ltd
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Shenzhen Sirius Semiconductor Co ltd
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Abstract

The invention discloses a double-groove MOSFET device and a preparation method for improving the voltage endurance capacity thereof, wherein the method comprises the following steps: etching a source electrode groove; filling a first oxide layer at an opening of a source electrode groove in a cell region; a metal electrode is doped over the first oxide layer. The prepared double-groove MOSFET device comprises the following components: a source trench; the first oxide layer is positioned above the opening of the source electrode groove of the cell area; and the metal electrode is positioned above the first oxide layer. According to the invention, the first oxide layer is formed by doping the oxide above the opening of the source electrode groove of the cellular region, so that the source electrode groove and the metal electrode are not in direct contact, and the voltage-withstanding capability of the double-groove MOSFET device is improved under the condition that the additional cost is not required to be increased.

Description

Double-groove MOSFET device and preparation method for improving voltage endurance capacity thereof
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a double-groove MOSFET device and a preparation method for improving the voltage endurance capacity of the double-groove MOSFET device.
Background
In trench MOSFETs, there are one or more vertical trenches between the gate and channel of the transistor, known as trench structures. The trenches are filled with some insulating material and communicate with the source and drain. By varying the gate voltage, the channel resistance of the MOSFET can be controlled to achieve current control.
The double-groove MOSFET device is a common power MOSFET and is characterized by simple and flexible structure, low on-resistance, high switching speed and the like. However, in the structure of the existing dual trench MOSFET device, the source trench and the metal are usually in direct contact, and such a structure generally causes the following problems: firstly, high current is generated at the contact surface of the dielectric layer of the source electrode groove and the metal, so that the thermal expansion coefficient is changed, and the short circuit test at the contact surface is easy to fail; second, the breakdown voltage test of the device is also prone to occur due to defects.
Disclosure of Invention
In order to solve at least one technical problem set forth above, the present invention provides a dual trench MOSFET device and a method for manufacturing the same, which can improve the voltage endurance capability of a cell.
In a first aspect, the present invention provides a method for manufacturing a dual trench MOSFET device with improved voltage endurance, the method comprising:
etching a source electrode groove;
filling a first oxide layer at an opening of a source electrode groove in a cell region;
a metal electrode is doped over the first oxide layer.
In one possible embodiment, the method for manufacturing the dual trench MOSFET device for improving the voltage endurance capability further includes:
filling a second oxide layer at an opening of the source electrode groove positioned in the terminal edge area;
the metal electrode is doped over the second oxide layer.
In one possible implementation manner, the filling the opening of the source trench in the cellular region with the first oxide layer includes:
etching back the source electrode groove to form a notch;
and filling the first oxide layer at the notch.
In one possible implementation, after the etching of the source trench;
oxide deposition is carried out, and a first groove is etched in the deposited source groove;
and filling a dielectric layer in the first groove.
In one possible embodiment, before the etching the source trench, the method further includes:
providing a substrate and an epitaxial layer on the substrate; wherein the epitaxial layer comprises a drift layer;
and P-type doping is carried out on the drift layer, so that a P-well region is formed.
In one possible implementation manner, after the forming of the P-well region, the method further includes:
etching a grid groove in the P well region;
and P+ ion implantation and N+ ion implantation are carried out in the P well region.
In a second aspect, the present invention also provides a dual trench MOSFET device comprising:
a source trench;
the first oxide layer is positioned above the opening of the source electrode groove of the cell area;
and the metal electrode is positioned above the first oxide layer.
In one possible embodiment, the dual trench MOSFET device further includes:
the second oxide layer is positioned above the opening of the source electrode groove of the terminal edge region;
wherein the metal electrode is also located above the second oxide layer.
In one possible embodiment, the dual trench MOSFET device further includes:
a first trench and a dielectric layer;
the first groove is etched in the source groove;
the dielectric layer is filled in the first groove.
In one possible embodiment, the dual trench MOSFET device further includes:
a substrate;
the epitaxial layer is obtained after epitaxy on the substrate, and comprises a drift layer;
the P well region is obtained after P type doping is carried out on the drift layer;
a grid groove etched in the P well region
Compared with the prior art, the invention has the beneficial effects that:
the invention discloses a double-groove MOSFET device and a preparation method for improving the voltage endurance capacity thereof, wherein the method comprises the following steps: etching a source electrode groove; filling a first oxide layer at an opening of a source electrode groove in a cell region; a metal electrode is doped over the first oxide layer. The prepared double-groove MOSFET device comprises the following components: a source trench; the first oxide layer is positioned above the opening of the source electrode groove of the cell area; and the metal electrode is positioned above the first oxide layer.
According to the invention, the first oxide layer is formed by doping the oxide above the opening of the source electrode groove of the cellular region, so that the source electrode groove and the metal electrode are not in direct contact, and the voltage-withstanding capability of the double-groove MOSFET device is improved under the condition that the additional cost is not required to be increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
In order to more clearly describe the embodiments of the present invention or the technical solutions in the background art, the following description will describe the drawings that are required to be used in the embodiments of the present invention or the background art.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the technical aspects of the disclosure.
Fig. 1 is a schematic structural diagram of a conventional dual trench MOSFET device according to an embodiment of the present invention;
FIG. 2 is a top view of FIG. 1;
fig. 3 is a schematic flow chart of a method for manufacturing a dual-trench MOSFET device for improving voltage endurance capability according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a dual trench MOSFET device according to an embodiment of the present invention;
fig. 5 is a schematic flow chart of a method for manufacturing a dual-trench MOSFET device for improving voltage endurance capability according to another embodiment of the present invention;
fig. 6 is a schematic diagram of a terminal structure of a conventional dual trench MOSFET device according to an embodiment of the present invention;
FIG. 7 is a top view of FIG. 6;
fig. 8 is a schematic diagram of a termination structure of a dual trench MOSFET device according to an embodiment of the present invention;
FIG. 9 (a) is a schematic diagram of a P-well region fabricated in a cellular region according to an embodiment of the present invention;
FIG. 9 (b) is a schematic diagram of a P-well region fabricated in a terminal edge region according to an embodiment of the present invention;
FIG. 10 (a) is a schematic diagram illustrating the principle of etching a trench in a cellular region according to an embodiment of the present invention;
fig. 10 (b) is a schematic diagram of etching a trench in a terminal edge region according to an embodiment of the present invention;
FIG. 11 (a) is a schematic diagram of an embodiment of the present invention for etching back a source trench and a gate trench in a cellular region;
fig. 11 (b) is a schematic diagram of etching back a source trench in a terminal edge region according to an embodiment of the present invention;
fig. 12 (a) is a schematic diagram of filling oxide layers in a source trench and a gate trench in a cellular region according to an embodiment of the present invention;
fig. 12 (b) is a schematic diagram of filling an oxide layer in a terminal edge region for a source trench according to an embodiment of the present invention;
fig. 13 (a) is a schematic structural diagram of a cell region of a dual trench MOSFET device according to an embodiment of the present invention;
fig. 13 (b) is a schematic structural diagram of a termination structure of a dual trench MOSFET device under the manufacturing process according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better illustration of the invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present invention.
At present, in the structure of a dual-trench MOSFET device, a source trench and a metal are usually in direct contact, and the structure is easy to cause some problems, firstly, a high current is generated at the contact surface of a dielectric layer of the source trench and the metal to generate high heat, so that the thermal expansion coefficient is changed, and therefore, the short circuit test at the contact surface is easy to fail; and secondly, breakdown is easy to occur due to defects in the withstand voltage test of the device. In order to solve the problem, the invention aims to provide a preparation method of a double-groove MOSFET device capable of improving the voltage endurance capability and a structure of the double-groove MOSFET device.
Referring to fig. 1-2, fig. 1 provides a schematic structure diagram of a conventional dual trench MOSFET device, and fig. 2 is a top view of fig. 1. As can be seen from fig. 1-2, the source trench is in direct contact with the metal electrode (Sourcemetal). The core of the present invention is therefore that the source trench and the metal electrode are not in direct contact when making a dual trench MOSFET device.
Referring to fig. 3, fig. 3 provides a flow chart of a method for manufacturing a dual trench MOSFET device with improved voltage endurance capability. As can be seen from fig. 3, the method comprises the steps of:
s10, etching a source electrode groove;
s20, filling a first oxide layer at an opening of a source electrode groove in a cell area;
s30, doping a metal electrode above the first oxide layer.
Trench-type power devices are a special type of Metal Oxide Semiconductor Field Effect Transistor (MOSFET). It has one or more trenches or grooves in which charge can be stored. These trenches form a diffusion region that is implanted when a forward voltage is applied. This implantation process results in a very small on-resistance of the device, thereby improving its switching speed and efficiency. The vertical grid structure is a stacked structure formed by alternately forming N-type materials and P-type materials. The grid electrode and the source/drain electrodes are perpendicular to the surface of the chip, so that the current flow can be better controlled.
The double-groove MOSFET device belongs to a groove type power device, in the structure, a grid electrode and a source electrode are vertical groove-shaped, when the grid electrode is applied with a sufficient positive voltage, charges in the groove can form a channel, and current can flow from the source electrode to the drain electrode. The dual trench MOSFET device generally has a lower on-resistance than the MOSFET device of the planar gate structure, and its breakdown voltage capability is further improved, so that it is widely used in power electronics applications such as DC-DC converters, inverters, motor drivers, and the like.
In this embodiment, the source trench is etched first in step S10.
In one embodiment, to etch the source trenches, it is generally necessary to use photolithography and plasma etching techniques, including the steps of:
step 1) providing a semiconductor substrate, and forming a first epitaxial layer on the surface of the semiconductor substrate;
step 2) forming a pattern of a dielectric film on the surface of the first epitaxial layer, wherein the dielectric film coverage area is arranged in the forming area of the groove; the dielectric film covering area is larger than the forming area of the groove defined in the subsequent step four, so that alignment redundancy between the groove formed by etching and the dielectric film is improved.
In one embodiment, step 1) further comprises the sub-steps of:
step 2.1), forming a first silicon nitride layer on the surface of the semiconductor substrate, and carrying out photoetching on the first silicon nitride layer, wherein the surface of the first epitaxial layer needing to form the dielectric film is exposed in an opening area of the first silicon nitride layer;
step 2.2) performing local field oxidation to form silicon oxide in the opening area of the first silicon nitride layer and forming the dielectric film by the silicon oxide;
step 2.3) removing the first silicon nitride layer.
Step 3), performing epitaxial growth on the surface of the first epitaxial layer on which the dielectric film pattern is formed to form a second epitaxial layer;
step 4) defining a forming area of the groove on the surface of the second epitaxial layer by adopting a photoetching process, and carrying out first etching on the second epitaxial layer in the forming area of the groove to form the groove, wherein the first etching is anisotropic etching, the dielectric film is used as a blocking layer of the first etching, the first etching is stopped on the dielectric film, and the depths of the grooves with different widths or the same width at different positions on the same semiconductor substrate are the same;
in one embodiment, step 4) further comprises the sub-steps of:
step 4.1) forming a hard mask layer on the surface of the second epitaxial layer;
step 4.2) defining a forming area of the groove by adopting a photoetching process;
step 4.3) etching the hard mask layer, wherein an opening area of the hard mask layer opens a forming area of the groove;
and 4.4) carrying out the first etching on the second epitaxial layer by taking the hard mask layer as a mask.
The hard mask layer needs to be removed after the dielectric film is removed in the subsequent step five.
Step 5) removing the dielectric film.
Further, after the source electrode groove is obtained by etching, a first oxide layer is filled in the opening of the source electrode groove in the cell area, and finally a metal electrode is doped on the first oxide layer.
In the current dual trench MOSFET device structure, the source trench is typically in direct contact with the metal electrode. In this embodiment, in order to prevent the Source trench from directly contacting the metal electrode, the trench opening is mainly filled with an oxide, i.e. the first oxide layer, and finally the Source trench (Source trench) and the Gate trench (Gate trench) may have a dielectric layer at the trench opening, as shown in fig. 4.
The oxide is filled in the source trench to isolate the direct contact between the source trench and the metal electrode. The filler material may be silicon dioxide, silicon nitride or other insulating material, the particular choice being dependent upon such factors as processability and reliability.
In one embodiment, the filled oxide is preferably a capping oxide.
The capping oxide (Encapsulated Oxide) is an insulating material used to encapsulate integrated circuits. It is usually made of silicate glass, silicon dioxide or silicon nitride, etc. to protect the metal circuit and transistor elements in the circuit, so as to improve the reliability and life of the circuit.
The capping oxide generally has high dielectric strength, low dielectric loss, and good chemical stability. In addition, it can resist the environmental effects such as humidity and pollution, thus improve the reliability and life-span of the circuit. The encapsulated oxide is mainly used for encapsulation and protection in the semiconductor industry. In integrated circuit manufacturing, circuit chips need to be packaged into different types of packages for different types of applications. In this process, the encapsulated oxide is used as an encapsulation material on the chip surface, forming a protective layer to protect the components in the chip from mechanical, electrical and thermal damage.
In this embodiment, the first oxide layer is formed by filling the cladding oxide at the opening of the source trench, so that compared with the common dielectric layer, the insulating strength of the device structure obtained in this embodiment is better, and the voltage endurance capability of the device is improved while the voltage endurance capability is ensured to be more stable.
Finally, when the first oxide layer is filled, a metal electrode is doped above the first oxide layer.
In the dual trench MOSFET, the source trench and the drain will have corresponding metal electrodes, and the present embodiment is mainly directed to the metal electrode above the source trench. In the double trench MOSFET, the metal electrode is required to have a low contact resistance, a high conductivity, and excellent thermal stability. In addition, the metal electrode should have good adhesion and corrosion resistance to ensure that it does not fall off or break down during long-term use.
The double-trench MOSFET is widely applied to the field of power electronic devices in the semiconductor industry, such as DC-DC converters, alternating current frequency converters, inverters and the like. Metal electrodes play a critical role in these applications as an important component of dual trench MOSFETs. For example, in a DC-DC converter, metal electrodes may help regulate the output voltage and current, thereby achieving efficient energy conversion.
The metal electrode of the present embodiment is required to have excellent conductivity, thermal stability and corrosion resistance, and for example, a material such as copper, tungsten or molybdenum is selected as the metal electrode. It will be appreciated that the choice of these materials is largely dependent on their processability and reliability in the manufacture of semiconductor devices. While this embodiment provides an exemplary selection, other embodiments may also be considered to select metal electrodes of other materials, and the embodiments of the present invention are not limited in any way.
Finally, metal electrodes (such as copper, tungsten or molybdenum) are deposited, and subsequent steps such as preparation and packaging are performed to form the complete dual trench MOSFET device.
In summary, in the above embodiment, the first oxide layer is formed by doping the oxide over the opening of the source trench in the cell region, so that the source trench and the metal electrode are not in direct contact, and the voltage-withstanding capability of the dual trench MOSFET device is improved without additional cost.
Referring to fig. 5, fig. 5 is a flow chart illustrating a method for manufacturing a dual trench MOSFET device with improved voltage endurance according to another embodiment. As can be seen from fig. 5, the method further comprises the steps of:
s40, filling a second oxide layer at the opening of the source electrode groove positioned in the edge area of the terminal;
s50, doping a metal electrode above the second oxide layer.
The meanings of the cell region and the terminal edge region are explained first as follows:
cell region: refers to the body portion of the transistor, including the source, drain, gate, etc. In operation, a current path is formed between the source and drain electrodes, while the gate electrode controls the flow of current by varying the strength of the electric field.
Terminal edge area: also referred to as a drain junction region, refers to a structure between the drain of the transistor and the substrate. The drain junction region has high electric field strength, and the current of the drain region can be controlled to a certain extent.
In the above embodiment, in order to improve the voltage-withstanding capability of the device, the structure of the cell region is mainly improved, and finally, the source trench in the cell region is not directly contacted with the metal electrode, that is, the voltage-withstanding capability of the cell region is improved.
Referring to fig. 6-7, fig. 6 is a schematic diagram of a termination structure of a conventional dual trench MOSFET device structure, and fig. 7 is a top view of fig. 6. As can be seen from fig. 6-7, the source trench of the prior art device at the termination edge region is also in direct contact with the metal electrode. Therefore, in order to further improve the withstand voltage capability of the device, the problem of low withstand voltage caused by the source trench and the metal electrode in the terminal edge region is also considered in this embodiment.
Specifically, in this embodiment, in step S40, the second oxide layer is filled at the opening of the source trench located in the terminal edge region; finally, in step S50, a metal electrode is doped over the second oxide layer. The final termination structure as shown in fig. 8 is formed. As can be seen from fig. 8, in this embodiment, the opening of the source trench in the terminal edge region is also filled with oxide, i.e., the second oxide layer, so that the source trench in the terminal edge region and the metal electrode are not directly contacted, and the voltage-withstanding capability of the terminal edge region of the device is further improved.
It can be understood that the second oxide layer filled in the present embodiment may refer to the material and the filling method of the first oxide layer described in the above embodiment, and the doping and the material selection of the metal electrode may refer to the description of the above embodiment, which will not be further described herein.
In one possible implementation manner, the filling the opening of the source trench in the cellular region with the first oxide layer includes:
etching back the source electrode groove to form a notch;
and filling the first oxide layer at the notch.
In the double-trench MOSFET, a channel region is provided on both sides of a source and a drain, and a switching function is realized by applying a voltage control current to the channel region. In order to improve the performance and stability of the device, after the source trench is filled with the dielectric layer to isolate the metal electrode from direct contact, the source trench needs to be etched back to form a notch, and then the first oxide layer is filled at the notch, so that the metal electrode is not in direct contact with the source trench, but can be communicated with the source trench.
Specifically, after the source trench is filled with the dielectric layer, the metal electrode cannot be connected to the source trench because the dielectric layer has good insulation properties. If the source trench is not etched back, a circuit break exists between the source trench and the metal electrode, and the normal operation is not possible. Therefore, it is necessary to etch back the source trench, form a notch so that a metal electrode can be connected to the source trench, and control a current by controlling the potential of the channel region.
In one possible implementation, after the etching of the source trench;
oxide deposition is carried out, and a first groove is etched in the deposited source groove;
and filling a dielectric layer in the first groove.
After the source trench has been formed, an oxide, such as silicon dioxide (SiO 2), needs to be deposited in the source trench and an annealing process is performed to improve its stability.
Further, a first trench is etched on the deposited oxide using a photolithography technique such that the first trench is located over the source trench. The first trench has the function of controlling the channel region potential.
A dielectric layer, such as silicon nitride (Si 3N 4) or Polyimide (PI), is filled in the first trench to isolate direct contact between the source trench and the trench walls of the P-well region. In general, dielectric layers have good insulating properties and thermal stability.
In one possible embodiment, before the etching the source trench, the method further includes:
providing a substrate and an epitaxial layer on the substrate; wherein the epitaxial layer comprises a drift layer;
and P-type doping is carried out on the drift layer, so that a P-well region is formed.
It should be noted that providing a substrate means that in the manufacture of a semiconductor device, a desired material is deposited on a base material, which is the substrate. The choice of substrate has a great impact on both the performance and the fabrication process of the semiconductor device. Depositing an epitaxial layer on a substrate is one of the important steps in the fabrication of semiconductor devices. Epitaxial layer refers to the deposition of a layer of a material, typically a semiconductor material, on a substrate that is different from the substrate material. The preparation of the epitaxial layer requires the use of chemical vapor deposition, physical vapor deposition, and other techniques. The thickness, material, doping, etc. parameters of the epitaxial layer have a great influence on the performance of the semiconductor device. For example, in the fabrication of photovoltaic devices, it is necessary to deposit a p-type or n-type epitaxial layer on a substrate to form a p-n junction to achieve photovoltaic conversion. In the fabrication of transistors, an n-type or p-type epitaxial layer is deposited on a substrate to form source, drain, gate, etc. structures. In summary, providing a substrate and preparing an epitaxial layer are indispensable steps in the preparation process of a semiconductor device, and have great influence on the performance and preparation process of the semiconductor device. The material may be prepared based on a silicon carbide substrate in this embodiment.
The drift layer is positioned between the source electrode and the drain electrode, has the functions of bearing an electric field and controlling current, and is a key for ensuring the performance and the reliability of the device. In a drift layer double trench SIC MOSFET, the drift layer is typically composed of an n-type or p-type doped silicon carbide material.
Specifically, in an n-type drift layer double-trench SIC MOSFET, the drift layer is composed of an n-type doped silicon carbide material, the thickness of which determines the resistance and electric field strength of the drift region; in the p-type drift layer double-trench SIC MOSFET, a p-type doped silicon carbide material is correspondingly used as the drift layer. The drift layer has the main function of forming an n-type region on the substrate so as to form a PN junction and realize electron injection and discharge. The thickness of the drift layer is typically between a few microns and tens of microns, with the specific thickness being dependent on the desired electrical and thermal properties.
Further, the drift layer is also responsible for carrying drift motion of electrons, thereby realizing current transmission. In SIC materials, the mobility of electrons is very high, so the drift layer can carry high current density, while having lower resistance and higher thermal conductivity, thereby effectively reducing the thermal effect of the device. In addition, the drift layer can also improve the switching speed and power density of the device, thereby realizing high-efficiency power conversion.
In this embodiment, the growth process of the epitaxial layer on the SIC substrate is approximately as follows.
Preparing a substrate: firstly, a SIC substrate needs to be prepared, placed in epitaxial growth equipment and subjected to surface treatment to ensure that the surface is flat, clean and free of impurities.
Gas phase transport: in an epitaxial growth apparatus, a material (e.g., ammonia, trimethylaluminum, etc.) transported in a gas phase is heated to a high temperature to decompose it into atoms or molecules, and then transported to the substrate surface by means of gas phase transport.
And (3) epitaxial growth: on the substrate surface, the vapor-phase transported material will combine with atoms on the substrate surface to form a new crystal structure. This process is called epitaxial growth. In the epitaxial growth process, parameters such as temperature, air pressure, flow and the like need to be controlled so as to ensure the quality and thickness of the epitaxial layer.
And (3) epitaxial layer growth: after the growth of the first epitaxial layer is completed, the next epitaxial layer may be grown. The growth conditions of each epitaxial layer need to be adjusted according to the growth condition of the previous layer so as to ensure the quality and thickness of each epitaxial layer.
And (3) detecting the crystallization quality: in the epitaxial growth process, the crystal quality of the epitaxial layer needs to be detected. Common detection methods include X-ray diffraction, raman spectroscopy, scanning electron microscopy, and the like.
And (3) epitaxial layer removal: after all epitaxial layers are grown, the epitaxial layers need to be removed from the substrate. This process is called epitaxial layer removal. Common removal methods include chemical etching, mechanical stripping, and the like.
Preparing a device: finally, the epitaxial layers can be fabricated into various devices such as LEDs, lasers, power devices, etc. The preparation process comprises the steps of photoetching, etching, metallization and the like.
In one possible implementation manner, after the forming of the P-well region, the method further includes:
etching a grid groove in the P well region;
and P+ ion implantation and N+ ion implantation are carried out in the P well region.
In this embodiment, as a result of the P-type doping, the gate trench is etched in the P-well region, and a part of the material on the surface edge of the epitaxial layer is removed by dry etching to form a mesa with a corresponding shape.
In the possible implementation manner, the shape of the edge of the main junction is changed by etching and the like, and is usually etched into the shapes of a table surface, a right angle, a curved surface and the like, so that the surface electric field distribution and the breakdown voltage are effectively improved.
Mesa termination is one of the more common edge termination techniques for SiC vertical structure power devices. Dry etching is typically used to selectively remove portions of the material at the edges of the device to form mesas of different shapes. The mesa terminals may be divided into two types of inclined mesa terminals (positive-inclination inclined mesa, negative-inclination inclined mesa) and right-angle mesa terminals. The junction area reduction defined from the side with higher doping concentration to the side with lower doping concentration is called positive mesa, and vice versa, negative mesa.
Generally, for vertical PN structures, forming a positive tilt angle mesa (the low doped region removes more material than the high doped region) is more significant for improving device performance. This is because more material is removed in the low doped regions, which will result in an increase in the depletion layer width along the etched sidewalls; the p-type side is heavily doped so the depletion region shrinks less. The surface depletion width at the edge of the bevel mesa is thus wider than the depletion width in the body, the surface electric field of the device is lower, and surface breakdown can be avoided. After the common etching process, the area removed from the p-type semiconductor side is larger than that of the n-type semiconductor side, and the positive inclination angle inclined bench surface terminal is difficult to realize.
And when the PN junction is etched, the negative dip angle inclined table top is finally obtained due to the fact that more heavily doped p-type regions are removed. The depletion region in the p-type region expands in width and the n-type side surface contracts. Since the p-type side is heavily doped, the depletion region expands to a limited extent, so the surface depletion width Ws at the negative bevel mesa edge is smaller than the in-body depletion width WB. This shows that the fringing electric field of the structure is larger than the internal electric field and thus more prone to breakdown. Negative-pitch angled mesas are generally considered unsuitable as termination structures for power devices.
However, the negative mesa may also act to reduce surface electric field spikes with a very small tilt angle combined with low p-type SiC doping. As the tilt angle decreases, the depletion region width of the n-type side surface gradually decreases, and thus the boundary of the depletion region gradually approaches the interface of the PN junction. When the tilt angle is small, the boundary of the n-type side depletion region is pinned at the interface of the PN junction, while the depletion region along the etched slope is mainly on the p-type side.
A positive tilt angle mesa (low doped region removes more material than high doped region) is more significant for improving device performance. This is because more material is removed in the low doped regions, which will result in an increase in the depletion layer width along the etched sidewalls; the p-type side is heavily doped so the depletion region shrinks less. The surface depletion width at the edge of the bevel mesa is thus wider than the depletion width in the body, the surface electric field of the device is lower, and surface breakdown can be avoided.
Further, p+ ion implantation and n+ ion implantation are performed in the P-well region.
The P-well region is part of a MOSFET device that is formed of a P-type semiconductor material for controlling current flow between the channel and the source drain.
Ion doping in the p-well region is a common process used to tailor the electrical properties in semiconductor devices. The following are some commonly used methods:
ion implantation: this is one of the most commonly used doping methods that can direct the ion beam to the surface of the p-well region to alter the electrical properties of the semiconductor device.
Atomic Layer Deposition (ALD): this is a gas phase reaction based technique that allows the deposition of monoatomic layers on a semiconductor surface at a predetermined timing and temperature to have desired electrical properties.
Molecular Beam Epitaxy (MBE): this is a high resolution thin film growth technique on which ions can be doped into the p-well region by chemical reaction or physical deposition.
Ion exchange: this involves replacing atoms already present in the p-well region with the desired ions by chemical reaction or other means.
Laser doping: this is a technique that uses a laser beam to heat a semiconductor surface and release ions from a solid state source to achieve desired electrical characteristics.
In order to optimize the device performance or achieve specific functions, the present embodiment preferably performs p+ ion implantation and n+ ion implantation in the P-well region.
The p+ ion implantation is to implant high concentration positive ions into the surface of the P-well region to form a shallow p+ region, so as to increase contact resistance and prevent reverse breakdown of the PN junction. Specifically, the P+ ion injection can adjust the contact resistance, and the switching speed and the working stability of the device are improved.
And N+ ion implantation is to implant high-concentration negative ions into the center of the P well region to form a deep N+ region. The deep N+ region has the function of increasing the charge density of the channel region and improving the reverse leakage current, thereby improving the breakdown voltage and the reliability of the device.
In an exemplary embodiment, the present invention also provides a dual trench MOSFET device, in particular a dual trench SiCMOSFET, prepared by the above process. To aid in understanding the structure of the device, a process flow for fabricating the device will be described, comprising the steps of:
1) Growing a first N-type epitaxial layer with doping concentration of 5e 13-3 e17cm < -3 > on an N++ -type SiC substrate;
2) Preparing an N-type current expansion region on the first N-epitaxial layer by adopting a local ion implantation method;
3) Preparing a P+ shielding region in the N-type current expansion region by changing the type, the dosage and the energy of the implanted ions by adopting the local ion implantation method;
4) Epitaxially growing a second N-type epitaxial layer with doping concentration of 5e 13-3 e17cm < -3 > above the first N-type epitaxial layer;
5) P-type doping is performed on the epitaxial layer to obtain a p-well region, as shown in fig. 8, where (a) is a schematic diagram of a cellular region and (b) is a schematic diagram of a terminal edge region.
6) And etching a source electrode groove and a gate electrode groove in the p-well region by adopting a local etching method, respectively digging the source electrode groove and the gate electrode groove, then carrying out oxide deposition, and digging grooves needed by the dielectric layer to fill the dielectric layer, as shown in fig. 10. Wherein (a) is a schematic diagram of a cellular region and (b) is a schematic diagram of a terminal edge region;
7) Etching back the source trench and the gate trench simultaneously to form a notch, as shown in fig. 11, wherein (a) is a schematic diagram of a cell region and (b) is a schematic diagram of a terminal edge region;
8) Filling oxide at the gaps of the source electrode groove and the gate electrode groove to form an oxide layer with a cladding structure, as shown in fig. 12, wherein (a) is a schematic diagram of a cellular region and (b) is a schematic diagram of a terminal edge region;
9) Preparing an N+ source region and a P+ source region in a P-well region by changing the type, the dosage and the energy of the implanted ions by adopting the local ion implantation method;
10 Forming a gate dielectric layer through thermal oxidation or dielectric layer deposition process, and forming a gate electrode through metal or polysilicon deposition process;
11 Depositing an interlayer isolation medium over the device and patterning it;
12 A metal electrode is doped over the oxide layer of the source trench.
Therefore, the source electrode groove and the metal electrode can not be in direct contact through the preparation process, and the voltage-withstanding capability of the device is improved.
If the voltage endurance capacity of the cell area is only required to be improved, filling an oxide layer at the opening of the source electrode groove of the cell area so that the oxide layer cannot be in direct contact with the metal electrode; if only the voltage-resistant capability of the terminal edge region needs to be improved, the oxide layer is filled in the opening of the source electrode groove of the terminal edge region, so that the oxide layer cannot be in direct contact with the metal electrode, and the oxide layer can be carried out according to the process requirements in specific implementation, and is not limited at all.
Referring to fig. 13, fig. 13 is a schematic structural diagram of a dual trench MOSFET device according to the present invention, in which (a) is a schematic structural diagram of a cellular region and (b) is a schematic structural diagram of a terminal edge region.
In this embodiment, a dual trench MOSFET device includes:
a source trench;
the first oxide layer is positioned above the opening of the source electrode groove of the cell area;
and the metal electrode is positioned above the first oxide layer.
Through the preparation process provided by the foregoing embodiment, a dual trench MOSFET device as shown in fig. 13 may be obtained, as shown in fig. 13 (a), in which the drain electrode is formed on the substrate, the epitaxial layer is formed on the substrate, ion doping is performed on the epitaxial layer to obtain a P-well region, then the gate trench and the source trench are etched on the P-well region, and the n+ source region and the p+ source region are implanted by ion implantation, then trenches are dug in the gate trench and the source trench to fill the dielectric layer, and the openings of the gate trench and the source trench are filled with the oxide layer, and finally the metal electrode is doped above the oxide layer of the source trench. As can be seen from fig. 13 (b), the source trench and the metal electrode do not directly contact, and thus the voltage withstand capability of the device can be improved.
In one possible embodiment, the dual trench MOSFET device further includes:
the second oxide layer is positioned above the opening of the source electrode groove of the terminal edge region;
wherein the metal electrode is also located above the second oxide layer.
In this embodiment, by the structure, the source trench in the terminal edge region may not be in direct contact with the metal electrode, and the withstand voltage of the cell region is improved, and the withstand voltage of the terminal edge region is also improved.
In one possible embodiment, the dual trench MOSFET device further includes:
a first trench and a dielectric layer;
the first groove is etched in the source groove;
the dielectric layer is filled in the first groove.
It can be understood that the gate trench is also provided with a trench which can be filled with a medium, and finally the gate trench with a cladding oxide layer structure is formed, so that the stability of the device is improved.
In one possible embodiment, the dual trench MOSFET device further includes:
a substrate;
the epitaxial layer is obtained after epitaxy on the substrate, and comprises a drift layer;
the P well region is obtained after P type doping is carried out on the drift layer;
and the grid groove is etched in the P well region.
As can be seen from fig. 13 (a), the drain electrode is formed on the substrate, an epitaxial layer is formed on the substrate, ion doping is performed on the epitaxial layer to obtain a P-well region, then a gate trench and a source trench are etched on the P-well region, and n+ source region and p+ source region are implanted by ion implantation, then trenches are dug in the gate trench and the source trench to fill the dielectric layer, and openings of the gate trench and the source trench are filled with an oxide layer, and finally a metal electrode is doped above the oxide layer of the source trench.
In summary, by the dual trench MOSFET device structure provided in this embodiment, the source trench of the cell region and/or the terminal edge region may not be in direct contact with the metal electrode, so that the voltage endurance capability of the cell region and/or the terminal edge region is finally improved without additional cost.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims (10)

1. The preparation method of the double-groove MOSFET device for improving the voltage endurance capability is characterized by comprising the following steps of:
etching a source electrode groove;
filling a first oxide layer at an opening of a source electrode groove in a cell region;
a metal electrode is doped over the first oxide layer.
2. The method of fabricating a dual trench MOSFET device with increased voltage endurance according to claim 1, further comprising:
filling a second oxide layer at an opening of the source electrode groove positioned in the terminal edge area;
the metal electrode is doped over the second oxide layer.
3. The method for manufacturing a dual-trench MOSFET device with improved voltage endurance according to claim 1, wherein filling the opening of the source trench in the cell region with the first oxide layer comprises:
etching back the source electrode groove to form a notch;
and filling the first oxide layer at the notch.
4. The method of fabricating a dual trench MOSFET device with increased voltage endurance according to claim 1, wherein after said etching of the source trench;
oxide deposition is carried out, and a first groove is etched in the deposited source groove;
and filling a dielectric layer in the first groove.
5. The method of fabricating a dual trench MOSFET device with increased voltage endurance according to claim 1, further comprising, prior to said etching the source trench:
providing a substrate and an epitaxial layer on the substrate; wherein the epitaxial layer comprises a drift layer;
and P-type doping is carried out on the drift layer, so that a P-well region is formed.
6. The method of manufacturing a dual trench MOSFET device with increased voltage endurance according to claim 5, further comprising, after said forming a P-well region:
etching a grid groove in the P well region;
and P+ ion implantation and N+ ion implantation are carried out in the P well region.
7. A dual trench MOSFET device comprising:
a source trench;
the first oxide layer is positioned above the opening of the source electrode groove of the cell area;
and the metal electrode is positioned above the first oxide layer.
8. The dual trench MOSFET device of claim 7, further comprising:
the second oxide layer is positioned above the opening of the source electrode groove of the terminal edge region;
wherein the metal electrode is also located above the second oxide layer.
9. The dual trench MOSFET device of claim 7, further comprising:
a first trench and a dielectric layer;
the first groove is etched in the source groove;
the dielectric layer is filled in the first groove.
10. The dual trench MOSFET device of claim 7, further comprising: a substrate;
the epitaxial layer is obtained after epitaxy on the substrate, and comprises a drift layer;
the P well region is obtained after P type doping is carried out on the drift layer;
and the grid groove is etched in the P well region.
CN202310613457.9A 2023-05-26 2023-05-26 Double-groove MOSFET device and preparation method for improving voltage endurance capacity thereof Pending CN116705604A (en)

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