JPH0437152A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0437152A JPH0437152A JP14166990A JP14166990A JPH0437152A JP H0437152 A JPH0437152 A JP H0437152A JP 14166990 A JP14166990 A JP 14166990A JP 14166990 A JP14166990 A JP 14166990A JP H0437152 A JPH0437152 A JP H0437152A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- layer
- trench
- oxide film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 21
- 239000001301 oxygen Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 18
- -1 oxygen ion Chemical class 0.000 claims abstract description 16
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- 238000002955 isolation Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 abstract description 23
- 238000000137 annealing Methods 0.000 abstract description 10
- 238000005530 etching Methods 0.000 abstract description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 5
- 229910021419 crystalline silicon Inorganic materials 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 description 10
- 238000007254 oxidation reaction Methods 0.000 description 10
- 239000013078 crystal Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の概要〕
半導体装置の製造方法に関し、
半導体基板に溝部を形成し、その後酸化処理した場合の
該溝部コーナ一部での応力集中の緩和を目的とし、溝部
形成後、アニール前に該溝部に酸素イオンを注入するよ
うに構成する。[Detailed Description of the Invention] [Summary of the Invention] Regarding a method for manufacturing a semiconductor device, the present invention relates to a method for manufacturing a semiconductor device, in which a groove is formed in a semiconductor substrate and is then subjected to an oxidation treatment. After that, oxygen ions are implanted into the trench before annealing.
本発明は、半導体装置の製造方法に関し、更に詳しくは
、半導体装置における素子分離として用いる溝(U溝等
)(トレンチ・アイソレーション)の平坦化、並びに酸
化時およびその後の熱プロセス過程で溝のコーナ一部に
発生するストレスを防ぐようにした半導体装置の製造方
法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more specifically, the present invention relates to a method for manufacturing a semiconductor device, and more particularly, to flattening a trench (such as a U trench) used for element isolation in a semiconductor device (trench isolation), and flattening the trench during oxidation and subsequent thermal processing. The present invention relates to a method for manufacturing a semiconductor device that prevents stress from occurring at a portion of a corner.
〔従来技術および発明が解決しようとする課題〕大規模
集積回路(LSI)においては、シリコン基板面に形成
された各素子を電気的に分離することが必要である。こ
のような素子間分離に、従来選択酸化が採用されている
。[Prior Art and Problems to be Solved by the Invention] In large-scale integrated circuits (LSI), it is necessary to electrically isolate each element formed on a silicon substrate surface. Conventionally, selective oxidation has been employed for such element isolation.
一方、近年のLSIの高集積化に伴い、集積度を上げる
ために素子分離もできるだけ細くして、分離に要する面
積を小さくする必要がある。そのため、選択酸化に代っ
て素子分離に要する面積の小さいトレンチアイソレーシ
ョン法が注目され、利用されている。On the other hand, as LSIs have become highly integrated in recent years, it is necessary to make element isolation as thin as possible to increase the degree of integration, thereby reducing the area required for isolation. Therefore, instead of selective oxidation, trench isolation, which requires a small area for element isolation, is attracting attention and being used.
このトレンチアイソレーション法は、第2図(1)〜(
3)に示すように例えば単結晶シリコン層1上に不純物
をドープしたSi層2を形成し、第2図(2)に示すよ
うに更にエピタキシャルS1層3を形成した半導体基板
Aを所定のエツチングガスを用いた反応性イオンエツチ
ング(Rr8)により垂直にU字形状に溝を掘り、次い
で第2図(3)に示すように熱酸化して酸化膜5を表面
に形成し、更に該溝にポリシリコン等の絶縁物を埋め込
んで素子分離を行う方式である。しかし、この方式によ
る場合、第2図(2)に示すようにエピタキシャルS1
層3およびドープしたS1層2す一部において応力集中
が起こり、このため溝壁部およびコーナ一部においては
酸化されに<<シかも結晶欠陥6が発生していた。This trench isolation method is shown in Figure 2 (1) to (
3) For example, a semiconductor substrate A in which an impurity-doped Si layer 2 is formed on a single crystal silicon layer 1 and an epitaxial S1 layer 3 is further formed as shown in FIG. 2(2) is etched in a predetermined manner. A U-shaped groove is dug vertically by reactive ion etching (Rr8) using gas, and then, as shown in FIG. 2 (3), an oxide film 5 is formed on the surface by thermal oxidation, and then the groove is This method performs element isolation by burying an insulator such as polysilicon. However, in this method, as shown in FIG. 2 (2), the epitaxial S1
Stress concentration occurred in the layer 3 and a portion of the doped S1 layer 2, and as a result, crystal defects 6 were generated in the groove wall portion and a portion of the corner due to oxidation.
このように、酸化過程およびその後の熱プロセスでの応
力集中は基板に転位や結晶欠陥を誘起させるたtlそれ
らの問題は例えばバイポーラデバイスにおけるエミッタ
ーコレクタ間のリーク原因にもなっていた。As described above, stress concentration during the oxidation process and subsequent thermal process induces dislocations and crystal defects in the substrate.These problems also cause leakage between emitter and collector in bipolar devices, for example.
〔課題を解決するた杓の手段〕
本発明は以上の点を鑑み、エツチング表面の凹凸の低減
とトレンチコーナ一部での応力集中の緩和を行うことを
目的としてなされたものであり、半導体基板の素子間分
離領域の形成せられるべき位置に溝部を形成し、次いで
酸素イオンを該溝部に注入し、しかる後熱処理を行い酸
化膜を形成することを特徴とする。[Means for Solving the Problems] In view of the above points, the present invention has been made for the purpose of reducing the unevenness of the etching surface and alleviating the stress concentration at a part of the trench corner. The method is characterized in that a trench is formed at a position where an element isolation region is to be formed, and then oxygen ions are implanted into the trench, followed by heat treatment to form an oxide film.
すなわち、本発明方法では、トレンチエツチング後に、
高濃度の酸素イオンを溝部に注入し、真空中または酸素
雰囲気中で低温アニールして酸化膜を形成して素子分離
を行うものである。このような本発明方法において、酸
素イオンの注入は基板に対して垂直方向から約10〜6
0度傾斜させて溝部に注入する。That is, in the method of the present invention, after trench etching,
Highly concentrated oxygen ions are injected into the trench, and low-temperature annealing is performed in a vacuum or in an oxygen atmosphere to form an oxide film and perform element isolation. In such a method of the present invention, oxygen ions are implanted in a direction perpendicular to the substrate at approximately 10 to 6
Inject into the groove at a 0 degree angle.
このように一定の角度をもたせてイオン注入を行う理由
は、結晶欠陥が発生しやすい溝のコーナ一部付近に、酸
素イオンを多量注入して丸みを帯びた注入領域を形成し
、応力集中の緩和を図るためである。つまり、注入角度
が約60度を超えた場合、角度が浅くなり酸素イオンが
低部まで入りにくくなり側壁ばかりに注入されるので具
合が悪い。The reason for performing ion implantation at a certain angle is that a large amount of oxygen ions are implanted near some corners of the groove where crystal defects are likely to occur, forming a rounded implantation region and reducing stress concentration. This is to alleviate the situation. In other words, if the implantation angle exceeds about 60 degrees, the angle becomes shallow, making it difficult for oxygen ions to penetrate into the lower part and implanting them only into the sidewalls, which is undesirable.
逆に約10℃未満の場合、底部近傍において丸みをおび
た注入領域が形成されなくなり、具合が悪いからである
。On the other hand, if the temperature is less than about 10° C., a rounded implanted region will not be formed near the bottom, resulting in poor conditions.
更に本発明方法ではトレンチエツチング後のアニール工
程は、比較的低温(800〜900℃)で真空中または
酸素雰囲気中で行うことが好ましい。この場合、800
℃未満でのアニール温度では酸化速度が極端に遅くなり
、一方、900℃を超えた高温のアニール温度では、す
でに前の工程で拡散層を形成していた場合ドーパント
(P、Bなど)が拡散しやすくなり余り好ましくない。Furthermore, in the method of the present invention, the annealing step after trench etching is preferably carried out at a relatively low temperature (800 to 900 DEG C.) in vacuum or in an oxygen atmosphere. In this case, 800
Annealing temperatures below 900°C will result in extremely slow oxidation rates, while high annealing temperatures above 900°C will oxidize the dopants if they have already formed a diffusion layer in a previous step.
(P, B, etc.) tend to diffuse, which is not very preferable.
従って、上記アニール温度を好ましく採用するのである
。Therefore, the above annealing temperature is preferably employed.
本発明による方法では、溝部への酸素イオン注入により
、溝周辺部にアモルファス層が第1図(3)の図番15
の如く形成され、アモルファス領域はトレンチコーナ一
部で丸くなり、しかもスパッタ効果によりトレンチ側壁
表面の凹凸は減少する。そして、続く酸化はイオン注入
によりアモルファス化された領域もしくは欠陥領域から
優先的に始まる。In the method according to the present invention, by implanting oxygen ions into the groove, an amorphous layer is formed around the groove as shown in figure 15 in FIG. 1(3).
The amorphous region is rounded at a portion of the trench corner, and the unevenness of the trench sidewall surface is reduced due to the sputtering effect. Then, the subsequent oxidation starts preferentially from regions made amorphous by ion implantation or from defective regions.
従って、酸化時における堆積膨張に起因するトレンチコ
ーナ一部でのストレスは減少ししかもトレンチ側壁は平
坦になるため、熱プロセス誘起の結晶欠陥は減少する。Therefore, stress at a portion of the trench corner due to deposition expansion during oxidation is reduced, and the trench sidewalls are flattened, so crystal defects induced by thermal processes are reduced.
以下、実施例により更に本発明を説明する。The present invention will be further explained below with reference to Examples.
口実流側;
第1図に示すように、単結晶ンリコン層11、ドープS
i層12およびエピタキシャルSi層13からなる半導
体基板BをRIE法により常法に従いトレンチエツチン
グし、U溝14を形成する。次いで酸素イオンを該基板
13に対して垂直方向から10度〜60度の角度をもた
せて、基板Bを回転させながら5QkeVで、I XI
O”:l/cj〜2 XIO”:)のイオンを注入する
(第2図(2))。この結果、第1図(3)に示すよう
に溝14の側壁は平坦化され、コーナ一部では丸みをお
びかつ底部では膜厚の厚い、酸素を多く含んだアモルフ
ァス層15が形成された。Pretext flow side: As shown in FIG. 1, single crystal silicon layer 11, doped S
A semiconductor substrate B consisting of an i-layer 12 and an epitaxial Si layer 13 is trench-etched in a conventional manner by RIE to form a U-groove 14. Next, while rotating the substrate B, the oxygen ions are irradiated with I
Ions of O":l/cj~2XIO":) are implanted (FIG. 2 (2)). As a result, as shown in FIG. 1(3), the side walls of the trench 14 were flattened, and an amorphous layer 15 containing a large amount of oxygen was formed, which was rounded at some corners and thick at the bottom.
次いで800〜900℃のアニール温度で真空中または
酸素雰囲気中でアニール工程を行い、結合力の強い酸化
膜16を溝部外表面に形成した。Next, an annealing step was performed in vacuum or in an oxygen atmosphere at an annealing temperature of 800 to 900° C. to form an oxide film 16 with strong bonding strength on the outer surface of the groove.
以後の工程は常法に従い溝に絶縁物を埋めこんで素子分
離を行った。In the subsequent steps, an insulator was filled in the grooves to isolate the elements according to a conventional method.
以上、説明したように、本発明方法ではトレンチエツチ
ング直後に高濃度の酸素イオンを基板に対して一定の角
度をもたせてイオン注入してその後比較的低温でアニー
ルするように構成したものであるから、溝コーナ一部で
のストレス集中を減少せし緬ることができ、しかも溝側
壁での凹凸を減少せしめる効果を奏する。As explained above, in the method of the present invention, high concentration oxygen ions are implanted at a certain angle to the substrate immediately after trench etching, and then annealing is performed at a relatively low temperature. This has the effect of reducing stress concentration at a portion of the groove corner, and also reducing unevenness on the groove sidewalls.
この結果、基板内で発生する結晶欠陥の発生をはX゛完
全防止することができ、このためエミッターコレクター
間のリーク特性も向上せしめる効果を奏する。As a result, the occurrence of crystal defects within the substrate can be completely prevented, and the leakage characteristics between the emitter and collector can also be improved.
第1図は、本発明方法の一実施を示す工程図であり、
第2図は、従来方法によるアイソレーションの一例を示
す工程図である。
11・・・単結晶シリコン層、
12・・・ドープSi層、
13・・・エピタキシャルSi層、
14・・・溝、
15・・・アモルファス層、
16・・・酸化膜、
B・・・半導体基板。
/
B・・・半導体基板
本発明方法の一実施例を示す1租国
策1図
本発明方法の一実施例を示す工程国
策 1 図 (続ぎ)FIG. 1 is a process diagram showing one implementation of the method of the present invention, and FIG. 2 is a process diagram showing an example of isolation by a conventional method. DESCRIPTION OF SYMBOLS 11... Single crystal silicon layer, 12... Doped Si layer, 13... Epitaxial Si layer, 14... Groove, 15... Amorphous layer, 16... Oxide film, B... Semiconductor substrate. / B... Semiconductor substrate 1 National policy 1 figure showing an embodiment of the method of the present invention Process national policy 1 figure showing an embodiment of the method of the present invention (Continued)
Claims (1)
置に溝部を形成し、次いで酸素イオンを該溝部に注入し
、しかる後熱処理を行い該酸素イオン注入領域に酸化膜
を形成することを特徴とする半導体装置の製造方法。 2、前記基板に対して垂直方向から約10〜60度傾斜
させて前記酸素イオンを前記溝部に注入する、請求項1
記載の半導体装置の製造方法。[Claims] 1. A groove is formed in a semiconductor substrate at a position where an element isolation region is to be formed, and then oxygen ions are implanted into the groove, and then heat treatment is performed to form an oxide film in the oxygen ion implanted region. 1. A method of manufacturing a semiconductor device, comprising: forming a semiconductor device. 2. The oxygen ions are implanted into the trench at an angle of about 10 to 60 degrees from a direction perpendicular to the substrate.
A method of manufacturing the semiconductor device described above.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14166990A JPH0437152A (en) | 1990-06-01 | 1990-06-01 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14166990A JPH0437152A (en) | 1990-06-01 | 1990-06-01 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0437152A true JPH0437152A (en) | 1992-02-07 |
Family
ID=15297438
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14166990A Pending JPH0437152A (en) | 1990-06-01 | 1990-06-01 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0437152A (en) |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5508215A (en) * | 1993-07-15 | 1996-04-16 | Micron Technology, Inc. | Current leakage reduction at the storage node diffusion region of a stacked-trench dram cell by selectively oxidizing the floor of the trench |
KR100236720B1 (en) * | 1997-04-10 | 2000-01-15 | 김영환 | Element separating method of semiconductor device |
US6469345B2 (en) | 2000-01-14 | 2002-10-22 | Denso Corporation | Semiconductor device and method for manufacturing the same |
US6482701B1 (en) | 1999-08-04 | 2002-11-19 | Denso Corporation | Integrated gate bipolar transistor and method of manufacturing the same |
US6521538B2 (en) | 2000-02-28 | 2003-02-18 | Denso Corporation | Method of forming a trench with a rounded bottom in a semiconductor device |
US6590271B2 (en) | 2000-08-10 | 2003-07-08 | Intel Corporation | Extension of shallow trench isolation by ion implantation |
KR100442852B1 (en) * | 1997-09-12 | 2004-09-18 | 삼성전자주식회사 | Method for forming trench isolation region to embody isolation region proper for high integrated semiconductor device |
US6864532B2 (en) | 2000-01-14 | 2005-03-08 | Denso Corporation | Semiconductor device and method for manufacturing the same |
KR100540850B1 (en) * | 1997-06-26 | 2006-02-28 | 지멘스 악티엔게젤샤프트 | Integrated circuit devices including shallow trench isolation |
US7645676B2 (en) * | 2006-01-26 | 2010-01-12 | International Business Machines Corporation | Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures |
US7648869B2 (en) | 2006-01-12 | 2010-01-19 | International Business Machines Corporation | Method of fabricating semiconductor structures for latch-up suppression |
US7655985B2 (en) | 2006-01-26 | 2010-02-02 | International Business Machines Corporation | Methods and semiconductor structures for latch-up suppression using a conductive region |
US7754513B2 (en) | 2007-02-28 | 2010-07-13 | International Business Machines Corporation | Latch-up resistant semiconductor structures on hybrid substrates and methods for forming such semiconductor structures |
US7818702B2 (en) | 2007-02-28 | 2010-10-19 | International Business Machines Corporation | Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates |
WO2019101009A1 (en) * | 2017-11-27 | 2019-05-31 | 重庆伟特森电子科技有限公司 | Preparation method for sic-based umosfet, and sic-based umosfet |
-
1990
- 1990-06-01 JP JP14166990A patent/JPH0437152A/en active Pending
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5508215A (en) * | 1993-07-15 | 1996-04-16 | Micron Technology, Inc. | Current leakage reduction at the storage node diffusion region of a stacked-trench dram cell by selectively oxidizing the floor of the trench |
KR100236720B1 (en) * | 1997-04-10 | 2000-01-15 | 김영환 | Element separating method of semiconductor device |
KR100540850B1 (en) * | 1997-06-26 | 2006-02-28 | 지멘스 악티엔게젤샤프트 | Integrated circuit devices including shallow trench isolation |
KR100442852B1 (en) * | 1997-09-12 | 2004-09-18 | 삼성전자주식회사 | Method for forming trench isolation region to embody isolation region proper for high integrated semiconductor device |
US6482701B1 (en) | 1999-08-04 | 2002-11-19 | Denso Corporation | Integrated gate bipolar transistor and method of manufacturing the same |
US6469345B2 (en) | 2000-01-14 | 2002-10-22 | Denso Corporation | Semiconductor device and method for manufacturing the same |
US7354829B2 (en) | 2000-01-14 | 2008-04-08 | Denso Corporation | Trench-gate transistor with ono gate dielectric and fabrication process therefor |
US6864532B2 (en) | 2000-01-14 | 2005-03-08 | Denso Corporation | Semiconductor device and method for manufacturing the same |
US6521538B2 (en) | 2000-02-28 | 2003-02-18 | Denso Corporation | Method of forming a trench with a rounded bottom in a semiconductor device |
US6590271B2 (en) | 2000-08-10 | 2003-07-08 | Intel Corporation | Extension of shallow trench isolation by ion implantation |
US7648869B2 (en) | 2006-01-12 | 2010-01-19 | International Business Machines Corporation | Method of fabricating semiconductor structures for latch-up suppression |
US7645676B2 (en) * | 2006-01-26 | 2010-01-12 | International Business Machines Corporation | Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures |
US7655985B2 (en) | 2006-01-26 | 2010-02-02 | International Business Machines Corporation | Methods and semiconductor structures for latch-up suppression using a conductive region |
US7727848B2 (en) | 2006-01-26 | 2010-06-01 | International Business Machines Corporation | Methods and semiconductor structures for latch-up suppression using a conductive region |
US7791145B2 (en) | 2006-01-26 | 2010-09-07 | International Business Machines Corporation | Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures |
US7754513B2 (en) | 2007-02-28 | 2010-07-13 | International Business Machines Corporation | Latch-up resistant semiconductor structures on hybrid substrates and methods for forming such semiconductor structures |
US7818702B2 (en) | 2007-02-28 | 2010-10-19 | International Business Machines Corporation | Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates |
WO2019101009A1 (en) * | 2017-11-27 | 2019-05-31 | 重庆伟特森电子科技有限公司 | Preparation method for sic-based umosfet, and sic-based umosfet |
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