JPH0196923A - Epitaxial growth method - Google Patents

Abstract

PURPOSE:To make impurities in a semiconductor substrate decrease auto doping into an epitaxial layer, by performing baking at a temp. 1100 deg.C or more at reduced pressure and epitaxial growth at the temp. 900 deg.C or less at reduced pressure as well. CONSTITUTION:An n<+> type buried layer 2 having the concentration of impurities, for example, 2X10<19>cm<-3> is formed at a p-type Si substrate 1, by doping, for example, arsenic with processes of ion-implantation or diffusion. Then, the Si substrate 1 is put in, for example, a barrel furnace-type epitaxial growth device and the Si substrate 1 is baked with H2 at a temp. 1100 deg.C or more for 5 min. at such a condition of, for example 1100 deg.C and 23Torr. Even though arsenic evaporates from the buried layer in this way, no arsenic is attracted very much to the surface of the Si substrate 1 because of the fact that it is at high temp. and reduced pressure. Further, this device allows an n-type Si epitaxial layer having the concentration of the impurities, for example, 2X10<16>cm<-3> to perform epitaxial growth. The epitaxial growth is carried out at a temp. 900 deg.C or less at such a condition of, for example, 900 deg.C and 32-34Torr by using silanedichlorosilane and the like as a reaction gas. In this way no arsenic is attracted to the surface of the Si substrate 1.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an epitaxial growth method.

[Summary of the invention]

In the present invention, in an epitaxial growth method in which a semiconductor substrate is baked and then a semiconductor layer is epitaxially grown on the semiconductor substrate, the baking is performed at a temperature of 1100''C or higher under reduced pressure, and the epitaxial growth is performed under reduced pressure. By performing the process at a temperature of 900° C. or lower, autodoping of impurities in the semiconductor substrate into the semiconductor layer can be reduced.

[Conventional technology]

Conventionally, in the manufacture of semiconductor integrated circuit devices such as bipolar LSIs, a technique has been used to epitaxially grow a single crystal Si layer on a silicon (St) substrate. In this case, it is usually necessary to epitaxially grow a Si layer with a low impurity concentration on a Si substrate having a buried layer heavily doped with an impurity such as arsenic. In addition, this epitaxial growth can also be performed on the Si substrate using hydrogen (
H2) Performed after cleaning the surface by baking in an atmosphere. Conventionally, both baking and epitaxial growth have been performed at a high temperature of 1000° C. or higher.

[Problem that the invention seeks to solve]

However, according to studies by the present inventors, the conventional epitaxial growth method described above has a problem in that autodoping of impurities into the epitaxial layer occurs. That is, as shown in FIG. 5, due to the effect of autodoping the epitaxial layer with this impurity, a transition region is formed in the epitaxial layer in a portion adjacent to the buried layer. For example, the impurity concentration of the buried layer is ~2×
1019cm-1, the impurity concentration of the epitaxial layer is ~
2 x 10 "cm", the width of this transition region can be ~0.5 μm or more.

The formation of the transition region by autodoping will be explained based on the results of experiments conducted by the present inventor. FIG. 6 is a graph showing impurity concentration distribution in an epitaxial layer formed by a conventional epitaxial growth method. Here, the H2bench conditions are 1090℃ 1100℃
Using Torr, the epitaxial growth conditions were 10
A temperature of 20° C. and 1100 Torr was used. In addition, as shown in FIG. 7, the sample used in this experiment had arsenic embedded N2 in the center of the Si substrate 1, and a Si layer (
(not shown) is epitaxially grown, and the width of the transition region (Δ
d) was measured. Note that the width Δd of this transition region is
This is the distance between the epitaxial layer/Si substrate interface and the depth position where the impurity concentration of this transition region is equal to the impurity concentration of the epitaxial layer (for example, 2X10"cm-3).As can be seen from this experimental result. , Δd at χ=0 (buried layer end) is as large as approximately 1.2 μm.

When Δd is large in this way, the following problem occurs.

That is, in a bipolar LSI, for example, if Δd is large, the collector-base breakdown voltage of the bipolar transistor decreases, so in order to avoid this, it is necessary to increase the thickness of the epitaxial layer. However, increasing the thickness of the epitaxial layer increases the series resistance of the collector, which reduces the collector charging time τ, which is one of the factors that determines the operating speed of bipolar transistors.
, ゛ increases, leading to a decrease in operating speed. - On the other hand, as can be seen from the large Δd2 of about 1 μm at x=8 mm in Figure 6, autodoping in the lateral direction (direction parallel to the substrate surface) is also large; Impurity compensation occurs in the p layer for separation.

In order to prevent this, it is possible to increase the impurity concentration of this p layer, but this increases the parasitic capacitance M Cr between the collector substrate and results in a decrease in the operating speed of the transistor. There was a problem. For these reasons, improvement in the operating speed of bipolar LSIs has been hindered.

This autodoping is becoming a serious problem as LSIs become smaller and faster, and the thickness of the required epitaxial layer becomes thinner.

Therefore, an object of the present invention is to provide an epitaxial growth method capable of reducing autodoping problems of impurities in a semiconductor substrate into an epitaxial layer.

[Means for solving problems]

The inventor of the present invention conducted various studies to solve the above-mentioned problems, and as a result, discovered the following facts. That is, the autodoping of impurities increases as the impurity concentration of the buried layer increases. Moreover, this autodoping becomes more pronounced as the epitaxial growth temperature is higher, the pressure during epitaxial growth is lower, and H! The higher the baking temperature is under reduced pressure,
It turns out that there are few.

Based on the above facts, the autodoping of arsenic can be considered as follows.

■Arsenic evaporated from the buried layer in the semiconductor substrate causes autodoping.

(2) After arsenic is evaporated by H2 baking or the like, it is adsorbed and captured on the surface of the semiconductor substrate, and is incorporated into the epitaxial layer during epitaxial growth.

■ Evaporation of arsenic occurs fairly easily and at high temperatures (900 to 1
(100°C), the vapor pressure tends to be almost saturated.

■The higher the temperature and the lower the pressure, the less adsorption of arsenic to the semiconductor substrate occurs.

The present inventors optimized the baking conditions and epitaxial growth conditions based on the above studies, and as a result, they came up with the present invention.

That is, the present invention provides an epitaxial growth method in which a semiconductor substrate is baked and then a semiconductor layer is epitaxially grown on the semiconductor substrate, in which the baking is performed at a temperature of 1100° C. or higher under reduced pressure, and the epitaxial growth is performed at a temperature of 900° C. or higher under reduced pressure. I try to do it at a temperature below ℃.

[Effect]

According to the above-mentioned means, baking is performed under reduced pressure for 110 minutes.
By performing baking at a temperature of 0° C. or higher, it is possible to reduce the probability that impurities evaporated from the semiconductor substrate by this baking will be adsorbed to the surface of the semiconductor substrate. In addition, the subsequent epitaxial growth was performed under reduced pressure at 90°C.
By carrying out the process at a temperature of 00''C or less, it is possible to prevent the progress of adsorption of impurities onto the surface of the semiconductor substrate.

This makes it possible to reduce the amount of impurities incorporated into the epitaxially grown semiconductor layer, and thus to reduce autodoping of impurities in the semiconductor substrate into the semiconductor layer.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

As shown in FIG. 2, first, for example, a p-type Si substrate 1 is doped with, for example, arsenic by ion implantation or diffusion to form an n-type buried layer 2 with an impurity concentration of, for example, 2×10 cm. Next, this Si substrate 1 is placed in, for example, a barrel furnace type epitaxial growth apparatus (not shown), and this Si substrate 1 is baked in H2 for 5 minutes at, for example, 1100° C. and 23 Torr. 2
Although arsenic evaporates from the Si substrate 1, this arsenic is hardly adsorbed on the surface of the Si substrate 1 because the temperature is high and the pressure is reduced.

Next, as shown in FIG. 3, an n-type Si epitaxial layer 3 having an impurity concentration of 2.times.10 "cm-", for example, is epitaxially grown on this Si substrate 1. Then, as shown in FIG. This epitaxial growth is performed using silane (Si
H4), dichlorosilane (SiHzClx), etc.
For example, the adsorption of arsenic onto the surface of the Si substrate 30 hardly progresses by performing it under conditions of 900° C. and 32 to 34 Torr.

FIG. 1 shows the impurity concentration distribution in the Si epitaxial layer 3 formed in this manner.

As shown in FIG. 1, the amount of autodoping into the Si epitaxial layer 3 by arsenic evaporated from the buried layer 2 is small, and the width Δd4 of the transition region at x-Omo+ is equal to the impurity concentration 2X IQ "c1++-". Approximately 0 when measured at the place
．． It is 26 μm. This value is extremely small, about half or less compared to the case where conventional epitaxial growth methods are used. Also, the distance from the buried layer 2 - x = 0.8a
No lateral autodoping is observed as seen from the sS 1.6 ms, 2.4 ml1 data.

In this way, according to this embodiment, the H2 bake is performed at 1100
℃ and 23 Torr, and the epitaxial growth is performed at 900℃ and 32 to 34 Torr, so lateral autodoping is virtually eliminated, and the region where autodoping is affected is in the buried layer 2. In addition, the autodoping in this buried layer 2 portion is also small, and the width of the transition region can be reduced to about half or less of the conventional width. Therefore, when the epitaxial growth method according to this embodiment is applied to, for example, the manufacture of bipolar LSI, the thickness of the Si epitaxial layer 3 can be made smaller than that of the conventional method, so the series resistance of the collector can be made small. Therefore, the collector charging time τ,' can be reduced. Moreover, since lateral autodoping is eliminated, the parasitic capacitance CtS between the collector substrates can also be reduced. As a result, the operating speed of the bipolar transistor can be improved, and therefore the operating speed of the bipolar LSI can be improved.

On the other hand, FIG. 4 shows the data of an experiment conducted for comparison with this example, in which H2 bake and epitaxial growth were performed with only the H2 bake temperature being 950°C and the other conditions being the same as in this example. The data is shown below. As is clear from this result, when the H2 bake temperature is 950°C, Δd5 at x=omm becomes extremely large, approximately 1.7 μm, and it is therefore clear that autodoping cannot be prevented at this bake temperature. .

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, the pressure during H22 baking and epitaxial growth may be different from that in the above embodiments, for example, 50
The pressure may be approximately Torr.

Furthermore, the present invention is applicable to bipolar LSIs as well as bipolar LSIs.
It can be applied to manufacturing various semiconductor integrated circuit devices using CMO3LSI and other epitaxial layers.

〔Effect of the invention〕

According to the present invention, by performing baking at a temperature of 1100°C or higher under reduced pressure and performing epitaxial growth at a temperature of 900°C or lower under reduced pressure, autodoping of impurities in the semiconductor substrate into the epitaxial layer is achieved. can be reduced.

[Brief Description of the Drawings] FIG. 1 is a graph showing the impurity concentration distribution in an epitaxial layer formed by an epitaxial growth method according to an embodiment of the present invention, and FIGS. 2 and 3 are graphs according to an embodiment of the present invention. Cross-sectional views showing the epitaxial growth method step by step,
FIG. 4 is a graph showing the results of an experiment conducted for comparison with an epitaxial growth method according to an embodiment of the present invention;
The figure is a graph to explain the phenomenon of auto-doping when a conventional epitaxial growth method is used. Figure 6 is a graph showing the impurity concentration distribution in an epitaxial layer formed by a conventional epitaxial growth method. Figure 7 is an auto-doping graph. FIG. 2 is a plan view showing a semiconductor substrate used in an experiment to investigate doping. Explanation of main symbols in the drawings 1: Si substrate (semiconductor substrate), 2: buried layer, 3: Si epitaxial layer (semiconductor layer). Agent Patent Attorney Tadashi Sugiura Chijiebi 5 ~ Shivru 1 no i+JT] 5\Uno>'! %／'
m) Figure 1 Figure 3 Dimensions (qm) of epitaxial layer A, strength, etc. 4th
Figure 5 Epitaxial layer of AlB 6' Ugezuka (, Llm
) Figure 6

Claims (1)

[Claims] In an epitaxial growth method in which a semiconductor substrate is baked and then a semiconductor layer is epitaxially grown on the semiconductor substrate, the baking is performed under reduced pressure for 11 days.
An epitaxial growth method characterized in that the epitaxial growth is performed at a temperature of 00°C or higher, and the epitaxial growth is performed under reduced pressure at a temperature of 900°C or lower.