JPH02302043A - Mos type semiconductor device and its manufacture - Google Patents
Mos type semiconductor device and its manufactureInfo
- Publication number
- JPH02302043A JPH02302043A JP12231089A JP12231089A JPH02302043A JP H02302043 A JPH02302043 A JP H02302043A JP 12231089 A JP12231089 A JP 12231089A JP 12231089 A JP12231089 A JP 12231089A JP H02302043 A JPH02302043 A JP H02302043A
- Authority
- JP
- Japan
- Prior art keywords
- region
- source
- gettering
- channel region
- impurities
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 239000012535 impurity Substances 0.000 claims abstract description 35
- 238000005247 gettering Methods 0.000 claims abstract description 24
- 150000002500 ions Chemical class 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 14
- 238000011109 contamination Methods 0.000 abstract description 10
- 230000000694 effects Effects 0.000 abstract description 10
- 238000010438 heat treatment Methods 0.000 abstract description 6
- 239000000356 contaminant Substances 0.000 abstract description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract 2
- 229910052757 nitrogen Inorganic materials 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 11
- 239000013078 crystal Substances 0.000 description 9
- 239000010410 layer Substances 0.000 description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 229910001385 heavy metal Inorganic materials 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［発明の目的コ
（産業上の利用分野）
本発明は、ＭＯＳ型半導体装置に係わり、特にイオン注
入技術を利用してチャネル領域の不純物低減をはかった
ＭＯＳ型半導体装置及びその製造方法に関する。[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) The present invention relates to a MOS type semiconductor device, and particularly to a MOS type semiconductor device in which impurities in a channel region are reduced using ion implantation technology. and its manufacturing method.
（従来の技術）
従来、半導体回路素子の製造において、正金属、炭素及
び酸素等の不純物による汚染は、素子の電気的特性を大
きく劣化させる。例えば、ＭＯ８素子においては、これ
らの汚染は易動度、リーク電流及び閾値電圧等へ影響を
及はすことか知られている。そこで従来より、半導体単
結晶を作成する際に、これらの不純物の混入を抑えるた
めに種々の工夫がなされてきた。(Prior Art) Conventionally, in the manufacture of semiconductor circuit elements, contamination by impurities such as positive metals, carbon, and oxygen greatly deteriorates the electrical characteristics of the elements. For example, it is known that these contaminants affect mobility, leakage current, threshold voltage, etc. in MO8 devices. Therefore, various efforts have been made to suppress the incorporation of these impurities when producing semiconductor single crystals.
しかし、シリコン単結晶においては、依然として１０”
ａｔｌｌｓ／ｃ１１３程度の酸素不純物が存在してい
る。また、素子作成の工程を経過する間に重金属や炭素
等の不純物が単結晶に混入していく可能性も大きい。こ
のため、これら不純物に基づく準位にキャリアがトラッ
プされ、本来の素子特性が十分に引き出されていないの
が現状であった。特に、ＭＯＳトランジスタにおいては
、チャネル領域に上記不純物の汚染があると、素子特性
が著しく低下する問題かあった。However, in silicon single crystal, it is still 10”
Oxygen impurities of about atlls/c113 are present. Furthermore, there is a high possibility that impurities such as heavy metals and carbon may be mixed into the single crystal during the process of producing the device. For this reason, carriers are trapped in levels based on these impurities, and the original device characteristics are not fully brought out. In particular, in MOS transistors, if the channel region is contaminated with the impurities, there is a problem in that device characteristics are significantly degraded.
（発明が解決しようとする課題）
このように従来、ＭＯＳ型半導体装置の形成において、
重金属、炭素及び酸素等の不純物によって素子形成領域
の単結晶が汚染され、この不純物汚染により素子特性が
劣化する問題があった。(Problems to be Solved by the Invention) As described above, conventionally, in the formation of a MOS type semiconductor device,
There is a problem in that the single crystal in the element formation region is contaminated by impurities such as heavy metals, carbon, and oxygen, and the element characteristics deteriorate due to this impurity contamination.
本発明は、上記事情を考慮してなされたもので、その目
的とするところは、素子形成領域における半導体単結晶
の不純物汚染を低減することができ、素子特性の向上を
はかり得るＭＯＳ型半導体装置及びその製造方法を提供
することにある。The present invention has been made in consideration of the above circumstances, and its purpose is to provide a MOS type semiconductor device that can reduce impurity contamination of a semiconductor single crystal in an element formation region and improve element characteristics. An object of the present invention is to provide a method for manufacturing the same.
［発明の構成］
（課題を解決するための手段）
本発明の骨子は、イオン注入法を応用したゲッタリング
効果により、不純物汚染による素子特性の劣化を防止す
ることにある。[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to prevent deterioration of device characteristics due to impurity contamination by a gettering effect using an ion implantation method.
即ち本発明は、半導体基板のチャネル領域上にゲート絶
縁膜を介してゲート電極を形成すると共に、チャネル領
域の両側にソース・ドレイン領域を形成したＭＯＳ型半
導体装置において、ソース・ドレイン領域の一部に電気
的に不活性な元素のイオン注入を行うことにより、チャ
ネル領域の不純物をゲッタリングするためのゲッタリン
グ領域を形成するようにしたものである。That is, the present invention provides a MOS type semiconductor device in which a gate electrode is formed on a channel region of a semiconductor substrate via a gate insulating film, and source/drain regions are formed on both sides of the channel region. A gettering region for gettering impurities in the channel region is formed by implanting ions of an electrically inactive element into the channel region.
また本発明は、上記ＭＯＳ型半導体装置の製造方法にお
いて、第１導電型半導体基板上にゲート絶縁膜を介して
ゲート電極を形成したのち、基板の表面におけるゲート
電極の両側に第２導電型の不純物を導入してソース・ド
レイン領域を形成し、次いでソース・ドレイン領域の一
部に電気的に不活性な元素をイオン注入し、次いで基板
を熱処理して不純物ゲッタリングのためのゲッタリング
領域を形成するようにした方法である。The present invention also provides a method for manufacturing a MOS type semiconductor device, in which a gate electrode is formed on a first conductive type semiconductor substrate via a gate insulating film, and then a second conductive type is formed on both sides of the gate electrode on the surface of the substrate. Impurities are introduced to form source/drain regions, then an electrically inert element is ion-implanted into part of the source/drain regions, and the substrate is then heat-treated to form gettering regions for impurity gettering. This is the method used to form the structure.
（作用）
本発明によれば、ソース・ドレイン領域の一部（特に、
チャネル領域に近い部分）にシリコン等の不活性な元素
のイオン注入を行い、その後に熱処理を行うことにより
、イオン注入によるダメージで欠陥（ゲッタリング層）
を発生させる。そして、この欠陥に汚染不純物（重金属
。(Function) According to the present invention, part of the source/drain region (particularly,
By implanting ions of an inactive element such as silicon into the area (near the channel region) and then performing heat treatment, defects (gettering layer) due to damage caused by the ion implantation are eliminated.
to occur. And this defect is contaminated by impurities (heavy metals).
炭素、酸素等）をゲッタリングさせる。その結果、素子
のチャネル領域等の汚染が問題となる部分から、素子特
性を劣化させる不純物を取り除くことができる。gettering carbon, oxygen, etc.). As a result, impurities that degrade device characteristics can be removed from areas where contamination is a problem, such as the channel region of the device.
このようにして、チャネル領域の汚染が大きく取り除か
れ、シリコン基板におけるＭＯＳトランジスタでは、従
来プロセスによる素子と比較して、リーク電流のレベル
で約１桁、易動度で約２割の向上が得られる。In this way, contamination in the channel region is largely removed, and MOS transistors on silicon substrates have improved leakage current by about one order of magnitude and mobility by about 20% compared to devices manufactured using conventional processes. It will be done.
（実施例） 以下、本発明の詳細を図示の実施例によって説明する。(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.
第１図は本発明の一実施例に係わるＭＯＳトランジスタ
の製造工程を示す断面図である。まず、第１図（ａ）に
示す如く、面方位（１００）。FIG. 1 is a cross-sectional view showing the manufacturing process of a MOS transistor according to an embodiment of the present invention. First, as shown in FIG. 1(a), the plane orientation (100).
比抵抗６〜８Ωｃｎのｐ型Ｓｉ基板１０上に素子分離用
酸化膜１１を形成し、素子形成領域上にゲート酸化膜１
２を形成する。さらに、ゲート酸化膜１２上にポリＳｉ
からなるゲート電極１３を形成し、ソース・ドレイン形
成のための不純物イオン注入を行う。その後、不純物活
性化のために、１０００℃で５０分の熱処理を行い、ソ
ースφドレイン領域１４ａ、１４ｂを形成する。An oxide film 11 for element isolation is formed on a p-type Si substrate 10 with a specific resistance of 6 to 8 Ωcn, and a gate oxide film 1 is formed on the element formation region.
form 2. Further, a poly-Si film is formed on the gate oxide film 12.
A gate electrode 13 is formed, and impurity ions are implanted to form sources and drains. Thereafter, heat treatment is performed at 1000° C. for 50 minutes to activate the impurities, thereby forming source φ drain regions 14a and 14b.
ここまでは、通常のＭＯＳ）ランジスタ製造工程と同様
であるが、本実施例では、この後に第１図（ｂ）に示す
如く、ゲート電極１３及びソースφドレイン領域１４ａ
、１４ｂの一部を除く領域にレジスト１５を形成し、こ
、のレジスト１５をマスクにソース−ドレイン領域１４
ａ。The steps up to this point are the same as the normal MOS) transistor manufacturing process, but in this embodiment, as shown in FIG.
, 14b is formed in the region excluding a part of the source-drain region 14. Using this resist 15 as a mask, the source-drain region 14 is
a.
１４ｂの約３０％の領域にＳｉ＋イオン注入を行い、ゲ
ッタリング層１６を形成する。注入条件は、加速電圧５
０ＫｃＶ 、 ドーズ量Ｉ Ｘ １０”ａｍ−２とし
た。また、注入領域はゲート電極下のチャネル領域の近
傍とした。Si+ ions are implanted into about 30% of the region 14b to form a gettering layer 16. The injection conditions are an acceleration voltage of 5
0 KcV and a dose of I.times.10" am.sup.-2. The implanted region was located near the channel region under the gate electrode.
次いで、窒素雰囲気中で９００℃の熱処理を行い、第１
図（Ｃ）に示す如く、チャネル領域の汚染不純物をゲッ
タリング層１６に集める。第２図は、熱処理温度による
ゲッタリング効果の違いを見るために、Ｓ ＩＭＳを用
いてチャネル領域の不純物分析を行った結果である。従
来例（不純物ＪＩＩＯ１８ｃｍ−３）に比して、チャネ
ル領域の汚染は、１０００℃以下の温度でも不純物ｆｆ
ｉ １０”ｃ「’以下と十分に取り除かれているのが判
る。Next, heat treatment is performed at 900°C in a nitrogen atmosphere, and the first
As shown in Figure (C), contaminant impurities in the channel region are collected in the gettering layer 16. FIG. 2 shows the results of impurity analysis of the channel region using SIMS in order to see the difference in the gettering effect depending on the heat treatment temperature. Compared to the conventional example (impurity JIIO18cm-3), contamination of the channel region is reduced even at temperatures below 1000°C due to impurity ff.
i 10"c"' It can be seen that it has been sufficiently removed.
ここでは、不純物として特に鉄（Ｆ ｅ）を示している
が、他の元素も略同様な傾向であった。Here, iron (Fe) is particularly shown as an impurity, but other elements had almost the same tendency.
これ以降は、通常のＭＯＳトランジスタ製造工程と同様
に、第１図（ｄ）に示す如く、全面に層間絶縁膜１７を
形成してこの絶縁膜１７にコンタクトホールを設け、さ
らにソース・ドレイン領域１４ａ、１４ｂにそれぞれ接
続されるＡｊＪ電極１８を形成することにより、ＭＯＳ
トランジスタが完成することになる。From this point on, in the same way as in the normal MOS transistor manufacturing process, as shown in FIG. , 14b, the MOS
The transistor will be completed.
なお、本実施例では素子寸法は０．５μｍルールで単体
ＭＯＳ）ランジスタを形成したが、この時の素子の特性
結果を第３図に示す。参考のために、ゲッタリングを行
わずに形成した素子の特性を図中に破線で示す。第３図
から、ゲッタリングによりゲート電圧Ｖｇに対するドレ
イン電流１ｄが増加し、駆動力が上がっていることが判
る。この時、相互コンダクタンスＧｍは、約２割程度増
加していることから、キャリアの易動度も２割程度増加
していることが判る。また、リーク電流においても、Ｖ
ｇ−ＯＶにお１）で、１桁近く低減していることが判り
、素子特性の大幅な改善が行われていることが判った。In this example, a single MOS transistor was formed using the 0.5 .mu.m rule for element dimensions, and the results of the characteristics of the element at this time are shown in FIG. For reference, the characteristics of an element formed without gettering are shown by broken lines in the figure. From FIG. 3, it can be seen that gettering increases the drain current 1d relative to the gate voltage Vg, increasing the driving force. At this time, since the mutual conductance Gm increases by about 20%, it can be seen that the carrier mobility also increases by about 20%. Also, in terms of leakage current, V
It was found that g-OV in 1) was reduced by nearly an order of magnitude, and it was found that the device characteristics were significantly improved.
この効果はＳｔ単結晶基板のみならず、絶縁膜上にＳｔ
単結晶層を形成したＳ ＯＩ （ＳｉｌｉｃｏｎＯｎ
Ｉｎ５ｕｌａｔｏｒ）にも応用できる。特に、シラン（
ＳｉＨ４）ガスの熱分解による多結晶シリコンを原料と
し、２酸化シリコン（Ｓｉ０２）を絶縁膜及び保護膜と
して用いたＳＯＩ技術では、膜の堆積過程或いは単結晶
化過程に、酸素等が不純物として多量に混入する。本実
施例によれば、これらの汚染を効果的１ど取り除くこと
ができ、このようなＳｏ！膜に形成した素子の特性を大
幅に向上できる。This effect is applicable not only to St single crystal substrates but also to St
SOI (SiliconOn) with a single crystal layer formed
It can also be applied to In5ulator). In particular, silane (
In SOI technology, which uses polycrystalline silicon produced by thermal decomposition of SiH4) gas as a raw material and uses silicon dioxide (Si02) as an insulating film and a protective film, large amounts of oxygen and other impurities are generated as impurities during the film deposition process or single crystallization process. be mixed into. According to this embodiment, these contaminants can be effectively removed, and such contamination can be effectively removed. The characteristics of elements formed on the film can be significantly improved.
また、前記イオン注入の条件として、イオン注入時の基
板温度を２００”Ｃ以下に保つと、イオン注入による欠
陥を、ゲッタリング効果を得た後に熱処理により効果的
に消失させることができた。さらに、イオン注入時の加
速電圧は、上記以外に３０〜４００ ＫｅＶの範囲であ
れば、同様の効果が得られた。In addition, as a condition for the ion implantation, if the substrate temperature during ion implantation was kept at 200''C or less, defects caused by ion implantation could be effectively eliminated by heat treatment after obtaining the gettering effect. Similar effects were obtained if the acceleration voltage during ion implantation was in the range of 30 to 400 KeV other than the above.
かくして本実施例によれば、ＭＯＳ）ランジスタのソー
ス・ドレイン領域１．４ａ、１４ｂのチャネル領域に近
接する領域にＳｉのイオン注入を行いゲッタリング層１
６を形成することにより、チャネル領域の不純物をゲッ
タリングすることができ、チャネル領域における不純物
量を著しく低減することができる。また、ソース・ドレ
イン領域１４ａ、 １４ｔ）の一部に注入するイオン
は基板１０と同じＳｉであるので、該イオン注入により
ソース争ドレイン領域１４ａ１１４ｂの導電型が変化す
る等の不都合はない。Thus, according to the present embodiment, Si ions are implanted into the source/drain regions 1.4a and 14b of the MOS transistor in the vicinity of the channel region to form the gettering layer 1.
By forming 6, impurities in the channel region can be gettered, and the amount of impurities in the channel region can be significantly reduced. Furthermore, since the ions implanted into a portion of the source/drain regions 14a, 14t) are the same Si as those of the substrate 10, there is no problem such as a change in the conductivity type of the source/drain regions 14a, 114b due to the ion implantation.
従って、ＭＯＳトランジスタの特性を大幅に向上するこ
とができ、その有用性は絶大である。Therefore, the characteristics of the MOS transistor can be greatly improved, and its usefulness is tremendous.
なお、本発明は上述した実施例に限定されるものではな
い。前記ソース・ドレイン領域の一部に注入するイオン
はＳ ｊに限るものではなく、不活性で且つ拡散係数が
小さいものであればよく、例えばゲルマニウム等を用い
ることができる。また、イオン注入の深さ１面積及び注
入量等は仕様に応じて適宜変更可能である。但し、ゲッ
タリング層があまりに大きいとソース・ドレインに悪影
響を及ぼす虞れがあるため、一般にはイオン注入深さ及
び面積はソース・ドレイン領域の５０％以下が望ましく
、イオン注入量は１０１６〜１０Ｉ８ｃＩｌ−’の範囲
が望ましい。また、前記半導体単結晶基板としてサファ
イア上に形成したシリコン単結晶層（ＳＯ３）を用いる
ことも可能であり、さらにゲルマニウム等の他の半導体
ｔｉを用いることも可能である。その他、本発明の要旨
を逸脱しない範囲で、種々変形して実施することができ
る。Note that the present invention is not limited to the embodiments described above. The ions to be implanted into a part of the source/drain region are not limited to Sj, but may be any ion as long as it is inactive and has a small diffusion coefficient; for example, germanium or the like can be used. Furthermore, the depth, area, and amount of ion implantation can be changed as appropriate depending on specifications. However, if the gettering layer is too large, it may have an adverse effect on the source/drain, so generally it is desirable that the ion implantation depth and area be 50% or less of the source/drain region, and the ion implantation amount should be 1016 to 10I8cIl- ' range is desirable. Further, it is also possible to use a silicon single crystal layer (SO3) formed on sapphire as the semiconductor single crystal substrate, and furthermore, it is also possible to use other semiconductors such as germanium. In addition, various modifications can be made without departing from the gist of the present invention.
［発明の効果］
以上詳述したように本発明によれば、ソース−ドレイン
領域の一部に不活性な元素のイオン注入を行いゲッタリ
ング層を形成しているので、チャネル領域の不純物汚染
をゲッタリング効果により取り除くことができ、素子特
性の向上をはかり得る。[Effects of the Invention] As detailed above, according to the present invention, since a gettering layer is formed by implanting ions of an inert element into a part of the source-drain region, impurity contamination of the channel region can be prevented. It can be removed by the gettering effect, and device characteristics can be improved.
第１図は本発明の一実施例に係わるＭＯＳトランジスタ
の製造工程を示す断面図、第２図及び第３図はそれぞれ
上記実施例の効果を説明するためのもので、第２図は温
度に対する不純物量の変化を示す特性図、第３図はゲー
トｉｔｓ圧に対するドレイン電流の変化を示す特性図で
ある。
１０・・・Ｓｔ基板、
１１・・・素子分離用酸化膜、
ユ２・・・ゲート酸化膜、
１３・・・ゲート電極、
１４ａ、１４ｂ・・・ソース・ドレイン領域、１５・・
・レジスト、
１６・・・ゲッタリング層、
１７・・・層間絶縁膜、
１８・・・ｉ電極。FIG. 1 is a cross-sectional view showing the manufacturing process of a MOS transistor according to an embodiment of the present invention, and FIGS. 2 and 3 are for explaining the effects of the above embodiment, respectively. FIG. 3 is a characteristic diagram showing changes in the amount of impurities, and FIG. 3 is a characteristic diagram showing changes in drain current with respect to gate its pressure. DESCRIPTION OF SYMBOLS 10... St substrate, 11... Oxide film for element isolation, U2... Gate oxide film, 13... Gate electrode, 14a, 14b... Source/drain region, 15...
・Resist, 16... Gettering layer, 17... Interlayer insulating film, 18... i-electrode.
Claims (2)
してゲート電極を形成すると共に、チャネル領域の両側
にソース・ドレイン領域を形成したＭＯＳ型半導体装置
において、前記ソース・ドレイン領域の一部に電気的に
不活性な元素のイオン注入を行い、前記チャネル領域の
不純物をゲッタリングするためのゲッタリング領域を形
成してなることを特徴とするＭＯＳ型半導体装置。(1) In a MOS semiconductor device in which a gate electrode is formed on a channel region of a semiconductor substrate via a gate insulating film, and source/drain regions are formed on both sides of the channel region, a part of the source/drain region is 1. A MOS type semiconductor device, characterized in that a gettering region for gettering impurities in the channel region is formed by implanting ions of an electrically inactive element.
ゲート電極を形成する工程と、前記基板の表面における
ゲート電極の両側に第２導電型の不純物を導入してソー
ス・ドレイン領域を形成する工程と、前記ソース・ドレ
イン領域の一部に電気的に不活性な元素をイオン注入し
たのち熱処理する工程とを含むことを特徴とするＭＯＳ
型半導体装置の製造方法。(2) A step of forming a gate electrode on a first conductivity type semiconductor substrate via a gate insulating film, and introducing impurities of a second conductivity type on both sides of the gate electrode on the surface of the substrate to form source/drain regions. and a step of ion-implanting an electrically inert element into a portion of the source/drain region and then heat-treating the source/drain region.
A method for manufacturing a type semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12231089A JP2718757B2 (en) | 1989-05-16 | 1989-05-16 | MOS type semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12231089A JP2718757B2 (en) | 1989-05-16 | 1989-05-16 | MOS type semiconductor device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02302043A true JPH02302043A (en) | 1990-12-14 |
| JP2718757B2 JP2718757B2 (en) | 1998-02-25 |
Family
ID=14832795
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12231089A Expired - Fee Related JP2718757B2 (en) | 1989-05-16 | 1989-05-16 | MOS type semiconductor device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2718757B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002118265A (en) * | 2000-10-06 | 2002-04-19 | Semiconductor Energy Lab Co Ltd | Method for fabricating semiconductor device |
| JP2003045880A (en) * | 2001-07-31 | 2003-02-14 | Mitsubishi Electric Corp | Semiconductor device and its fabricating method |
| JP2009246381A (en) * | 2009-07-16 | 2009-10-22 | Renesas Technology Corp | Method of manufacturing semiconductor device, and mis transistor |
-
1989
- 1989-05-16 JP JP12231089A patent/JP2718757B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002118265A (en) * | 2000-10-06 | 2002-04-19 | Semiconductor Energy Lab Co Ltd | Method for fabricating semiconductor device |
| JP2003045880A (en) * | 2001-07-31 | 2003-02-14 | Mitsubishi Electric Corp | Semiconductor device and its fabricating method |
| JP2009246381A (en) * | 2009-07-16 | 2009-10-22 | Renesas Technology Corp | Method of manufacturing semiconductor device, and mis transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2718757B2 (en) | 1998-02-25 |
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