JPH06188256A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for the manufacture of a semiconductor device of LDD structure free from junction leakage failure. CONSTITUTION:The title method for manufacturing semiconductor devices consists of a process wherein a gate oxide film 2 is formed on a semiconductor substrate 1, and then a gate electrode 3 is formed thereon; process wherein an ion is implanted in a low impurity concentration to form an n<->-type source region 4 and n<->-type drain region 5; process wherein the gate oxide film 2 is etched, and then a polycrystalline silicon film 6a is formed to cover the gate electrode 3; process wherein a silicon single-crystal layer 7 is formed on the substrate 1; process wherein a CVD oxide film 8 is formed and then etched back to form spacers 9 and 10; and process wherein an ion is implanted in a high impurity concentration to form an n<+>-type source region 11 and n<+>-type drain region 12. This reduces the stress between the substrate 1 and spacers 9 and 10, and thus makes it possible to manufacture a semiconductor device of LDD structure free from junction leakage failure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to an LDD (Lightly Do) having no junction leak defect.
The present invention relates to a method for manufacturing a semiconductor device having a ped drain structure.

[0002]

2. Description of the Related Art The LDD structure is effective in preventing the reliability deterioration due to hot electrons (hot carriers) which is a problem when the transistor is miniaturized. A general method for manufacturing an LDD / MOS is to thermally oxidize a p-type semiconductor substrate (hereinafter, simply referred to as a substrate) to form a gate oxide film, and form a gate electrode with polycrystalline silicon on the p-type semiconductor substrate, and then to reduce impurities. The source and drain regions of high concentration are formed by ion implantation, a spacer (sidewall) is usually formed on the side surface of the gate electrode by SiO ₂ , and the source / drain regions of high impurity concentration are formed again by ion implantation.

[0003]

However, the spacer having the LDD structure formed by the conventional method as described above has the following problems.
Since it is in direct contact with the upper surface of the substrate, stress is generated in that portion. In addition, when high impurity concentration ion implantation is performed to the low impurity concentration source / drain regions where such stress is generated, oxygen atoms in the gate oxide film enter the substrate to form dislocation loops, This leads to a problem that a junction leak defect occurs between the source / drain region and the substrate.

As a means for suppressing the stress induced in the step of forming such a spacer, for example, JP-A-3-320
As disclosed in Japanese Patent Publication No. 30, after the step of forming the source / drain regions having a low impurity concentration, a polycrystalline Si thin film is deposited on the entire surface, and then anisotropic etching is performed to extend along the side surface of the gate electrode. A manufacturing method has been proposed in which a source / drain region having a high impurity concentration is formed after providing a Si spacer. However, in this method, since ion implantation with a high impurity concentration is performed with the gate insulating film (gate oxide film) being deposited, the above-mentioned dislocation loop is formed and the problem of defective junction leakage cannot be solved. .

It is an object of the present invention to provide a method of manufacturing a semiconductor device that solves the above problems of the prior art.

[0006]

According to the present invention, a step of forming a gate electrode after forming a gate oxide film on a semiconductor substrate and a step of ion-implanting a low impurity concentration to form an n ⁻ type source / drain region. And a step of forming a polycrystalline silicon film so as to cover the gate electrode after etching the gate oxide film, and a step of forming a silicon single crystal layer by removing the oxide film on the substrate so as not to remain. When,
Manufacturing of a semiconductor device comprising: a step of forming a CVD oxide film and then etching it back to form a spacer; and a step of ion-implanting a high impurity concentration to form an n ⁺ type source / drain region. Is the way.

The thickness of the silicon single crystal layer is preferably at least 1000Å.

[0008]

[Operation] According to the present invention, at least a silicon single crystal layer having a coefficient of thermal expansion which is not different from that of the substrate is provided between the spacer and the substrate.
Since the stress can be reduced by forming the film with a film thickness of 1000 Å, it is possible to suppress defects generated in the substrate when forming the source region and the drain region having a high impurity concentration.

According to the results of various researches and investigations by the present inventors, the thickness of the silicon single crystal layer is set to at least 1000 Å because the magnitude of this stress is maximum near the substrate surface. This is due to the fact that it is known to affect up to about 600 Å in the depth direction.

[0010]

Embodiments of the present invention will be described below with reference to the manufacturing process of FIG.
It will be explained based on. As shown in FIG. 1 (a), a gate is formed on the p-type semiconductor substrate 1.
Forming a oxide film 2 and forming a thin film on it by low pressure CVD
Form a 3500Å polycrystalline silicon layer and₃Thermal diffusion method
The polycrystalline silicon layer is made n-type by. And generated
The PSG film formed is etched to form an n-type polycrystalline silicon layer.
Forming, photo patterning and etching
Form electrode 3 and use this gate electrode 3 as a mask to reduce impurities
Concentration of P ⁺LDD structure by ion implantation
N^-Mold source regions 4 and n^-Shape the drain region 5
To achieve. Next, as shown in FIG. 1 (b), the gate acid on the substrate 1 is
The oxide film 2 is etched to form the gate electrodes 3, n^-Type source
Regions 4 and n^-On the drain region 5 of polycrystalline silicon
The oxide film 6 is formed. At this time, n^-Mold source area 4
And n^-An oxide film with a thickness of 250 Å on the drain region 5
Is formed, and the film thickness is formed on the upper portion and the side wall portion of the gate electrode 3.
A 1000Å oxide film is formed. Then, as shown in Fig. 1 (c), hydrofluoric acid solution was used to
Etching the oxide film to a thickness of 300 Å, n^-Type source area
Zone 4 and n^-Silicon on the mold drain region 5
The gate electrode is removed while removing the oxide film 6 so as not to remain.
3 on the upper and side walls of the polycrystalline silicon oxide film 6a.
Form to leave 0 Å or more. As shown in Fig. 1 (d), the CVD method
N growth device^-Mold source regions 4 and n^-Type dray
A 1000 Å silicon single crystal layer 7 is grown on the region 5.
It At this time, SiO₂Silicon single crystal 7 does not grow above
Therefore, silicon is not formed on the top and side walls of the gate electrode 3.
The single crystal layer does not grow. Then, by the CVD method
About 3000Å SiO₂Form layer 8. Then, as shown in Fig. 1 (e), SiO₂Anisotropic in layer 8
Etch back is performed to remove sidewalls on both sides of the gate electrode 3.
Spacers 9 and 10 are formed as
Recon oxide film 6a (gate electrode 3), spacers 9 and 10
As mask with high impurity concentration⁺Ion implantation
By n⁺Mold source regions 11 and n⁺Type drain region
Forming twelve. Then, heat treatment is applied to⁺Type source
Regions 11 and n⁺The mold drain region 12 is activated.

[0011]

As described above, according to the present invention,
Since the single crystal silicon layer is formed between the spacer and the substrate, defects in the substrate at the time of ion implantation with a high impurity concentration for forming the n ⁺ type source / drain regions can be suppressed, and n ⁺ It is possible to supply a high-quality semiconductor device having no junction leak defect between the type source and the n ⁺ type drain and the substrate.

[Brief description of drawings]

FIG. 1 is a process drawing showing an example of the present invention.

[Explanation of symbols]

1 p-type semiconductor substrate (substrate) 2 gate oxide film 3 gate electrode 4 n ^- type source region 5 n ^- type drain region 6 polycrystalline silicon oxide film 7 silicon single crystal layer 8 SiO ₂ layer 9, 10 spacer 11 n ⁺ type Source region 12 n ⁺ type drain region

Claims (2)

[Claims] 1. A step of forming a gate electrode after forming a gate oxide film on a semiconductor substrate, a step of ion-implanting a low impurity concentration to form n ⁻ type source / drain regions, and etching the gate oxide film. After that, a step of forming a polycrystalline silicon film so as to cover the gate electrode, a step of forming a silicon single crystal layer after the oxide film on the substrate is removed so as not to remain, and a CVD oxide film is formed. A method of manufacturing a semiconductor device comprising a step of forming a spacer by post-etching back and a step of ion-implanting a high impurity concentration to form an n ⁺ type source / drain region. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon single crystal layer has a film thickness of at least 1000 Å.