JPH0878403A - Semiconductor device and formation of element isolating region in semiconductor device - Google Patents

Abstract

PURPOSE: To prevent the generation of voids easily and surely to avoid a drop in element characteristics in the formation of an element isolating region in a semiconductor device. CONSTITUTION: A trench 3 is formed by etching, etc., a monocrystalline silicon substrate 2. Then, plasma CVD equipment is used to form an amorphous silicon layer 8. Next, the silicon substrate 2 in which an amorphous silicon layer 8 is formed is subjected to thermal oxidation to convert the amorphous silicon layer 8 to a silicon oxide film. Thereafter, the plasma CVD equipment is used to deposit a polycrystal silicon layer and an element isolating region is formed. Unlike a crystalline silicon, amorphous silicon has no definite crystal orientation. Depending on its part, no difference in the density of a silicon atom occurs. Consequently, the amorphous silicon layer 6 possesses an averaged atomic density at any part. Its speed when it is oxidized becomes constant, and the film thickness of the formed silicon oxide film becomes approximately uniform.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an element isolation region and a method for forming the element isolation region.

[0002]

2. Description of the Related Art Conventionally, for example, the following method has been generally adopted as a method of forming this type of element isolation region. That is, as shown in FIG. 12, first, a trench groove 52 having a rectangular cross section is formed by etching between elements of a silicon substrate 51 made of single crystal silicon. And
The silicon oxide film 53 is formed by directly thermally oxidizing the bottom wall surface and the side wall surface of the trench groove 52. Then
A polycrystalline silicon layer 54 is deposited on the silicon oxide film 53, and an element isolation region is formed in the trench groove 52.

The silicon substrate 51 thus formed with the element isolation region is subjected to a number of subsequent steps such as thermal oxidation and formation of a diffusion region to form an element or the like. Finally, a semiconductor device in which the elements are insulated from each other by the element isolation region is obtained.

However, in the above technique, the silicon oxide film 53 is formed by directly thermally oxidizing the bottom wall surface and the side wall surface made of single crystal silicon.
Therefore, there is a possibility that the film thickness of the silicon oxide film 53 may become uneven depending on the part. That is,
Since the silicon oxide film 53 at the boundary portion (corner portion) between the bottom wall and the side wall receives compressive stress during the growth of the film, the oxidation rate of that portion becomes lower than that of other portions. Further, the growth rate of the silicon oxide film 53 at the boundary portion is slower than that at other portions. for that reason,
There is a possibility that the film thickness of the silicon oxide film 53 at the boundary portion may be thinner than the film thickness at other portions. On the other hand, the film thickness of the polycrystalline silicon layer 54 formed thereafter is uniform.

Therefore, as described above, the silicon oxide film 5
When the film thickness of No. 3 was not uniform, voids 55 were sometimes formed corresponding to the thin portion of the film when the polycrystalline silicon layer 54 was deposited later. As a result, due to such voids 55, stress concentration may occur in the subsequent heat treatment step, which may cause crystal defects (strain). Further, when the semiconductor device is used, the element characteristics may be deteriorated, such as an increase in current leakage due to the crystal defects.

On the other hand, a technique disclosed in Japanese Patent Laid-Open No. 5-29541 is known as a technique for solving the above problems. In this technique, first, a trench groove having a rectangular cross section is formed. Then, after forming an oxide film by thermal oxidation, the oxide film is completely removed by etching. Then, the side walls and bottom wall of the trench groove are slightly curved. After that, the oxide film is formed again by the subsequent thermal oxidation. At this time, since there is no edge-shaped corner portion in the trench groove, it is difficult to form an extremely thin oxide film portion. Therefore, the voids described above are less likely to be formed.

[0007]

However, in the above-mentioned conventional technique, the trench groove having a rectangular cross section is once formed, oxidized, and then removed by etching. For this reason, the number of steps is remarkably increased, resulting in deterioration of workability and increase in cost.
Further, even if the above technique is adopted, it is not always possible to obtain a completely curved shape, and it is practically difficult to reliably prevent the occurrence of voids.

The present invention has been made in view of the above-mentioned circumstances, and an object thereof is to easily and surely prevent generation of voids when forming an element isolation region in a semiconductor device. Accordingly, it is an object of the present invention to provide a semiconductor device and a method for forming an element isolation region in a semiconductor device, which can avoid deterioration of element characteristics.

[0009]

In order to achieve the above object, in the invention according to claim 1, an amorphous silicon layer formed on a trench groove having a substantially rectangular cross section formed on a silicon substrate. An element isolation region formed by depositing a crystalline silicon layer on a silicon oxide film that is at least partially oxidized substantially uniformly, and a semiconductor element formed on both sides of the element isolation region. The gist is the semiconductor device provided.

According to the second aspect of the invention,
Forming a trench groove having a substantially rectangular cross section on a silicon substrate; forming an amorphous silicon layer in the trench groove; and oxidizing at least a portion of the amorphous silicon layer to form a silicon oxide film. The gist is a method of forming an element isolation region in a semiconductor device, which includes a step of forming and a step of depositing a crystalline silicon layer on the silicon oxide film to form an element isolation region in the trench groove.

[0011]

According to the above structure, first, the trench groove having a substantially rectangular cross section is formed on the silicon substrate. Next, an amorphous silicon layer is formed in the trench groove. Then, at least a part of this amorphous silicon layer is oxidized to form a silicon oxide film.

Here, amorphous silicon, unlike crystalline silicon, does not have a fixed crystal orientation.
That is, crystalline silicon has a diamond structure, whereas amorphous silicon has a structure that can be slightly deviated from the structure to an arbitrary position, so that there is no difference in the density of silicon atoms depending on the site. for that reason,
The amorphous silicon layer has an averaged atom density regardless of whether it is at the boundary between the side wall and the bottom wall of the trench groove or not. Therefore, when the amorphous silicon layer is oxidized, the oxidation rate becomes constant, and the film thickness of the formed silicon oxide film becomes almost uniform.

Thereafter, by depositing a crystalline silicon layer on the silicon oxide film, the trench groove is filled with the crystalline silicon layer to form an element isolation region. At this time, the crystalline silicon layer is formed with a uniform film thickness.
Therefore, since the silicon oxide film is formed to have a uniform film thickness, no void is formed in the finally formed element isolation region.

Further, in particular, according to the semiconductor device of the first aspect, since voids are not formed, the element characteristics do not deteriorate. Furthermore, when the amorphous silicon layer partially remains, even if there is thermal expansion of the crystalline silicon layer due to its own heat generation during use,
The stress generated at that time can be relieved by the buffer function of the amorphous silicon layer.

[0015]

【Example】

(First Embodiment) A first embodiment embodying a method for forming an element isolation region in a semiconductor device according to the present invention will be described below with reference to FIGS.

FIG. 2 is a sectional view showing the element isolation region 1 of the semiconductor device in this embodiment. In the figure, on the left and right sides of the element isolation region 1, for example, transistor elements (not shown) are formed by going through the steps after the formation of the area 1. A trench groove 3 having a substantially rectangular cross section is formed between the elements of the single crystal silicon substrate 2. The silicon substrate 2 has, for example, a <111> crystal orientation. The width of the trench groove 3 is, for example, “2 μm”, and the depth thereof is “15 μm”.

A silicon oxide film 4 is formed in the trench groove 3. Further, a polycrystalline silicon layer 5 as a crystalline silicon layer is formed on the silicon oxide film 4, and the trench groove 3 is filled with the polycrystalline silicon layer 5. The polycrystalline silicon layer 5 constitutes the element isolation region 1.

Next, the method for forming the element isolation region 1 in this embodiment will be described in detail. First, as shown in FIG. 3, the silicon substrate 2 is placed in an oxygen atmosphere at 1100 ° C.
By performing the high temperature treatment of the above, the protective silicon oxide film 6 is formed on the silicon substrate 2 (film thickness “950 n
m ”). Next, as shown in FIG. 4, by using photolithography, a novolac-based resist pattern 7 having an opening (opening width “2 μm”) only at a portion corresponding to the trench groove 3 is formed.

Then, an opening 6 is formed in the protective silicon oxide film 6 by using an RIE type plasma etching apparatus.
a is formed. Then, as shown in FIG. 5, the resist pattern 7 is removed using a hydrogen peroxide solution and a sulfuric acid solution.

Next, anisotropic etching is performed using a magnetically excited plasma etching apparatus, and as shown in FIG.
The trench groove 3 is formed. The gas used at this time is SF ₆ , HBr, He, O ₂ , for example, RF power is 500 W, excitation magnetic force is 65 G, and chamber pressure is 15 P.
a. In such a case, the etching rate of single crystal silicon is, for example, 600 nm / min. After that, as shown in FIG. 7, the protective silicon oxide film 6 is removed with a hydrofluoric acid solution or the like.

Then, using a plasma CVD apparatus, as shown in FIG. 1, an amorphous silicon layer 8 is deposited and formed to have a film thickness of 100 nm. The processing conditions at this time are, for example, a substrate temperature of 350 ° C., a SiH ₄ gas or Si ₂ H ₆ gas flow rate of 100 sccm, and a processing pressure of 20 P.
and RF power is 300W. At this time, the optical CV
A similar amorphous silicon layer 8 can be obtained by using D.

Next, a step of oxidizing the amorphous silicon layer 8 is provided. That is, the silicon substrate 2 on which the amorphous silicon layer 8 is formed is subjected to a high temperature treatment of 850 ° C. in an oxygen atmosphere. From this thermal oxidation
As shown in FIG. 8, the amorphous silicon layer 8 is transformed into the silicon oxide film 4. The above temperature is 850 ° C.
The temperature is not limited to, for example, about 800 ° C to 110 ° C.
The same effect as above can be obtained in the range of about 0 ° C.

After that, a plasma CVD apparatus or a reduced pressure CV is used.
A polycrystalline silicon layer 5 as a crystalline silicon layer is deposited using a D device. In this way, the element isolation region 1 is formed.

As described above, in this embodiment, the silicon oxide film 4 is formed by oxidizing the amorphous silicon layer 8. Here, amorphous silicon, unlike crystalline silicon, does not have a fixed crystal orientation. That is, as shown in FIG. 9, crystalline silicon atoms have a diamond structure, whereas in amorphous silicon, silicon atoms Si have a structure that can be slightly deviated from the diamond structure to an arbitrary position. There is no difference in the density of atomic Si. Therefore, the amorphous silicon layer 8
1 has an averaged atom density regardless of whether it is a boundary portion between the side wall and the bottom wall of the trench groove 3 or not, as shown in FIG. Therefore, when the amorphous silicon layer 8 is oxidized, the oxidation rate becomes constant, and the film thickness of the silicon oxide film 4 formed is substantially uniform. Further, the polycrystalline silicon layer 5 formed thereafter is also formed with a uniform film thickness.

Therefore, as shown in FIG. 2, no void is formed in the finally formed element isolation region 1. As a result, according to the present embodiment, it is possible to easily and surely prevent the generation of voids, and thus it is possible to reliably prevent deterioration of element characteristics due to the generation of voids.

(Second Embodiment) Next, a second embodiment of a semiconductor device having an element isolation region according to the present invention will be described with reference to FIG.

FIG. 10 is a view showing a concrete example of a semiconductor device in which a bipolar transistor is formed as a semiconductor element in this embodiment. In the figure, element isolation regions 11 almost similar to those described in the first embodiment are formed at a plurality of locations. However, the structure is slightly different from that of the first embodiment in that a high-density P ⁺ region 12 is formed below the trench groove 3. This P ⁺ region 12 is for preventing current leakage.

Further, the activity defined by the element isolation region 11
In the region, a bipolar transistor 13 as an element,
14 is formed. That is, on the silicon substrate 2
Is P from the bottom^-Area 15, N⁺Area 16, N^-
Area 17, P⁺Region 18 and N ⁺Area 19 is formed by diffusion
Have been. Further, an insulating film 20 is formed on the
The base electrode 21 and the emitter at predetermined locations.
An electrode 22 and a collector electrode 23 are formed respectively
It

Next, a method of manufacturing the semiconductor device having the above structure will be described. First, P ^{− of the} silicon substrate 2
N ⁺ region 16 epitaxially grown on region 15 is formed in advance. Then, the element isolation region 11 is formed by the process described in the first embodiment. However, in this embodiment, the protective silicon oxide film 6 on the upper surface (see FIGS.
The amorphous silicon layer 8 is formed in a state where a small amount (see FIG. 3) is left, and the amorphous silicon layer 8 is oxidized to form the silicon oxide film 4. Then, the silicon oxide film 4 is formed on the protective silicon oxide film 6 on the upper surface of the silicon substrate 2, and the film thickness of the oxide films 4 and 6 on the upper surface is increased. After the above oxidation, dry etching (RI) is performed.
Anisotropic etching is performed. Then, the silicon oxide film 4 is etched on the upper surface, and the protective silicon oxide film 6 is exposed again. Further, the side wall portion is not etched. Further, the silicon oxide film 4 formed at the bottom of the trench groove 3 is etched, and the silicon substrate 1 is exposed.

Then, implant boron (implantatio
n) together with P ⁺ region 12
To form. After that, the polycrystalline silicon layer 5 is formed as in the first embodiment. With such a structure, the element isolation region 11 in which no void is generated is formed, and the P ⁺ region 12 is formed below the trench groove 3.

Then, in the subsequent steps, N ⁻ region 1
7. P ⁺ region 18 and N ⁺ region 19 are diffused and formed. After that, the insulating film 20 is formed, and the electrodes 21 to 23 are formed by photoetching, whereby the semiconductor device as shown in FIG. 10 is manufactured.

As described above, in this embodiment, a concrete example of the semiconductor device in which the bipolar transistors 13 and 14 are formed as the elements is shown. Also in this embodiment, it is possible to prevent the formation of voids when forming the element isolation region 11. Therefore, the deterioration of the characteristics of the bipolar transistors 13 and 14 formed thereafter is not impaired. More specifically, it is possible to suppress an increase in leakage current, and in turn prevent a decrease in the current amplification factor h _FE .

Further, in this embodiment, the P ⁺ region 12 is formed below the trench groove 3. Therefore, leakage of current can be surely cut off, and further deterioration of element characteristics can be prevented.

The present invention is not limited to the above embodiments,
For example, it may be configured as follows. (1) In the above-described embodiment, the amorphous silicon layer 8 is almost entirely oxidized to form the silicon oxide film 4. However, as shown in FIG. 11, a part of the amorphous silicon layer 8 is oxidized to silicon oxide. The film 4 may be formed so that a part of the amorphous silicon layer 8 is left. The above structure is obtained by oxidizing the surface layer surface of the amorphous silicon layer 8 by adjusting the temperature and the time. The amorphous silicon layer 8 thus left without being oxidized has a smaller coefficient of thermal expansion than the polycrystalline silicon layer 5. Therefore, the amorphous silicon layer 8 can relieve the stress caused by the thermal expansion of the polycrystalline silicon layer 5 embedded in the trench groove 3 (due to the operating environment temperature and its own heat generated during use).

(2) In the second embodiment, a specific example of the semiconductor device in which the bipolar transistors 13 and 14 are formed as elements is shown. However, it is embodied in the semiconductor device in which the CMOS transistors are formed as elements. Good. In such a case, it is possible to suppress a decrease in electron mobility and prevent a decrease in operating speed of the element.

The fine structure of the element is not limited to that of the second embodiment. (3) In the above embodiment, the polycrystalline silicon layer 5 is formed as the crystalline silicon layer, but the crystalline silicon layer is meant to include a polycrystalline silicon layer and a single crystal silicon layer, and can be implemented. If present, it may be embodied when forming a single crystal silicon layer.

(4) The width and depth of the trench groove and the thickness and characteristic values of each layer and film in the above embodiment are not limited to the above numerical values, and can be changed appropriately according to the application field. is there.

The technical idea which is not stated in the claims of the present invention and which can be understood from the above-mentioned embodiment will be described below together with its effect. (A) In the semiconductor device according to claim 2, a junction isolation region is provided at the bottom of the trench groove. With such a configuration, leakage of current can be cut off, and deterioration of element characteristics can be further prevented.

[0039]

As described in detail above, according to the present invention,
When forming the element isolation region in the semiconductor device, there is an excellent effect that the generation of voids can be easily and surely prevented.

Further, according to the semiconductor device of the present invention, there is an excellent effect that it is possible to avoid the deterioration of the element characteristics due to the generation of voids. Furthermore, when a part of the amorphous silicon layer remains, the stress due to thermal expansion is
The buffering function of the amorphous silicon layer is alleviated, and there is an excellent effect that it is possible to reliably prevent deterioration of element characteristics.

[Brief description of drawings]

FIG. 1 is a diagram showing a step in forming an element isolation region of a semiconductor device according to a first embodiment of the present invention, which is a partial cross-sectional view showing a state in which an amorphous silicon layer is formed in a trench groove.

FIG. 2 is a partial cross-sectional view showing an element isolation region of a semiconductor device in the first embodiment.

FIG. 3 is a partial cross-sectional view showing a state in which a protective silicon oxide film is formed on a silicon substrate in the first embodiment.

FIG. 4 is a partial cross-sectional view showing a state in which a resist pattern is formed on a protective silicon oxide film in the first embodiment.

FIG. 5 is a partial cross-sectional view showing a state in which the resist pattern is removed and an opening is formed in the protective silicon oxide film in the first embodiment.

FIG. 6 is a partial cross-sectional view showing a state where a trench groove is formed in the first embodiment.

FIG. 7 is a partial cross-sectional view showing a state in which a protective silicon oxide film is removed in the first embodiment.

FIG. 8 is a partial cross-sectional view showing a state in which the amorphous silicon layer is transformed into a silicon oxide film by thermal oxidation in the first embodiment.

FIG. 9 is a perspective view schematically showing a bonding structure of amorphous silicon atoms in the first example.

FIG. 10 is a partial cross-sectional view schematically showing a semiconductor device according to a second embodiment of the present invention.

FIG. 11 illustrates another embodiment embodying the invention,
It is a figure which shows one process at the time of forming the element isolation region of a semiconductor device, Comprising: It is a partial cross section figure which shows the state which oxidized a part of amorphous silicon layer.

FIG. 12 is an enlarged cross-sectional view showing an element isolation region of a conventional semiconductor device.

[Explanation of symbols]

1, 11 ... Element isolation region, 2 ... Silicon substrate, 3 ... Trench groove, 4 ... Silicon oxide film, 5 ... Polycrystalline silicon layer as crystalline silicon layer, 8 ... Amorphous silicon layer.

Claims (2)

[Claims] 1. A crystalline silicon layer is formed on a silicon oxide film obtained by substantially uniformly oxidizing at least a part of an amorphous silicon layer formed in a trench groove having a substantially rectangular cross section formed on a silicon substrate. A semiconductor device comprising: an element isolation region formed by being deposited; and semiconductor elements formed on both sides of the element isolation region. 2. A step of forming a trench groove having a substantially rectangular cross section on a silicon substrate, a step of forming an amorphous silicon layer in the trench groove, and a step of oxidizing at least a part of the amorphous silicon layer substantially uniformly. An element isolation region in a semiconductor device, comprising: a step of forming a silicon oxide film by a step of depositing a crystalline silicon layer on the silicon oxide film to form an element isolation region in the trench groove. Forming method.