JP2763216B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2763216B2
JP2763216B2 JP3287804A JP28780491A JP2763216B2 JP 2763216 B2 JP2763216 B2 JP 2763216B2 JP 3287804 A JP3287804 A JP 3287804A JP 28780491 A JP28780491 A JP 28780491A JP 2763216 B2 JP2763216 B2 JP 2763216B2
Authority
JP
Japan
Prior art keywords
oxide film
heat treatment
film
semiconductor substrate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3287804A
Other languages
Japanese (ja)
Other versions
JPH05129328A (en
Inventor
あきつ 鮎川
茂夫 大西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Consejo Superior de Investigaciones Cientificas CSIC
Original Assignee
Consejo Superior de Investigaciones Cientificas CSIC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Consejo Superior de Investigaciones Cientificas CSIC filed Critical Consejo Superior de Investigaciones Cientificas CSIC
Priority to JP3287804A priority Critical patent/JP2763216B2/en
Priority to US07/932,943 priority patent/US5348900A/en
Publication of JPH05129328A publication Critical patent/JPH05129328A/en
Application granted granted Critical
Publication of JP2763216B2 publication Critical patent/JP2763216B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、より詳細にはLDD(Lightly Doped Drain) 構造
を有するMOS型半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOS type semiconductor device having an LDD (Lightly Doped Drain) structure.

【0002】[0002]

【従来の技術】従来のLDD構造を有するMOS型メモ
リセルの製造方法を図面に基づいて説明する。まず、図
2(a)に示したように、P型のシリコン基板(11)
上に活性領域及びフィールド酸化膜からなる素子分離領
域を形成することによって、素子形成領域を確保した
後、ゲート酸化膜としてSiO2 膜(12)が形成され
た素子形成領域上に3500〜4000Åの厚さのポリ
シリコンからなるゲート電極(13)を形成し、CVD
法でSiO2 膜を2500〜3500Åの厚さで堆積さ
せ、ゲート電極(13)にSiO2からなるサイドウォ
ール(14)を反応性イオンエッチング(RIE)法及
びHFウェットエッチング法によって形成するととも
に、シリコン基板(11)上に約100〜400ÅのS
iO2 膜(16)を形成する。
2. Description of the Related Art A conventional method for manufacturing a MOS memory cell having an LDD structure will be described with reference to the drawings. First, as shown in FIG. 2A, a P-type silicon substrate (11)
After forming an element isolation region including an active region and a field oxide film thereon, an element formation region is secured. Then, the device isolation region having a SiO 2 film (12) as a gate oxide film has a thickness of 3500 to 4000 °. A gate electrode (13) made of polysilicon having a thickness is formed, and CVD is performed.
A SiO 2 film is deposited to a thickness of 2500 to 3500 ° by a method, and a sidewall (14) made of SiO 2 is formed on the gate electrode (13) by a reactive ion etching (RIE) method and an HF wet etching method. About 100-400 ° S on a silicon substrate (11)
An iO 2 film (16) is formed.

【0003】次いで、ゲート電極(13)をマスクとし
てソース/ドレイン領域(17)となる領域にSiO2
膜(16)を介してAs等のN型不純物イオン(15)
の注入を行う。そして、ソース/ドレイン領域(17)
の不純物を拡散させるため、例えば、800℃の温度で
1時間の第1の熱処理を行う。その後、図2(b)示し
たように、ソース/ドレイン領域(17)の外方拡散を
抑制するためにSiO2 膜(16)上にNSG膜(1
9)を堆積し、その上にNSG膜(19)上の層間段差
を少なくするためにBPSG膜(20)を堆積して、例
えば950℃で30分間の第2の熱処理を行い、ソース
/ドレイン領域(17)を形成する。
Next, using the gate electrode (13) as a mask, SiO 2 is formed in a region to be a source / drain region (17).
N-type impurity ions (15) such as As via the film (16)
Is performed. And a source / drain region (17)
Is performed, for example, at a temperature of 800 ° C. for one hour. Thereafter, as shown in FIG. 2B, an NSG film (1) is formed on the SiO 2 film (16) in order to suppress out-diffusion of the source / drain region (17).
9), a BPSG film (20) is deposited thereon in order to reduce an interlayer step on the NSG film (19), and a second heat treatment is performed at 950 ° C. for 30 minutes, for example. An area (17) is formed.

【0004】[0004]

【発明が解決しようとする課題】微細MOS型トランジ
スタの諸特性の変動をもたらす原因の一つとして、ソー
ス/ドレイン領域の結晶欠陥の存在があげられるが、上
記の半導体装置の製造方法においては、イオン注入がS
iO2 膜(16)を通して行われるので、酸素がイオン
とともにシリコン基板(1)に打ち込まれ、シリコン基
板(1)内で不純物イオンが酸素と結合し、結晶欠陥
(18)を発生させるという問題があった。
One of the causes of variations in the characteristics of the fine MOS transistor is the presence of crystal defects in the source / drain regions. However, in the above method of manufacturing a semiconductor device, Ion implantation is S
Since the process is performed through the iO 2 film (16), oxygen is implanted into the silicon substrate (1) together with ions, and impurity ions combine with oxygen in the silicon substrate (1) to generate crystal defects (18). there were.

【0005】また、この結晶欠陥(18)はその後の熱
処理でも消失せず、半導体装置の電気的リークの原因と
なり、歩留り低下の原因となるという問題があった。さ
らに、イオン注入後の高温熱処理によって、接合深さ
(Xj)が長くなり、微細化という点において不適当で
あるという問題があった。本発明はこのような問題を鑑
みなされたものであり、結晶欠陥を発生させることな
く、微細化に適した半導体装置の製造方法を提供するこ
とを目的としている。
Further, there is a problem that the crystal defect (18) does not disappear even in the subsequent heat treatment, causes electrical leakage of the semiconductor device, and lowers the yield. Furthermore, there is a problem that the junction depth (Xj) becomes longer due to the high-temperature heat treatment after the ion implantation, which is inappropriate in terms of miniaturization. The present invention has been made in view of such a problem, and has as its object to provide a method for manufacturing a semiconductor device suitable for miniaturization without generating crystal defects.

【0006】[0006]

【課題を解決するための手段】この発明によれば、半導
体基板上に形成されたゲート電極上に酸化膜を積層し、
該酸化膜をエッチングして、前記ゲート電極側壁にサイ
ドウォールを形成するとともに、前記半導体基板表面が
露出しないように前記酸化膜を残す工程、前記半導体基
板のソース/ドレイン領域となる部分に、前記酸化膜を
介して不純物をイオン注入して第1の熱処理を行う工
程、前記半導体基板上の前記酸化膜を除去した後、酸素
雰囲気にて第2の熱処理を行う工程を含む半導体装置の
製造方法が提供される。
According to the present invention, an oxide film is laminated on a gate electrode formed on a semiconductor substrate,
Etching the oxide film to form sidewalls on the side walls of the gate electrode and leaving the oxide film so that the surface of the semiconductor substrate is not exposed; A method of manufacturing a semiconductor device, comprising: a step of performing a first heat treatment by ion-implanting impurities through an oxide film; and a step of performing a second heat treatment in an oxygen atmosphere after removing the oxide film on the semiconductor substrate. Is provided.

【0007】本発明においては、半導体基板(例えば、
シリコン基板)に予めゲート酸化膜(例えばSiO
2 膜)を介して、サイドウォールが形成されてゲート電
極が形成されている。そして、この半導体基板は、上記
のゲート電極の部分を含む全面に100〜400Å程度
の酸化膜(例えばSiO2 膜)が形成される。この酸化
膜を介して半導体基板のソース/ドレイン領域となる部
分に不純物であるAs、P等のイオン注入が、公知の方
法によって行われる。
In the present invention, a semiconductor substrate (for example,
A gate oxide film (eg, SiO 2) is previously formed on a silicon substrate.
2 ), a sidewall is formed and a gate electrode is formed. Then, an oxide film (for example, SiO 2 film) of about 100 to 400 ° is formed on the entire surface of the semiconductor substrate including the gate electrode. Ion implantation of impurities such as As and P into a portion serving as a source / drain region of the semiconductor substrate via the oxide film is performed by a known method.

【0008】その後、本発明ではこの不純物をソース/
ドレイン領域に拡散させるために、第1の熱処理が行わ
れる。この第1の熱処理は約750〜850℃の温度範
囲で、30〜60分間程度行うことによって達すること
ができる。そして、半導体基板の酸化膜を公知の方法に
よって除去したのち、酸素雰囲気にて第2の熱処理を行
う。この場合の酸素雰囲気中での第2の熱処理とは、約
30〜40リットル/minの流量で酸素ガスを流入し
た雰囲気にて、約800〜900℃、10〜30分間行
うことによって、欠陥のない不純物拡散領域を形成する
ことができる。
Thereafter, in the present invention, this impurity is
A first heat treatment is performed to diffuse into the drain region. This first heat treatment can be achieved by performing the first heat treatment in a temperature range of about 750 to 850 ° C. for about 30 to 60 minutes. Then, after removing the oxide film of the semiconductor substrate by a known method, a second heat treatment is performed in an oxygen atmosphere. In this case, the second heat treatment in an oxygen atmosphere is performed at about 800 to 900 ° C. for 10 to 30 minutes in an atmosphere in which oxygen gas flows at a flow rate of about 30 to 40 liters / min. No impurity diffusion region can be formed.

【0009】[0009]

【作用】上記した方法によれば、半導体基板内で不純物
イオンと酸素との結合により生じる結晶欠陥が、酸素雰
囲気にて熱処理を行うことにより解消される。つまり、
酸素雰囲気での熱処理により、半導体基板内の不純物イ
オンと酸素との結合が切断され、欠陥のない不純物拡散
領域が形成されることとなる。また、イオン注入後に行
う熱処理の温度を低く、短時間に設定しても、欠陥が解
消されるとともに、不純物イオンの拡散を抑制して接合
深さの浅い不純物拡散領域が形成されることとなる。
According to the above-described method, crystal defects caused by a bond between impurity ions and oxygen in a semiconductor substrate are eliminated by performing a heat treatment in an oxygen atmosphere. That is,
By the heat treatment in the oxygen atmosphere, the bond between the impurity ion and oxygen in the semiconductor substrate is cut, so that a defect-free impurity diffusion region is formed. Further, even if the temperature of the heat treatment performed after the ion implantation is set to a low temperature for a short time, the defect is eliminated, and the diffusion of the impurity ions is suppressed to form an impurity diffusion region having a shallow junction depth. .

【0010】[0010]

【実施例】本発明に係る半導体装置の製造方法の実施例
を図面に基づいて説明する。まず、シリコン基板(1)
上に活性領域及びフィールド酸化膜からなる素子分離領
域を形成することによって、素子形成領域を確保し、ゲ
ート酸化膜としてSiO2 膜(2)を積層したのち、こ
の素子形成領域上に3500〜4000Åの厚さのポリ
シリコンからなるゲート電極(3)を形成する。そし
て、シリコン基板(1)及びゲート電極(3)上にCV
D法でSiO2 膜を2500〜3500Åの厚さで堆積
させ、ゲート電極(3)にSiO2からなるサイドウォ
ール(4)を反応性イオンエッチング(RIE)法及び
HFウェットエッチング法によって形成する。この際、
シリコン基板(1)上に積層されたSiO2 膜は約40
0Åの厚さで残しておく。次いで、このSiO2 膜を介
してAs等の不純物イオン(7)を80KeV、5×1
15ions/cm2 で注入する。そして、例えば約8
00℃で、約1時間第1の熱処理を行う(図1
(a))。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. First, silicon substrate (1)
An element formation region consisting of an active region and a field oxide film is formed thereon to secure an element formation region, and an SiO 2 film (2) is laminated as a gate oxide film. A gate electrode (3) made of polysilicon having a thickness of 3 nm is formed. Then, CV is formed on the silicon substrate (1) and the gate electrode (3).
A SiO 2 film is deposited to a thickness of 2500 to 3500 ° by Method D, and a sidewall (4) made of SiO 2 is formed on the gate electrode (3) by a reactive ion etching (RIE) method and an HF wet etching method. On this occasion,
The SiO 2 film laminated on the silicon substrate (1) is about 40
Leave at 0mm thickness. Then, impurity ions (7) such as As are supplied at 80 KeV and 5 × 1 through the SiO 2 film.
Inject at 0 15 ions / cm 2 . And, for example, about 8
A first heat treatment is performed at 00 ° C. for about 1 hour (FIG. 1)
(A)).

【0011】その後、ゲート電極(3)およびシリコン
基板(1)上のSiO2 膜を除去し、酸素雰囲気にて、
例えば、900℃で10分間程度、熱処理を行う。
After that, the SiO 2 film on the gate electrode (3) and the silicon substrate (1) is removed, and in an oxygen atmosphere,
For example, heat treatment is performed at 900 ° C. for about 10 minutes.

【0012】[0012]

【発明の効果】本発明に係る半導体装置の製造方法によ
れば、半導体基板内で不純物イオンと酸素との結合によ
り生じる結晶欠陥が、酸素雰囲気にて熱処理を行うこと
により解消することができる。つまり、酸素雰囲気での
熱処理により、半導体基板内の不純物イオンと酸素との
結合を切断して、欠陥のない不純物拡散領域を形成する
ことができる。また、イオン注入後に行う熱処理の温度
を低く、短時間に設定しても、欠陥を解消することがで
きるとともに、不純物イオンの拡散を抑制して接合深さ
の浅い不純物拡散領域を形成することができる。
According to the method of manufacturing a semiconductor device according to the present invention, crystal defects caused by bonding of impurity ions and oxygen in a semiconductor substrate can be eliminated by performing a heat treatment in an oxygen atmosphere. That is, by the heat treatment in the oxygen atmosphere, the bond between the impurity ions and oxygen in the semiconductor substrate is cut, so that a defect-free impurity diffusion region can be formed. In addition, even if the temperature of the heat treatment performed after the ion implantation is set to be low and set for a short time, defects can be eliminated, and diffusion of impurity ions can be suppressed to form an impurity diffusion region having a shallow junction depth. it can.

【0013】従って、欠陥のない不純物拡散領域を形成
することにより、リーク電流を低下させることが可能と
なるとともに、微細な半導体装置を歩留り良く製造する
ことが実現可能となる。
Therefore, by forming the impurity diffusion region having no defect, it is possible to reduce the leak current and to realize the manufacture of a fine semiconductor device with high yield.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係わる半導体装置の製造方法の実施例
を示す製造工程説明図である。
FIG. 1 is an explanatory view of a manufacturing process showing an embodiment of a method of manufacturing a semiconductor device according to the present invention.

【図2】従来の半導体装置の製造方法を示す概略断面図
である。
FIG. 2 is a schematic sectional view showing a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 シリコン基板(半導体基板) 2 SiO2 膜(ゲート酸化膜) 3 ゲート電極 4 サイドウォール 5 不純物イオン 6 SiO2 膜(酸化膜) 7 ソース/ドレイン領域Reference Signs List 1 silicon substrate (semiconductor substrate) 2 SiO 2 film (gate oxide film) 3 gate electrode 4 sidewall 5 impurity ion 6 SiO 2 film (oxide film) 7 source / drain region

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体基板上に形成されたゲート電極上
に酸化膜を積層し、該酸化膜をエッチングして、前記ゲ
ート電極側壁にサイドウォールを形成するとともに、前
記半導体基板表面が露出しないように前記酸化膜を残す
工程、前記半導体基板のソース/ドレイン領域となる部
分に、前記酸化膜を介して不純物をイオン注入して第1
の熱処理を行う工程、前記半導体基板上の前記酸化膜を
除去した後、酸素雰囲気にて第2の熱処理を行う工程を
含むことを特徴とする半導体装置の製造方法。
An oxide film is laminated on a gate electrode formed on a semiconductor substrate, and the oxide film is etched to form a sidewall on a side wall of the gate electrode and to prevent a surface of the semiconductor substrate from being exposed. Leaving the oxide film on the substrate, and ion-implanting impurities through the oxide film into a portion to be a source / drain region of the semiconductor substrate.
And a second heat treatment in an oxygen atmosphere after removing the oxide film on the semiconductor substrate.
JP3287804A 1991-10-11 1991-11-01 Method for manufacturing semiconductor device Expired - Fee Related JP2763216B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP3287804A JP2763216B2 (en) 1991-11-01 1991-11-01 Method for manufacturing semiconductor device
US07/932,943 US5348900A (en) 1991-10-11 1992-08-21 Process for manufacturing a semiconductor device including heat treatment in ammonia or oxygen

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3287804A JP2763216B2 (en) 1991-11-01 1991-11-01 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH05129328A JPH05129328A (en) 1993-05-25
JP2763216B2 true JP2763216B2 (en) 1998-06-11

Family

ID=17721968

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3287804A Expired - Fee Related JP2763216B2 (en) 1991-10-11 1991-11-01 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2763216B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0621629A3 (en) * 1993-04-20 1996-07-17 Texas Instruments Inc Method for reducing dislocations in integrated circuit devices.

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01309375A (en) * 1988-06-08 1989-12-13 Toshiba Corp Manufacture of mos type semiconductor device

Also Published As

Publication number Publication date
JPH05129328A (en) 1993-05-25

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