JP2774019B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. More specifically, the source with few crystal defects
The present invention relates to a method for manufacturing a semiconductor device including forming a MOS transistor with a drain. Particularly, it is used for manufacturing a MOS type memory device.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional semiconductor device is composed of a) SiO ₂ formed on a silicon substrate 11 on which a gate electrode 13 is formed via a gate oxide film 12 by CVD.
By processing the film using RIE and HF aqueous solution, SiO ₂ side walls are formed on both sides of the gate electrode, and a film thickness of about 100 to 400 is formed in a region where a source / drain is formed.
(B) a step of leaving an SiO ₂ film; b) a step of implanting As ions into a region where a source / drain is to be formed and heat-treating at 800 ° C. for about 1 hour to diffuse As;
An NSG (non-doped silicate glass) film is deposited thereon in order to prevent As in a region where a drain is formed from diffusing out of the substrate, and a BPSG film is further deposited to reduce a step of the NSG film. Forming a source / drain in the diffusion region by heat treatment at 950 ° C. for 30 minutes; and d) forming a contact hole in a predetermined region of the BPSG film and the NSG film, burying a tungsten layer, and forming a wiring layer thereon. It is manufactured.

[0003]

In the above-described conventional method for manufacturing a semiconductor device, oxygen in the SiO ₂ film is implanted into the silicon substrate together with the ions during ion implantation, so that a crystal defect occurs in the silicon substrate (source / drain region). Occurs
Since this defect does not disappear even in the subsequent heat treatment, it causes an electric leak of the semiconductor device, and there is a problem that the manufacturing yield is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and it is an object of the present invention to provide a method of manufacturing a semiconductor device which has no crystal defects in its source and drain, has low electric leakage, and has a high manufacturing yield. It is assumed that.

[0005]

According to the present invention, a)
An SiO ₂ film is stacked on a silicon substrate on which a gate electrode is formed via a gate oxide film, and a silicon substrate in a region where a side wall adjacent to the gate electrode is formed and a source / drain is formed by performing etch back B) laminating a polysilicon layer over the entire surface and injecting impurities into regions where the polysilicon layer and the source / drain are to be formed, and c) placing the substrate in a nitrogen-based gas atmosphere. Heating; and d) removing the SiN layer on the polysilicon layer formed by the heating and then etching the polysilicon layer into a predetermined pattern;
e) laminating an interlayer insulating film over the entire surface, opening a contact hole reaching the polysilicon layer, burying a wiring material in the contact hole, and forming a wiring layer thereon. Provided.

According to the present invention, a) forming a silicon oxide film on a silicon substrate on which a gate electrode is formed via a gate oxide film;
By stacking an O ₂ film and performing etch back, a sidewall adjacent to the gate electrode is formed, and a silicon substrate of a region where a source / drain is to be formed is exposed. The SiO ₂ film is usually formed by a CVD method.

A known method can be used for the etch back, and examples thereof include a RIE method and a method combining the RIE method and the HF solution processing method. The side wall is for forming an LDD (ligutly doped drain), and is formed by the etch back. The exposure of the silicon substrate is for electrically connecting the polysilicon layer laminated thereon to the source / drain in the silicon substrate.

In the present invention, b) a polysilicon layer is laminated on the entire surface, and the polysilicon layer and the source
Impurities are implanted and diffused into a region where a drain is formed. When the polysilicon layer is irradiated with impurity ions from above to implant ions into the polysilicon layer and the silicon substrate, the polysilicon layer protects the silicon substrate so that contaminants are not introduced into a region where a source / drain is formed. The purpose is to eliminate crystal defects in the source / drain regions caused by ion implantation.
The layers are laminated so as to have a thickness of 100 to 400 °.

The above-mentioned impurities are used to make the region for forming the source / drain and the polysilicon layer thereover conductive. To make the region n-type conductive, P and A are usually used.
When s or Sb is used and p-type conductivity is used, B, BF ₂ or In is usually used. Due to the implantation of the impurities, crystal defects occur in the region where the source / drain is formed and the polysilicon layer.

In the present invention, c) the substrate is heated in a nitrogen-based gas atmosphere. The nitrogen-based gas is used for nitriding the upper portion of the polysilicon layer to convert it into a SiN film, and for example, NH ₃ gas or the like can be used. The heating is for promoting this nitriding. By this nitridation, Si atoms in the polysilicon layer and the silicon substrate move in the direction of the SiN layer, and crystal defects at the source and drain are eliminated.

In the present invention, d) the polysilicon layer is etched into a predetermined pattern after removing the SiN layer on the polysilicon layer formed by the heating. S
The removal of iN can be performed by a known method.
The predetermined pattern is formed leaving a polysilicon layer in a region where a contact is formed so as to electrically connect the source / drain and a wiring layer formed in a later step.

In the present invention, e) an interlayer insulating film is laminated on the entire surface, a contact hole reaching the polysilicon layer is opened, a wiring material is buried in the contact hole, and a wiring layer is formed thereon to form a semiconductor device. Is manufactured. As the wiring material, for example, tungsten or the like is used.

[0013]

The vacancy is generated in the crystal structure of the nitrided region (SiN layer) by nitriding the upper portion of the polysilicon layer under heating,
Si atoms in the polysilicon layer and the source / drain regions move to the vacancies, and crystal defects in the polysilicon layer and the source / drain regions are eliminated.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A gate electrode 3 is formed on a silicon substrate 1 via a gate oxide film 2 by a conventional method, and an NSG layer (non-doped silicate glass) is formed thereon to reduce a step of the gate electrode. Further, S is deposited thereon by CVD.
An iO ₂ film is laminated and etched by RIE and hydrofluoric acid solution treatment so as to leave the gate electrode and the side surface of the gate electrode. By this etching, the side wall 5 of the gate electrode is formed, and a predetermined surface of the silicon substrate is exposed.

Next, a polysilicon layer 4 having a thickness of 300.degree. Is laminated thereon, and 80 KeV
Is implanted into the source / drain so that the As ion has a concentration of 3 × 10 ¹⁵ ions / cm ² . Next, the substrate is heated in an NH ₃ gas atmosphere to nitride the polysilicon layer and eliminate crystal defects at the source and drain.

Thereafter, the SiN formed by the above nitridation is formed.
The film 6 is removed, the polysilicon layer is etched leaving an MR contact region, an interlayer insulating film 7 is formed, a contact hole is opened, conduction is established with the tungsten layer 8 of the selective W method, and etch back is performed. To form In this wiring formation, even with a contact having a high aspect ratio, a contact having good characteristics and an MR wiring can be formed by the barrier of the polysilicon layer and the tungsten layer 8.

[0017]

According to the present invention, contamination during impurity implantation is suppressed, there is no crystal defect in the source / drain regions, the leak current is low, the yield is improved, and the characteristics are high even in a contact having a high aspect ratio. It is possible to provide a method of manufacturing the device.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a manufacturing process of a semiconductor device manufactured according to an embodiment of the present invention.

FIG. 2 is an explanatory view of a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Gate oxide film 3 Gate electrode 4 Polysilicon layer 5 Side wall 6 SiN film 7 Interlayer insulating film 8 Tungsten layer 9 MR wiring

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/768

Claims (1)

(57) [Claims] 1. a) A SiO ₂ film is stacked on a silicon substrate on which a gate electrode is formed via a gate oxide film, and a sidewall adjacent to the gate electrode is formed by performing an etch back, and a source / drain is formed. Exposing a silicon substrate in a region where a is to be formed; b) laminating a polysilicon layer over the entire surface and implanting impurities from above onto a region where a polysilicon layer and a source / drain are to be formed; Heating in a nitrogen-based gas atmosphere, d) removing the SiN layer on the polysilicon layer formed by the heating, and then etching the polysilicon layer into a predetermined pattern; e) an interlayer insulating film on the entire surface Forming a contact hole reaching the polysilicon layer, burying a wiring material in the contact hole, and forming a wiring layer thereon. Method of manufacturing a conductor arrangement.