JP2716300B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2716300B2
JP2716300B2 JP26402091A JP26402091A JP2716300B2 JP 2716300 B2 JP2716300 B2 JP 2716300B2 JP 26402091 A JP26402091 A JP 26402091A JP 26402091 A JP26402091 A JP 26402091A JP 2716300 B2 JP2716300 B2 JP 2716300B2
Authority
JP
Japan
Prior art keywords
film
semiconductor device
oxide film
heat treatment
sio
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP26402091A
Other languages
Japanese (ja)
Other versions
JPH05102183A (en
Inventor
あきつ 鮎川
茂夫 大西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP26402091A priority Critical patent/JP2716300B2/en
Priority to US07/932,943 priority patent/US5348900A/en
Publication of JPH05102183A publication Critical patent/JPH05102183A/en
Application granted granted Critical
Publication of JP2716300B2 publication Critical patent/JP2716300B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、より詳細にはMOS型半導体装置の製造方法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOS type semiconductor device.

【0002】[0002]

【従来の技術】従来のLDD(Lightly Doped Drain)構
造を有するMOS型メモリセルの製造方法を図2に基づ
いて説明する。まず、P型のシリコン基板(10)上に
活性領域及びフィールド酸化膜からなる素子分離領域を
形成することによって、素子形成領域を確保した後、ゲ
ート酸化膜としてSiO2 膜(2)が形成された素子形
成領域上に3500〜4000Åの厚さのポリシリコン
からなるゲート電極(3)を形成し、CVD法でSiO
2 膜を2500〜3500Åの厚さで堆積させ、ゲート
電極(3)の側壁にSiO2 からなるサイドウォール
(4)を反応性イオンエッチング(RIE)法及びHF
ウェットエッチング法によって形成するとともに、シリ
コン基板(10)上に約100〜400ÅのSiO2
(6)を形成する。
2. Description of the Related Art Conventional LDD (Lightly Doped Drain) structure
A method for manufacturing a MOS memory cell having a structure is described with reference to FIG.
Will be described. First, on a P-type silicon substrate (10)
An element isolation region consisting of an active region and a field oxide film
After forming an element formation region,
SiO2 as oxide filmTwoElement type with film (2) formed
3500-4000 mm thick polysilicon on the active area
Of a gate electrode (3) made of
TwoA film is deposited to a thickness of 2500-3500 °
SiO on the side wall of electrode (3)TwoSidewall consisting of
(4) using reactive ion etching (RIE) method and HF
It is formed by wet etching and
Approximately 100 to 400 ° of SiOTwofilm
Form (6).

【0003】次いで、ゲート電極(3)をマスクとして
ソース/ドレイン領域(8)となる領域にSiO2
(6)を介してAs等のN型不純物のイオン注入を行っ
てソース/ドレイン領域(8)を形成する(図2
(a))。そして、生成したソース/ドレイン領域
(8)の不純物を拡散させるため、例えば、800℃の
温度で1時間の中温熱処理を行う。
Then, using the gate electrode (3) as a mask, ion implantation of an N-type impurity such as As is performed on the region serving as the source / drain region (8) via the SiO 2 film (6) through the source / drain region (8). 8) (FIG. 2)
(A)). Then, in order to diffuse the generated impurities in the source / drain regions (8), for example, a medium temperature heat treatment is performed at a temperature of 800 ° C. for one hour.

【0004】その後、ソース/ドレイン領域(8)の外
方拡散を抑制するためにSiO2 膜(6)上にNSG膜
(11)を堆積し、その上にNSG膜(11)上の層間
段差を少なくするためにBPSG膜(12)を堆積し
て、例えば950℃で30分間の高温熱処理を行い、ソ
ース/ドレイン領域(8)を形成する(図2(b))。
Thereafter, an NSG film (11) is deposited on the SiO 2 film (6) in order to suppress outward diffusion of the source / drain region (8), and an interlayer step on the NSG film (11) is formed thereon. A BPSG film (12) is deposited to reduce the temperature, and a high-temperature heat treatment is performed at, for example, 950 ° C. for 30 minutes to form a source / drain region (8) (FIG. 2B).

【0005】[0005]

【発明が解決しようとする課題】微細MOS型トランジ
スタの諸特性の変動をもたらす原因の一つとして、ソー
ス/ドレイン領域の結晶欠陥の存在があげられるが、上
記した半導体装置の製造方法においては、イオン注入が
SiO2 膜(6)を通して行われるので、注入されるイ
オンがSiO2 膜(6)を通過する際に、SiO2
(6)中の酸素原子が反跳されて注入イオンとともにシ
リコン基板(10)に打ち込まれることとなり、シリコ
ン基板(10)に打ち込まれた酸素はシリコン基板(1
0)内に結晶欠陥(7)を発生させるという課題があっ
た。
One of the causes of variations in the characteristics of the fine MOS transistor is the presence of crystal defects in the source / drain regions. However, in the above-described method for manufacturing a semiconductor device, since the ion implantation is performed through the SiO 2 film (6), a silicon implanted ions when passing through the SiO 2 film (6), an oxygen atom of the SiO 2 film (6) in along with recoil has been implanted ions Oxygen implanted into the silicon substrate (10) will be implanted into the substrate (10).
There is a problem that a crystal defect (7) is generated in 0).

【0006】また、この結晶欠陥(7)はその後の熱処
理でも消失せず、半導体装置の電気的リークの原因とな
り、歩留り低下の原因となるという課題もあった。本発
明はこのような課題を鑑みなされたものであり、結晶欠
陥を発生させることなく、歩留りの高い半導体装置の製
造方法を提供することを目的としている。
Further, the crystal defect (7) does not disappear even in the subsequent heat treatment, causing an electric leak of the semiconductor device and a reduction in the yield. The present invention has been made in view of such problems, and has as its object to provide a method for manufacturing a semiconductor device having a high yield without generating crystal defects.

【0007】[0007]

【課題を解決するための手段】上記記載の課題を解決す
るために本発明によれば、側壁にサイドウォールが形成
されたゲート電極がゲート酸化膜を介して配設されてい
る半導体基板のソース/ドレイン領域となる部分に、酸
化膜を介して不純物をイオン注入して中温熱処理を行う
工程、半導体基板上の酸化膜を除去した後、アンモニア
雰囲気下で高温熱処理を行う工程を含むことを特徴とし
ている。
According to the present invention, in order to solve the above-mentioned problems, according to the present invention, a source of a semiconductor substrate in which a gate electrode having a sidewall formed on a side wall is disposed via a gate oxide film. A step of performing an intermediate temperature heat treatment by ion-implanting impurities through a oxide film into a portion serving as a / drain region, and a step of performing a high temperature heat treatment in an ammonia atmosphere after removing the oxide film on the semiconductor substrate. Features.

【0008】本発明において、中温熱処理は750〜8
50℃の温度範囲で、30〜60分間行うのが好まし
い。また、RTA装置中のアンモニア雰囲気下にて行う
高温熱処理は1000〜1100℃の温度範囲で、10
〜60秒間行うのが好ましい。
In the present invention, the intermediate temperature heat treatment is performed at 750 to 8
It is preferable to carry out in a temperature range of 50 ° C. for 30 to 60 minutes. The high-temperature heat treatment performed in an RTA apparatus under an ammonia atmosphere is performed in a temperature range of 1000 to 1100 ° C.
It is preferably performed for up to 60 seconds.

【0009】[0009]

【作用】上記した方法によれば、酸化膜を介してソース
/ドレイン領域にイオン注入した際に半導体基板内に生
じる挿入型の積層欠陥等の結晶欠陥を消失させるもので
ある。つまり、RTAのNH4 雰囲気下で高温熱処理を
行うことにより、高温のNH4 雰囲気下で半導体基板か
らSi原子が飛びだし、半導体基板内に空孔が強制的に
導入されることとなる。そして、その空孔が半導体基板
内に生じた欠陥を解消させて欠陥のない不純物拡散領域
を形成する。
According to the method described above, crystal defects such as insertion-type stacking faults generated in a semiconductor substrate when ions are implanted into a source / drain region through an oxide film are eliminated. That is, by performing the high-temperature heat treatment in the NH 4 atmosphere of RTA, Si atoms are ejected from the semiconductor substrate in the high-temperature NH 4 atmosphere, and holes are forcibly introduced into the semiconductor substrate. Then, the holes eliminate defects generated in the semiconductor substrate to form impurity-free impurity diffusion regions.

【0010】[0010]

【実施例】本発明に係る半導体装置の製造方法の実施例
を図面に基づいて説明する。まず、シリコン基板(1)
上に活性領域及びフィールド酸化膜からなる素子分離領
域を形成することによって、素子形成領域を確保し、ゲ
ート酸化膜としてSiO2 膜(2)を積層したのち、こ
の素子形成領域上に3500〜4000Åの厚さのポリ
シリコンからなるゲート電極(3)を形成する。そし
て、ゲート電極(3)上にCVD法で酸化膜としてSi
2 膜を2500〜3500Åの厚さで堆積させ、ゲー
ト電極(3)の側壁にSiO2 からなるサイドウォール
(4)を反応性イオンエッチング(RIE)法及びHF
ウェットエッチング法によって形成するとともに、シリ
コン基板(1)上に約100〜400ÅのSiO2
(6)を形成する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. First, silicon substrate (1)
An element formation region consisting of an active region and a field oxide film is formed thereon to secure an element formation region, and an SiO 2 film (2) is laminated as a gate oxide film. A gate electrode (3) made of polysilicon having a thickness of 3 nm is formed. Then, Si is formed as an oxide film on the gate electrode (3) by a CVD method.
An O 2 film is deposited to a thickness of 2500-3500 °, and a sidewall (4) made of SiO 2 is formed on the side wall of the gate electrode (3) by reactive ion etching (RIE) and HF.
An SiO 2 film (6) of about 100 to 400 ° is formed on the silicon substrate (1) while being formed by a wet etching method.

【0011】次いで、ゲート電極(3)をマスクとして
ソース/ドレイン領域(5)となる領域にAs等の不純
物を80KeV、5×1015ions/cm2 でイオン
注入してソース/ドレイン領域(5)を形成する(図1
(a))。そして、生成したソース/ドレイン領域
(5)の不純物を拡散させるため、例えば、800℃の
温度で1時間の中温熱処理を行う。
Next, using the gate electrode (3) as a mask, an impurity such as As is ion-implanted into the source / drain region (5) at 80 KeV and 5 × 10 15 ions / cm 2 to form the source / drain region (5). (FIG. 1)
(A)). Then, in order to diffuse the generated impurities in the source / drain regions (5), for example, a middle-temperature heat treatment is performed at a temperature of 800 ° C. for one hour.

【0012】その後、ゲート電極(3)及びシリコン基
板(1)上のSiO2 膜(6)を除去し、RTA(Rapid
Thermal Annealing)装置中のNH4 雰囲気下にて例え
ば、30秒間、1000℃の温度で高温熱処理する。こ
のように製造される半導体装置のシリコン基板(1)に
おいては、SiO2 膜(6)を通してイオン注入した際
に、シリコン基板(1)内に挿入型の積層欠陥等の結晶
欠陥(7)を生じる。そこで、NH4 雰囲気下にて短時
間高温熱処理することにより、空孔をシリコン基板
(1)内に強制的に導入することができ、シリコン基板
(1)に形成されていた積層欠陥(7)が消失し、均一
な面となることが確認された。
Thereafter, the gate electrode (3) and the SiO 2 film (6) on the silicon substrate (1) are removed, and RTA (Rapid) is removed.
Thermal annealing is performed at a high temperature of 1000 ° C. for 30 seconds in an NH 4 atmosphere in the apparatus. In the silicon substrate (1) of the semiconductor device manufactured as described above, when ions are implanted through the SiO 2 film (6), crystal defects (7) such as insertion type stacking faults are formed in the silicon substrate (1). Occurs. Therefore, by performing a high-temperature heat treatment in an NH 4 atmosphere for a short time, the vacancies can be forcibly introduced into the silicon substrate (1), and the stacking fault (7) formed in the silicon substrate (1) can be formed. Disappeared and a uniform surface was confirmed.

【0013】[0013]

【発明の効果】本発明に係る半導体装置の製造方法によ
れば、アンモニア雰囲気下にて短時間高温熱処理するの
で、酸化膜を通してイオン注入された半導体基板に生じ
る挿入型の欠陥部分に空孔を強制的に導入することがで
きる。そのため、欠陥のない不純物拡散領域が形成で
き、リーク電流を低下させることが可能となり、歩留り
を向上させる効果がある。
According to the method of manufacturing a semiconductor device according to the present invention, high-temperature heat treatment is performed for a short time in an ammonia atmosphere, so that holes are formed in insertion-type defects generated in a semiconductor substrate ion-implanted through an oxide film. Can be enforced. Therefore, a defect-free impurity diffusion region can be formed, the leak current can be reduced, and the yield is improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)〜(b)は本発明に係わる半導体装置の
製造方法の実施例を示す腰部の概略断面図である。
FIGS. 1A and 1B are schematic sectional views of a waist showing an embodiment of a method of manufacturing a semiconductor device according to the present invention.

【図2】(a)、(b)は従来の半導体装置の製造方法
の製造工程を示す腰部の概略断面図である。
FIGS. 2A and 2B are schematic cross-sectional views of a waist showing manufacturing steps of a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 シリコン基板(半導体基板) 2 SiO2 膜(ゲート酸化膜) 3 ゲート電極 4 サイドウォール 5 ソース/ドレイン領域 6 SiO2 Reference Signs List 1 silicon substrate (semiconductor substrate) 2 SiO 2 film (gate oxide film) 3 gate electrode 4 sidewall 5 source / drain region 6 SiO 2 film

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 側壁にサイドウォールが形成されたゲー
ト電極がゲート酸化膜を介して配設されている半導体基
板のソース/ドレイン領域となる部分に、酸化膜を介し
て不純物をイオン注入して中温熱処理を行う工程、半導
体基板上の酸化膜を除去した後、アンモニア雰囲気下で
高温熱処理を行う工程を含むことを特徴とする半導体装
置の製造方法。
An impurity is ion-implanted through an oxide film into a portion to be a source / drain region of a semiconductor substrate in which a gate electrode having a sidewall formed on a side wall is disposed via a gate oxide film. A method for manufacturing a semiconductor device, comprising: a step of performing a medium temperature heat treatment; and a step of performing a high temperature heat treatment in an ammonia atmosphere after removing an oxide film on a semiconductor substrate.
JP26402091A 1991-10-11 1991-10-11 Method for manufacturing semiconductor device Expired - Fee Related JP2716300B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP26402091A JP2716300B2 (en) 1991-10-11 1991-10-11 Method for manufacturing semiconductor device
US07/932,943 US5348900A (en) 1991-10-11 1992-08-21 Process for manufacturing a semiconductor device including heat treatment in ammonia or oxygen

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26402091A JP2716300B2 (en) 1991-10-11 1991-10-11 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH05102183A JPH05102183A (en) 1993-04-23
JP2716300B2 true JP2716300B2 (en) 1998-02-18

Family

ID=17397440

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26402091A Expired - Fee Related JP2716300B2 (en) 1991-10-11 1991-10-11 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2716300B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0621629A3 (en) * 1993-04-20 1996-07-17 Texas Instruments Inc Method for reducing dislocations in integrated circuit devices.
JP2776272B2 (en) * 1994-11-02 1998-07-16 日本電気株式会社 Method for manufacturing semiconductor device
US6121120A (en) * 1997-08-07 2000-09-19 Nec Corporation Method for manufacturing semiconductor device capable of flattening surface of selectively-grown silicon layer
KR101006513B1 (en) * 2003-11-12 2011-01-07 매그나칩 반도체 유한회사 Method of manufacturing semiconductor device

Also Published As

Publication number Publication date
JPH05102183A (en) 1993-04-23

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