JPH09172060A - Semiconductor device with trench element separation structure and its preparation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a high-concentration leakage current generated in the edge parts of an active region on a substrate from being generated by a field concentration due to a P-N junction. SOLUTION: This device comprises a substrate 100 formed with a trench 115 for limiting an active region, leakage current preventive parts 145 and 150, which are respectively formed under the edge parts of the entrance of the trench 115 and in the substrate 100 under the bottom of the trench 115 and contain doped impurities, and an element isolation film 155 consisting of an insulating material film filled in the interior of the trench 115. Thereby, a leakage current, which is generated in the edge parts of the active region on the substrate to be formed with an element, is prevented from being generated and the electrical characteristics of the element can be made to enhance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an element isolation structure of a semiconductor device, and more particularly, to a substrate at the edge of the entrance of the trench and a substrate at the bottom of the trench provided with a leakage current preventer so that the edge of the active region can be prevented. The present invention relates to a semiconductor device having a trench element isolation structure capable of preventing a leakage current that occurs and a manufacturing method thereof.

[0002]

2. Description of the Related Art A conventional device isolation method is to form a device isolation film by forming a trench in a predetermined portion of a substrate to limit an active region of the substrate and filling an insulating material in the trench. It is realized by using. 1 to 3
FIG. 6 is a cross-sectional view for explaining a conventional element isolation structure using a trench.

FIG. 1 shows a trench 2 which defines an element isolation region.
It is sectional drawing which shows 5. The cross-sectional structure shown in FIG. 1 has a structure in which an oxide film and a nitride film are sequentially stacked on a substrate 10.
A second step of patterning the two stacks to expose a predetermined portion of the substrate, and a third step of etching the substrate 10 exposed by the oxide pattern 15 and the nitride pattern 20 to form a trench 10. , And the substrate 10 inside the trench 25 is doped with impurities 35 to form a channel blocking region 40.

FIG. 2 is a cross-sectional view showing an element isolation film 45 formed by filling the inside of the trench 25 with an insulating material. In the cross-sectional structure shown in FIG. 2, a first step of removing the oxide film pattern (15 in FIG. 1) and the nitride film pattern (20 in FIG. 1), an insulating film is formed by burying an insulating material in the trench. It is formed by the second step of forming the element isolation film 45 by planarizing the insulating film on the substrate 10.

FIG. 3 is a sectional view showing the active region 55.
The active region 55 is formed by doping the substrate 10 with an impurity 50 having a conductivity type opposite to that of the impurity (35 in FIG. 1) doped to form the channel blocking region 40. At this time, impurities 35 and 5
A mixed impurity layer 60 in which 0s are superposed and doped is also formed. Here, the reference numeral “X” indicates a predetermined portion of the bonding interface formed at the edge of the active region 55.

FIG. 4 shows a normal transistor T1 formed in an active region defined by a conventional trench isolation layer and a parasitic transistor T3, T4, T2 formed in the edge of the active region and the isolation region. FIG. 5 is a schematic view, and FIG. 5 is a cross-sectional view of the substrate taken along the line 5-5 ′ of FIG. Element isolation film 4 formed in the trench 25
5 and 5 showing the structure of FIG. 5, the gate oxide film 6 is formed on the active region 55 doped with a predetermined impurity.
5 is formed, a gate electrode 70 is formed on the upper part of the gate oxide film 65 and a part of the device isolation film 45, and a channel diffusion prevention layer 40 is formed on the sidewall and bottom surface of the trench 25. ing. On the other hand, the normal transistor region T1 and the parasitic transistor regions T3, T4, and T2 shown in FIG. 4 are displayed on the gate electrode 70, and the junction interface between the element isolation film 45 and the active region 55 is indicated by a reference numeral ". Displayed as Y ".

The conductivity types of the impurities doped in the channel diffusion preventing layer 40 and the active region 55 are opposite to each other. On the other hand, the parasitic transistors T2, T3, T
In order to increase the threshold voltage of 4 and the punch-through voltage for device isolation, the impurities (35 in FIG. 1 and 50 in FIG. 3) are doped at a high concentration. As a result, a high-concentration PN junction having opposite conductivity types is formed between the channel blocking region 40 and the active region 55. At this time, an electric field concentration phenomenon occurs at the interface of the high-concentration PN junction, that is, “X” in FIG. 3 and “Y” in FIG. 5, so that the leakage current of the device increases.

Therefore, in order to prevent the electric field concentration phenomenon occurring at the high-concentration PN junction interface ("X" in FIG. 3, "Y" in FIG. 5), impurities doped in the channel blocking region (see FIG. The method of reducing the doping concentration of 35) of 1) has been proposed. However, such a method lowers the threshold voltage of the parasitic transistors T2, T3, and T4 and the punch-through voltage of the element isolation region, so that there is a problem that the leakage current increases.

As described above, the conventional element isolation technique cannot solve the problem that leakage current occurs at the edge of the active region. The leakage current of the device hinders the normal operation of the completed device and increases the operating power consumption of the MOS transistor. Therefore, the product yield is reduced.

[0010]

SUMMARY OF THE INVENTION The present invention has been devised to solve the above-mentioned conventional problems, and leaks due to electric field concentration due to a high-concentration PN junction generated at the edge of the active region. A trench isolation structure is provided, which includes a leakage current prevention unit including impurities doped in a substrate at an edge of an entrance of a trench and a substrate at a bottom of a trench so as to prevent a current from being generated. An object is to provide a semiconductor device.

Another object of the present invention is to provide a method of manufacturing a semiconductor device having the trench element isolation structure.

[0012]

In order to achieve the above object, a semiconductor device having a trench isolation structure according to the present invention comprises a substrate having a trench defining an active region, and an edge portion of the entrance of the trench. And a leakage current prevention part formed on the substrate on the bottom surface of the trench and containing doped impurities, and an isolation layer made of an insulating material filled in the trench.

In order to achieve the above other object, a method of manufacturing a semiconductor device having a trench isolation structure according to the present invention comprises: (a) forming an impurity doping prevention layer pattern exposing a predetermined portion of a substrate; (B) etching the exposed substrate using the impurity doping prevention layer pattern as a mask to form a trench;
(C) forming an etching prevention layer having a uniform thickness on the side wall and the bottom surface of the trench; and (d) forming an insulating film on the etching prevention layer and then etching the same. And forming an insulating film spacer exposing the etching prevention layer on the upper side wall of the trench and the bottom surface of the trench,
(E) forming a leakage current prevention part on the substrate at the edge of the entrance of the trench and the substrate at the bottom of the trench by doping impurities using the insulating film spacer and the impurity doping prevention layer pattern as a mask. It is characterized by including.

[0014]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. [Embodiment 1] FIG. 6 is a sectional view showing a trench element isolation structure according to an embodiment for achieving one object of the present invention. This is because the trench 115 formed in the substrate 100, the substrate 100 at the edge of the trench 115, and the leakage current prevention unit 14 formed in the substrate 100 at the bottom of the trench 115, respectively.
5 and 150, and a trench type element isolation structure including an element isolation film 155 formed by filling the trench 115 with an insulator.

The leakage current preventing portions 145 and 150 are doped with impurities of the same conductivity type as the semiconductor substrate 100. At this time, even if the leakage current preventing portions 145 and 150 are doped with a high concentration, unlike the prior art, the problem of leakage current due to electric field concentration does not occur. Meanwhile, the device isolation structure shown in FIG. 6 has an etching prevention layer (120 in FIG. 7) formed on the sidewalls and bottom of the trench 115 with a uniform thickness.
May be further provided.

[Embodiment 2] FIG. 7 is a cross-sectional view showing a trench isolation structure according to another embodiment of the present invention, in which an etching prevention layer is formed in the trench 115 shown in FIG. 120 and an insulating film spacer 130 are further provided. At this time, the etching prevention layer 120 is interposed between the insulating film spacer 130 and the sidewall of the trench 115. In addition, the insulating film spacer 130 is a material having a relatively high dry etching selection compared to the etching prevention layer 120.
For example, it can be formed using silicon nitride or polysilicon.

[Embodiment 3] FIGS. 8 to 12 are sectional views for sequentially explaining one embodiment for achieving another object of the present invention. FIG. 8 is a sectional view showing the trench 115 formed in a predetermined portion of the substrate 100. This is the first step of stacking an impurity doping prevention layer on the substrate 100, and patterning the impurity doping prevention layer to form the substrate 100.
Forming a trench 115 by etching the exposed substrate 100 using the impurity doping prevention layer pattern 105 as a mask, and forming a trench 115. And a fourth step of forming a thin film anti-etching layer 120 on the sidewalls and bottom of the trench 115.

FIG. 9 shows the insulating film 1 on the etching prevention layer 120.
It is sectional drawing which shows that 25 was apply | coated. At this time, the insulating layer 125 is formed using a material having a higher dry etching selection ratio than the etching prevention layer 120, such as silicon nitride or polysilicon.

FIG. 10 is a sectional view showing that an insulating film spacer 130 exposing a predetermined portion of the second etching prevention layer 120 is formed. The insulating film spacer 130 is formed by performing a dry etching process on the insulating film (125 in FIG. 9). The insulating layer spacer 130 exposes the sidewalls of the trench 115 and the etch prevention layer 120 on the bottom of the trench 115.

FIG. 11 shows the substrate 100 at the edge of the entrance of the trench 115 and the substrate 100 at the bottom of the trench 115.
FIG. 9 is a cross-sectional view showing that leakage current prevention parts 145 and 150 are formed on the inner surface. This is formed by implanting impurities 140 using the insulating film spacer 130 and the impurity doping prevention layer pattern 105 as an ion implantation mask. In FIG. 11, the cross arrow indicating the impurity 140 is the impurity 14 due to the change of the ion implantation incident angle.
0 is injected into the substrate 100 at the edge of the trench 115 and the substrate 100 at the bottom of the trench 115. At this time, it is preferable that the ion implantation angle is symmetrical with respect to the normal line of the upper surface of the substrate 100. Further, the impurities 140 may have the same conductivity type as the substrate 100. Therefore, the trench 11
The substrate 140 at the edge of No. 5 is uniformly doped with the impurities 140 to form the leakage current prevention unit 145. At this time, the leakage current prevention part 145 formed on the sidewall of the trench 115 is usually formed in a fan shape.

FIG. 12 is a sectional view showing an element isolation film 155 formed by filling the inside of the trench 115 with an insulating material. The device isolation layer 155 includes a first step of removing the impurity doping prevention layer pattern (105 of FIG. 11), a second step of filling the trench 115 with an insulating material to form the device isolation layer 155, and an upper portion thereof. It is formed by the third step of flattening the surface. At this time, the flattening step of the third stage is arbitrarily performed by the subsequent steps.

[Embodiment 4] FIG. 13 is a cross-sectional view showing another embodiment for achieving another object of the present invention. Specifically, after sequentially performing the steps of FIGS. 8 to 11, the insulating film spacers 130 formed on the sidewalls of the trench 115 are removed, and the inside of the trench 115 is filled with an insulating material. The separation film 155 is formed.

[Embodiment 5] FIG. 14 is a sectional view for explaining still another embodiment which achieves another object of the present invention. Specifically, after sequentially performing the steps of FIGS. 8 to 10, the structure shown in FIG.
In the first step of applying the resultant to the entire surface of the resultant, a high temperature heat treatment process is performed to remove the impurities contained in the impurity source film 160 using the doping prevention layer pattern 105 and the insulating film spacer 130 as a diffusion mask.
The leakage current prevention unit 1 by thermally diffusing the substrate 100 at the edge of 15 and the substrate 100 at the bottom of the trench 115.
It is formed by the second step of forming 45 and 150, respectively. On the other hand, it is desirable to perform the first step and the second step at the same time from the viewpoint of process simplification.

After the impurity diffusion step, the impurity source layer 160 and the doping prevention layer pattern 105 are removed. Then, the device isolation layer 155 is formed by filling the inside of the trench 115 with an insulating material to form the cross-sectional structure of FIG. At this time, a step of removing the insulating film spacer 130 before forming the device isolation film 155 may be further included, and a resultant structure thereof is similar to that of FIG.

[0025]

Various embodiments according to the present invention, that is,
Parasitic transistor generated at an edge of an active region by an element isolation structure and an element isolation method using the trench 115 having the leakage current prevention portions 145 and 150 formed on the substrate 100 on the edge of the trench 115 and the bottom surface of the trench 115. It is possible to improve the electrical characteristics of the device by preventing the generation of leakage current.

The present invention is not limited to the above embodiments, and it is obvious that many modifications can be made by a person having ordinary skill in the art within the technical idea of the present invention.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a conventional method used to manufacture a device isolation film of a semiconductor device.

FIG. 2 is a cross-sectional view illustrating a conventional method used to manufacture a device isolation film of a semiconductor device.

FIG. 3 is a cross-sectional view illustrating a conventional method used to manufacture a device isolation film of a semiconductor device.

FIG. 4 is a schematic view of a transistor manufactured by a conventional method.

5 is a cross-sectional view taken along line 5-5 'of FIG.

FIG. 6 is a cross-sectional view illustrating the first embodiment of the present invention.

FIG. 7 is a sectional view illustrating a second embodiment of the present invention.

FIG. 8 is a sectional view illustrating a third embodiment of the present invention.

FIG. 9 is a sectional view illustrating a third embodiment of the present invention.

FIG. 10 is a sectional view illustrating a third embodiment of the present invention.

FIG. 11 is a sectional view illustrating a third embodiment of the present invention.

FIG. 12 is a sectional view illustrating a third embodiment of the present invention.

FIG. 13 is a sectional view illustrating a fourth embodiment of the present invention.

FIG. 14 is a sectional view illustrating a fifth embodiment of the present invention.

[Explanation of symbols]

 100 substrate 105 doping prevention layer pattern 115 trench 120 etching prevention layer 125 insulating film 130 insulating film spacer 140 impurity 145 leakage current prevention unit 150 leakage current prevention unit 155 element isolation film 160 source film

Claims (22)

[Claims] 1. A substrate on which a trench defining an active region is formed, a leakage current prevention unit including doped impurities formed on an edge of an entrance of the trench and a substrate on a bottom surface of the trench, and the trench. And a device isolation film made of an insulating material filled inside the semiconductor device, the semiconductor device having a trench device isolation structure. 2. The semiconductor device having a trench isolation structure according to claim 1, wherein the impurities have the same conductivity type as the substrate. 3. The semiconductor device having the trench isolation structure according to claim 2, further comprising an etching prevention layer having a uniform thickness on the sidewall of the trench and the bottom surface of the trench. . 4. The trench isolation according to claim 3, further comprising an insulating film spacer on the etching prevention layer, which exposes an etching prevention layer on an upper portion of a sidewall of the trench and a bottom surface of the trench. A semiconductor device having a structure. 5. The semiconductor device having a trench isolation structure according to claim 4, wherein the insulating film spacer is formed of a material having a relatively high dry etching selection ratio with respect to the etching prevention layer. apparatus. 6. The semiconductor device having a trench isolation structure according to claim 5, wherein the insulating film spacer is made of silicon nitride or polysilicon. 7. (a) Forming an impurity doping prevention layer pattern exposing a predetermined portion of the substrate, and (b) etching the exposed substrate using the impurity doping prevention layer pattern as a mask. Forming a trench; (c) forming an etching prevention layer having a uniform thickness on the side wall and the bottom surface of the trench; and (d) forming an insulating film on the etching prevention layer. And forming an insulating film spacer exposing the etching prevention layer on the upper side wall of the trench and the bottom surface of the trench, and (e) the insulating film spacer and the impurity doping prevention layer. Forming a leakage current prevention part on the substrate at the edge of the entrance of the trench and on the substrate at the bottom of the trench by doping impurities using the pattern as a mask. A manufacturing method of a semiconductor device having a trench isolation structure according to symptoms. 8. The trench according to claim 7, wherein the insulating layer of step (d) is formed using a material having a relatively high dry etching selection ratio with respect to the etching prevention layer. A method of manufacturing a semiconductor device having an element isolation structure. 9. The method of manufacturing a semiconductor device having a trench isolation structure according to claim 7, wherein the insulating film of step (d) is made of silicon nitride or polysilicon. 10. The method of claim 7, wherein the impurity doping in the step (e) is performed using impurities having the same conductivity type as that of the substrate. Method. 11. The method of manufacturing a semiconductor device having a trench isolation structure according to claim 10, wherein the impurity doping in the step (e) is performed by an ion implantation process. 12. The method of manufacturing a semiconductor device having a trench isolation structure according to claim 11, wherein the ion implantation step is performed while changing an ion implantation incident angle. 13. The trench isolation structure according to claim 12, wherein the ion implantation incident angle changes within a range having a predetermined symmetry angle with respect to a normal line of a plane of a substrate into which ions are implanted. A method for manufacturing a semiconductor device comprising: 14. After forming the insulating film spacer of step (d), forming an impurity source layer on the upper side wall of the trench and the etching prevention layer on the bottom surface of the trench exposed by the insulating film spacer. The method for manufacturing a semiconductor device having a trench element isolation structure according to claim 7, further comprising: 15. The semiconductor device having a trench isolation structure according to claim 14, wherein, after forming the impurity source layer, the impurity doping in the step (e) is performed by a thermal diffusion method. Production method. 16. The semiconductor device having a trench isolation structure according to claim 15, further comprising removing the impurity source layer after the impurity doping step by the thermal diffusion method of step (e). Device manufacturing method. 17. After removing the impurity source layer,
18. The method of claim 16, further comprising removing the insulating film spacer. 18. After removing the insulating film spacer,
18. The method of claim 17, further comprising removing the etching prevention layer. 19. The semiconductor device having a trench isolation structure according to claim 15, wherein the step of doping impurities by the thermal diffusion method of step (e) is performed simultaneously with the step of forming the impurity source layer. Device manufacturing method. 20. The semiconductor device having a trench isolation structure according to claim 19, further comprising a step of removing the impurity source layer after the impurity doping step by the thermal diffusion method of the step (e). Manufacturing method. 21. After removing the impurity source layer,
21. The method as claimed in claim 20, further comprising removing the insulating film spacer. 22. After removing the insulating film spacer,
22. The method of claim 21, further comprising removing the etching prevention layer.