JP2000200902A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit on which an active clamping circuit is loaded in which a chip area can be miniaturized. SOLUTION: This semiconductor integrated circuit is provided with at least an (n)-well (NWL) 3, a first (p) base region (PBA) 4 and a second (p) base region (PBA+PBA2) 7 inside the (n)-well (NWL) 3, an (n)-type source region 5, a second (p) base region (PBA+PBA2) 7, a (p)-type anode contact region 8 on the surface of the second (p)-base region (PBA+PBA2) 7, an (n)-type drain/ cathode region 2 (NBL), and a gate structure 18. A reverse breakdown voltage Vr of a diode constituted between the anode contact region 8 and the drain/ cathode region 2 is made lower than an drain/source blocking voltage BVdss of a power MOS which is constituted of the drain/cathode region (NBL) 2, gate structure 18, and source region 5. The drain/cathode region (NBL) 2 is connected with an inductive load.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a circuit for protecting a power semiconductor device (power device) from a surge voltage or the like.

[0002]

2. Description of the Related Art Conventionally, an active clamp circuit has been known as a circuit for protecting a power semiconductor element (power device) from a surge voltage or the like. FIG. 6 shows a configuration of a semiconductor integrated circuit equipped with this type of active clamp circuit. FIG. 7 is a circuit diagram of the main part. As shown in FIG. 7, a buffer 50 is connected to the control input terminal 41, and the output of the buffer 50 is connected to a resistor R _0.
Through the gate of the n-channel power MOS transistor 42. The load element 43 is connected to the drain electrode of the n-channel power MOS transistor 42. The plurality of constant voltage diodes 51 to 57 are connected in series, and the cathode terminal of the final diode 51 is connected to the drain electrode of the n-channel power MOS transistor 42. A plurality of constant voltage diodes 51 connected in series
The anode end of the diode 57 at the leading end of .about.57 is connected to the anode end of the general diode 58, and the cathode end of the general diode 58 is connected to one end of the resistor _R0 and the gate electrode of the n-channel power MOS transistor 42. I have.

In order to integrate the circuit shown in FIG. 7 on the same semiconductor chip, as shown in FIG.
A p-base region (PBA) 4 is formed in an n-well (NWL) 3 serving as a drift region of the OS transistor 42, and a source region 5 and a base contact region 6 are formed therein. The n-well (NWL) 3 is selectively formed inside a p-epitaxial growth layer (p-epi layer) 11 formed above the p-substrate 1 via a buried region (NBL) 2. The source region 5 and the p base contact 6 are connected to the aluminum wiring 15 through the contact plug 12.
To form a source electrode, and this source electrode is grounded. An n-type sinker region 9 reaching the n-buried region (NBL) is formed in the n-well (NWL) 3.
A sinker contact region 10 is formed on the surface of the n-type sinker region 9. The sinker contact region 10 is formed on the aluminum wiring 1 through the contact plug 13.
7 and this aluminum wiring 17 becomes a drain electrode. This drain electrode is connected to the load element 43 as shown in FIG.
Connected to.

The constant voltage diodes 51 to 57 and the general diode 58 shown in FIG. 7 are formed of polysilicon on an oxide film. The constant voltage diodes 51 to 57 and the diode 51 are formed on the junction surface between the p-type impurity doped portion and the n-type impurity doped portion of the polysilicon wiring portion. As shown in FIG. 6, an anode electrode 14 connected to p-type polysilicon and n
It has a cathode electrode 19 connected to the mold polysilicon (only one of them is shown in FIG. 6).

In FIG. 7, a control signal input to a control input terminal 41 is input to the gate of an n-channel power MOS transistor 42 via a buffer 50 and a resistor R ₀ . First, when the gate voltage of the n-channel power MOS transistor 42 is “0”, the n-channel power MOS transistor 42 is in the OFF state, and the drain-source voltage Vds becomes equal to the power supply voltage.

Next, when the gate voltage of the n-channel power MOS transistor 42 becomes "1", the n-channel power MOS transistor 42 is turned on, and the drain-source voltage Vds becomes substantially equal to the ground voltage. Here, when the gate voltage of the n-channel power MOS transistor 42 becomes “0” again, the n-channel power MOS transistor 42 is turned off.

When the load element 43 is an inductive element (for example, a coil), the load element 43 has a function of maintaining the current that has been flowing so far, so that at the time of turn-off, V (t) =-Ldi / dt. ... (1) The back electromotive voltage of (1) is generated. Here, L indicates the self-inductance of the inductive load, and di / dt is a differential operator of current i with respect to time t. Therefore, the drain-source voltage Vds tends to be higher than the power supply voltage by approximately L · di / dt. Here, the threshold voltage of the n-type MOS transistor 42 is Vth, the reverse breakdown voltages of the constant voltage diodes 51 to 57 are Vz, and the constant voltage diode 51 is
Assuming that the number of stages of ５７57 is n (here, the number of stages is n = 7) and the forward voltage of the general diode 58 is Vfp, the drain-source voltage Vds is Vds <Vth + n · Vz + Vfp. (2), the constant voltage diodes 51 to 57 and the general diode 58 are turned on, and the gate voltage of the n-channel power MOS transistor 42 is set to Vgs, and Vgs = Vds− (n · Vz + Vfp) ··· ... (3) are applied, and the n-channel power MOS transistor 42
Turns on. As a result, the drain-source voltage Vds is clamped at a voltage of approximately Vth + nVz + Vfp, and if Vds <BVdss, the element breakdown of the n-channel power MOS transistor 42 can be prevented. That is, when a surge voltage is applied, a current flows through the constant voltage diodes 51 to 57 and the general diode 58, a voltage is applied to the gate, and the n-channel power MOS transistor 42 is turned on to prevent breakdown. In such an active clamp circuit, the clamp voltage can be approximated by Vds = Vth + nVz + Vfp (4). That is, if Vz = 6V, the clamp voltage is varied in 6V steps.

[0008]

However, such a conventional semiconductor integrated circuit (active clamp circuit)
In this case, the diode (constant voltage diodes 51 to 57 and diode 58) used to protect the surge and the manufacturing process of the n-channel power MOS transistor 42 to be protected are each performed independently and in different time series. That is, the n-channel power MOS transistor 42
N well (NWL) 3 and p base region (PBA)
4, a step of forming the source region 5 and the base contact region 6 by selective diffusion, and forming polycrystalline silicon (polysilicon) by CVD on the constant voltage diodes 51 to 57 and the diode 58 on the oxide film. N for silicon
This step is completely independent of the step of introducing (doping) the type and p-type impurities. According to the order, the source region 5,
After forming the base contact region 6, an oxide film is formed, and then the CV of polycrystalline silicon (polysilicon) is formed.
Step D is performed. In addition, the behavior of impurity diffusion is different between single crystal silicon and polysilicon. Further, the shapes of the n-well (NWL) 3 and the p-base region (PBA) 4 constituting the n-channel power MOS transistor 42 are completely different from the anode regions and the cathode regions of the diodes 51 to 57, 58. Therefore, variations in manufacturing steps such as process conditions occur completely independently, and their electrical characteristics vary independently. For example, the variation in the reverse breakdown voltage Vz of the constant voltage diodes 51 to 57 made of polysilicon is substantially determined by the impurity density distribution and the thickness of the junction surface of polysilicon. On the other hand, n-channel power M
Drain-source breakdown voltage BVds of OS transistor 42
Since s is generally determined by the distribution and thickness of the impurity density of the well and the p-based impurity density, they vary independently.

As described above, there is no correlation between the variations in the characteristics of the n-channel power MOS and the diodes 51 to 57 and 58 in the prior art. If there is no correlation between the variations, it is necessary to estimate the maximum variation width in anticipation of the case where the variations overlap each other. As a result, an unnecessarily high safety factor must be estimated for the n-channel power MOS transistor 42 to be protected, and the transistor must have a higher withstand voltage.

More specifically, the variations in the drain-source breakdown voltage BVdss of the n-channel power MOS transistor 42 and the reverse breakdown voltage Vz of the constant voltage diodes 51 to 57 are each set to ± 10% of the center value, and even in the worst case. Considering the case where a clamp voltage of 37 V or more is secured, Vds (min) = 37 V <Vth + nVz (min) + Vfp (5) Here, Vth = 2V, Vfp = 0.7V, Vz (ty
Assuming that p) = 6V and Vz (min) = 5.4V, then 37V <Vth + nVz (min) + Vfp = 2 + n5.4 + 0.7 (6) Here, the number n of stages of the constant voltage diodes 51 to 57
If 7 is set, Vz (min) = 2 + 7 × 5.4 + 0.7 = 40.5> 37 (= Vds (min)) (7)

On the other hand, when the reverse breakdown voltage Vz of the constant voltage diodes 51 to 57 is the maximum allowable value Vz (max) and the drain-source breakdown voltage BVdss of the n-channel power MOS transistor 42 is the minimum value BVdss (min). But Vd
s <BVdss must be satisfied. Here, Vz (max) =
Assuming 6.6 V, Vds <Vth + nVz (max) + Vfp = 2 + 7 + 6.6 + 0.7 = 48.9 V (8) That is, when the clamp voltage is 37 V or more, since BVdss (min)> 48.9 V, the drain-source breakdown voltage BVdss (typ) is 48.9 / 0.9 = 54.4.
V or more.

As described above, in a semiconductor integrated circuit on which a conventional active clamp circuit is mounted, the drain-source breakdown voltage B of the n-channel power MOS transistor 42 is
Since the variation of Vdss and the reverse breakdown voltage Vz of the constant voltage diodes 51 to 57 occur "with no correlation" with each other, the drain-source breakdown voltage BVdss of the n-channel power MOS transistor 42 can be increased more than necessary. Required. This means that the thickness of each layer constituting the n-channel power MOS transistor 42 must be increased or a semiconductor layer having a higher specific resistance must be used. In particular, it is required to increase the thickness of an n-well (NWL) functioning as an n-drift region (n-drain region) or to use a semiconductor layer having higher specific resistance for the n-well (NWL). n-well (N
As the thickness WL) increases and the specific resistance increases, the on-resistance per unit area increases. As a result, in order to keep the conduction loss below a certain value, the n-channel power MO
There is a problem that the area occupied by the S transistor 42 needs to be larger than necessary.

SUMMARY OF THE INVENTION An object of the present invention is to provide a novel structure in which, among circuit elements constituting an active clamp circuit, a circuit element having a problem of characteristic variation can be formed by a diffusion process for the same semiconductor region. An object of the present invention is to provide a semiconductor integrated circuit capable of reducing “relative variation” of characteristics and a method of manufacturing the same.

[0014]

In view of the above, a semiconductor integrated circuit according to a first aspect of the present invention includes an n-type semiconductor region and a first p-base region disposed inside the semiconductor region. And a second p-base region, an n-type source region disposed on the surface of the first p-base region, and an n-type drain / cathode disposed below the first and second p-base regions. And a gate structure arranged near the first p-base region and controlling a current flowing through the first p-base region. Is characterized in that the reverse breakdown voltage of the diode is lower than the drain-source breakdown voltage of the transistor comprising the drain / cathode shared region, the gate structure and the source region.

In the present invention according to claim 2,
The drain / cathode combined region is electrically connected to the load element, the source region is grounded, and the gate structure has first and second regions.
A control signal is input through an OR circuit having an input terminal of. With this configuration, it is possible to operate as an active clamp circuit that protects the transistor from a surge voltage or an abnormally high voltage.

Further, according to the present invention, a control signal is inputted to the first input terminal, and the second input terminal and the second p base region are electrically coupled. Here, "electrically coupled" refers to the direct connection between the second input terminal and the second p base region, as well as the second input terminal and the second p base region. And the presence of another element or the like. On the surface of the second p-base region, a p-type anode contact region can be further arranged, in which case the second input terminal is:
It is electrically connected to the second p base region through the anode contact region. A typical example of a load element connected to the drain / cathode shared region is an inductive load.

According to the semiconductor integrated circuit equipped with such an active clamp circuit, both the transistor and the diode can be formed by the step of selectively diffusing p-type impurities into the same n-type semiconductor region, and the step of selectively ion-implanting. And a heat treatment step can be performed at the same time, so that the manufacturing steps of both devices can be made substantially common. Further, the same n-type semiconductor region can be shared as the cathode region and the n drift region. Further, the first and second p
Since the base regions can be arranged close to each other, substantially the same variation in the manufacturing process occurs with respect to the first and second p base regions. For example, variations in the dose during ion implantation vary in the same tendency because they are spatially close. Therefore, the correlation between the collector-source breakdown voltage of the transistor and the relative breakdown caused by the manufacturing process and structure between the reverse breakdown voltage Vr of the surge protection diode is established, and the relative variation can be essentially reduced. it can.

As a result, it is possible to effectively protect a transistor having a low withstand voltage. That is, a transistor with a lower breakdown voltage can be used. If the withstand voltage can be reduced, for example, the thickness of the semiconductor region serving as the drift region can be reduced, so that the thickness of the n-well or the n-epitaxial growth layer can be reduced. Alternatively, the specific resistance of the semiconductor region serving as the drift region can be reduced. Therefore, the on-resistance per unit area can be reduced. as a result,
With the same chip area, a larger current can be passed,
If the current values are the same, the chip area can be made smaller and the cost can be reduced. Therefore, it is not necessary to increase the area of the transistor more than is originally required. A chip is downsized by reducing the area occupied by the transistor.

In particular, according to the fourth aspect of the present invention, the OR
A first resistor having the other end grounded is connected to the second input terminal side of the circuit, and a first resistor is connected between the second input terminal of the OR circuit and the second p base region (anode region of the diode). If the reverse breakdown voltage Vr of the diode becomes too small, the clamp voltage is adjusted to a desired value by adjusting the values of the first resistor and the second resistor. It can be.

In order for the reverse breakdown voltage Vr of the diode to be lower than the drain-source breakdown voltage of the transistor, the impurity concentration of the first p-base region may be reduced. However, the introduction amount of the impurity is set so as to be lower than the impurity density of the second p base region. In this case, if the configuration is made as in the fourth aspect of the invention, the clamp voltage can be changed by adjusting the values of the first resistor and the second resistor, so that the clamp voltage is injected into the second p base region. It is possible to increase the degree of freedom in selecting the dose of the impurity.

Further, according to the present invention, the first
The reverse breakdown voltage Vr of the diode can be reduced even if the respective heat treatment conditions are set so that the diffusion depth of the p base region becomes deeper than the diffusion depth of the second p base region. It can be made lower than the source breakdown voltage.

Further, as in the seventh aspect of the present invention, the geometrical shape of the first p base region is the second p base region.
By making the shape similar to the geometric shape of the base region, the reverse breakdown voltage Vr of the diode and the breakdown voltage between the drain and the source of the transistor can be defined in the same tendency. For example, if the geometric shapes are similar, the radius of curvature of the corner of the first p base region and the second p
Since the radius of curvature at the corner of the base area is the same,
The electric field concentration at the corner also has a correlation, and a variation in breakdown voltage occurs with a similar tendency. As described above, by making the geometrical shape of the first p-base region and the geometrical shape of the second p-base region similar, the withstand voltage between the collector and the source of the transistor and the surge protection are improved. This is preferable because a correlation is easily established between the relative variation of the diode and the reverse breakdown voltage Vr.

In the invention according to claim 8, the drain / cathode region is formed as a buried region, and the semiconductor device further comprises an n-type lead region (sinker) extending from the surface of the semiconductor region to the drain / cathode region. Such a horizontal structure is employed, which is advantageous for integration.

Further, in the invention according to claim 9,
A drain / cathode combined region is formed on the back surface of the semiconductor substrate, and a vertical structure in which a metal electrode is in ohmic contact with the drain / cathode combined region is provided, thereby facilitating the manufacturing process.

Further, in the invention according to claim 10 of the present invention, the gate structure comprises a groove formed from the surface of the first p base region to the bottom thereof, and a gate insulating film formed on a side wall of the groove. A groove-type gate structure at least composed of a film and a control electrode buried in the groove, facilitating high-speed operation by shortening the channel,
The structure is such that the ON resistance per unit chip can be reduced.

On the other hand, in the invention according to claim 11,
depositing an n-type semiconductor region over the n-type drain / cathode combined region;
A step of introducing a p-type impurity at a first dose into a portion where a second p-base region is to be formed; And a step of introducing a n-type impurity into the surface of the first p-base region to form a source region. Here, the “drain / cathode combined region” may be an n-type substrate having a high impurity density or a buried region. As a result, a diode is formed between the second p base region and the drain / cathode combined region,
A transistor is formed between the cathode shared region and the source region. Then, in addition to the first dose, a second dose impurity is introduced into the second p base region, so that the second p base region has a higher impurity density region than the first p base region. I can do it. As a result, the reverse breakdown voltage of the diode becomes lower than the drain-source breakdown voltage of the transistor.

According to the method for manufacturing a semiconductor integrated circuit according to the eleventh aspect, the transistor and the diode can be manufactured by a series of manufacturing steps including a step of introducing a p-type impurity into the same n-type semiconductor region. , Heat treatment process and the like can be performed simultaneously, and the manufacturing process of both devices can be made substantially common. Further, the same n-type semiconductor region can be shared as the cathode region and the n drift region.
Therefore, the correlation between the collector-source breakdown voltage of the transistor and the relative breakdown caused by the manufacturing process and structure between the reverse breakdown voltage Vr of the surge protection diode is established, and the relative variation can be essentially reduced. it can.

As a result, it is possible to provide a method of manufacturing an active clamp circuit that can effectively protect a transistor having a low withstand voltage. That is, a transistor mounted on a semiconductor chip can be handled by a transistor having a lower breakdown voltage. Since the withstand voltage of the transistor can be reduced, the thickness of the n-type semiconductor region included in the transistor can be reduced. For this reason, the on-resistance of the transistor per unit area can be reduced, and the chip area can be reduced if the rated current value is the same, so that a low-cost semiconductor integrated circuit can be manufactured easily with a high manufacturing yield.

[0029]

According to the present invention, it is possible to more effectively and reliably protect a transistor from a surge voltage. As a result, the reliability of the transistor is improved.

According to the present invention, the withstand voltage of the transistor to be protected can be relatively reduced, so that the on-resistance per unit area of the transistor can be reduced and the conduction loss can be reduced. Thus, a highly efficient semiconductor integrated circuit can be provided.

According to the present invention, since the on-resistance per unit area can be reduced, the area occupied by the transistor can be reduced, and the chip area of the semiconductor integrated circuit can be reduced and the integration density can be increased. Become. as a result,
The manufacturing cost of a semiconductor integrated circuit can be reduced and an inexpensive electronic device can be provided.

According to the present invention, it is possible to provide a method of manufacturing a semiconductor integrated circuit capable of effectively and surely protecting a transistor from a surge voltage by eliminating variations in characteristics of circuit elements at the time of manufacturing.

According to the manufacturing method of the present invention, a semiconductor integrated circuit having a low on-resistance per unit area and capable of reducing the chip area and increasing the integration density can be easily manufactured at a low manufacturing cost.

[0034]

Next, first to third embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimension, the ratio of the thickness of each layer, and the like are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. In addition, it goes without saying that parts having different dimensional relationships and ratios are included between the drawings.

(First Embodiment) The present invention will be described below with reference to the drawings. FIG. 1 is a sectional structural view of a main part of a semiconductor integrated circuit on which an active clamp circuit according to a first embodiment of the present invention is mounted. FIG. 2 is a circuit diagram of main parts of the active clamp circuit (semiconductor integrated circuit). In a semiconductor integrated circuit equipped with an active clamp circuit according to the first embodiment of the present invention, a lateral type n-channel power MOS transistor (hereinafter, referred to as a first embodiment) is an example of a transistor to be protected from a surge voltage. , Abbreviated as “lateral power MOS”).

As shown in FIG. 1, the semiconductor integrated circuit having the active clamp circuit according to the first embodiment of the present invention has an n-well (NWL) 3 as an n-type semiconductor region.
And a first element disposed inside the n-well (NWL) 3.
P base region (PBA) 4 and second p base region (PBA + PBA 2) 7 and first p base region (PB)
A) an n-type source region 5 disposed on the surface of
, A p-type anode contact region 8 disposed on the surface of the p base region (PBA + PBA2) 7, a first p base region (PBA) 4 and a second p base region (PBA +
An N-type drain / cathode region (n-buried region: NBL) 2 disposed below the PBA 2) 7 and a first p-base region (PBA) 4 are disposed near the first p-type region.
A gate structure for controlling a current flowing through the base region. The n-well (NWL) 3 is selectively formed inside a p epitaxial growth layer (p epi layer) 11 formed on the p substrate 1. The p-type anode contact region 8 is formed in the second p-base region (PBA
+ PBA2) can be omitted if the impurity density of 7 is sufficiently high. The gate structure has a first p base region (PBA) 4
, And at least a control electrode 18 formed on the gate insulating film. The control electrode 18 is a polysilicon made of a polycrystalline silicon (doped polysilicon) film to which an impurity is added. When a high-melting point metal such as tungsten (W), titanium (Ti), or molybdenum (Mo) is used instead of doped polysilicon, gate resistance is reduced, and high-speed operation and uniform operation in a large area can be performed. . Further, silicide (WSi ₂ , TiSi ₂ , M
It is also possible to use oSi ₂ ) or polycide using these silicides as the electrode material of the control electrode 18. The anode contact region 8 is a p region having a higher impurity density than the second p base region (PBA + PBA2) 7. The drain / cathode combined region is a buried region (N
BL), the n-well (NWL)
From the surface of No. 3, the drain / cathode combined area (NBL)
N-type lead region (n sinker: NSK) 9
Is further provided. On the surface of the n sinker (NSK) 9, a sinker contact region 10 composed of an n region having a higher impurity density than the n sinker (NSK) 9 is formed. Although not shown, the planar shape of the source region 5 is a donut shape. At the center of the donut, a base contact region 6 formed of a p region having a higher impurity density than the first p base region (PBA) 4 is further formed. Various geometric shapes such as a circular donut shape, a rectangular donut shape, or a polygonal donut shape can be adopted as the planar shape of the source region 5. The source region 5 and the base contact region 6 of the lateral power MOS are short-circuited by a contact plug 12, and the contact plug 12 is connected to an aluminum wiring 15. The aluminum wiring 15 functions as a source electrode. The anode contact region 8 is connected to the aluminum wiring 16 via the contact plug 14 to form an anode electrode. Further, the aluminum wiring 17 serving as the drain / cathode shared electrode is formed on the
2 is connected to a contact plug 13 through a contact hole opened in the inside. The aluminum wiring 16 is connected to the contact plug 14 via a contact hole opened in the second interlayer insulating film 32. The contact plugs 12, 13 and 14 are formed on the first interlayer insulating film 31.
Doped polysilicon, tungsten (W), titanium (T
i), a high melting point metal such as molybdenum (Mo) may be used. Alternatively, the side (W
Si ₂ , TiSi ₂ , MoSi ₂ ) or polycide using these silicides may be embedded. Aluminum wiring 1
A passivation film 33 is deposited on 5, 16, 17 and the second interlayer insulating film 32. However, the above-described metal wiring structure is merely an example. In some cases, the contact plugs 12, 13, and 14 are omitted, and the aluminum wirings 15, 1 are omitted.
It is possible to make ohmic contacts 6 and 17 directly to the semiconductor region. In FIG. 1, the aluminum wirings 15, 1
Although the structure is shown in which the metal wirings 6 and 17 have the same metal wiring level, the aluminum wiring 15 is provided in the first layer, and the aluminum wirings 16 and 17 in the second layer are formed via an interlayer insulating film thereover. Needless to say, the multi-layer wiring structure described above can be adopted.

This semiconductor integrated circuit has a reverse breakdown voltage Vr of a diode 44 (see FIG. 2) formed between the anode contact region 8 and the drain / cathode region 2.
Is a lateral power MO composed of a drain / cathode combined region (NBL) 2, a gate structure 18 and a source region 5.
The drain-source breakdown voltage BVdss of S42 (see FIG. 2)
BVdss> Vr... (9).

This diode 44 has a lateral power M
A constant voltage diode as a surge protection diode for protecting the OS 42. As is apparent from FIG. 1, the cathode region of the constant voltage diode 44 has a lateral power M
An n-well (NWL) 3 serving as a drift region of the OS 42 is shared. Second p base region (PBA + PBA
2) 7 functions as an anode region of the constant voltage diode 44. As can be understood by referring to FIG. 2, the drain / cathode combined region (NBL) 2 has n
It is electrically connected to the load element 43 via the sinker (NSK) 9 and the aluminum wiring 17 serving as the drain / cathode electrode. The source region 5 is grounded via an aluminum wiring 15, and a control signal is input to a polysilicon gate electrode 18 constituting a gate structure via an OR circuit 45. Here, the OR circuit 45 has at least first and second input terminals, a control signal is input to the first input terminal, and the anode contact region 8 is connected to the second input terminal.
Is connected. On the second input terminal side of the OR circuit 45,
Resistor R ₁ which is grounded and the other end as shown in FIG. 2 are connected. A typical inductive load 43 is a load element connected to the common drain / cathode region (NBL) 2. However, the load element 43 shown in FIG. 2 may be a load element connected outside the semiconductor integrated circuit. Further, an OR circuit 45 connected to the polysilicon gate 18 or an OR circuit 45
The second input terminal side resistor R ₁ or the like connected to the R circuit 45 is not necessarily monolithic, need not be mounted on the transistor and the same semiconductor substrate (chip). For example, on a ceramic substrate or a resin substrate, by mounting the chip (or a circuit element) equipped with OR circuits 45 and resistor R ₁ and the like, may be in the configuration of a hybrid integrated circuit. In other words, assuming that the semiconductor integrated circuit of the present invention is narrowly defined as a monolithic integrated circuit, the above-mentioned “semiconductor integrated circuit equipped with an active clamp circuit” is referred to as a “monolithic integrated circuit equipped with at least a part of an active clamp circuit”. It should be noted that it can be understood as "a semiconductor integrated circuit". However, it may be more appropriate to interpret the invention as a "broader integrated circuit" that includes these hybrid integrated circuits.

In the first embodiment of the present invention, the p-type impurity is additionally introduced into the second p-base region 7 with the second dose Φ _PBA2 by ion implantation or the like, so that the first dose Φ _PBA The impurity density of the second p base region (PBA + PBA2) 7 serving as the anode region of the constant voltage diode 44 is increased with respect to the impurity density of the first p base region (PBA) region 4 into which the p-type impurity is introduced. ing.
The drain-source breakdown voltage BVdss of the transistor is determined by the impurity density and thickness of the n-well 3 serving as a drift region,
It is determined by the impurity density and the thickness of the first p base region (PBA) 4. Qualitatively, when the impurity density is low or the region is thick, the drain-source breakdown voltage BVdss increases, and when the impurity density is high or the region is thin, the breakdown voltage BVdss decreases. On the other hand, the constant voltage diode 4
4, the reverse breakdown voltage Vr depends on the impurity density and thickness of the n-well 3 serving as the cathode region, and the second
And the impurity density and thickness of the p base region (PBA + PBA2) 7. Qualitatively, the reverse breakdown voltage Vr is high when the impurity density is low or the region is thick, and the reverse breakdown voltage Vr is low when the impurity density is high or the region is thin.

In the first embodiment, since the drain region of the lateral power MOS and the n-well 3 of the cathode region of the constant voltage diode 44 are common, both have the same impurity density and thickness. Then, as can be understood from the description of the manufacturing method described later, the first p base region (PBA)
At the same time, a p-type impurity is introduced into the region where the second p-base region is to be formed by the first dose Φ _PBA , and then a predetermined impurity corresponding to the second dose Φ _{PBA2 is added} to the second p-base _region. By selectively additionally introducing only the region where the region is to be formed, the impurity density of the second p base region is increased by the amount of the second dose Φ _PBA2 . Thereafter, if both p bases 4 and 7 are driven in at the same time, the thickness (diffusion depth) becomes substantially the same.

By setting the impurity density as described above, the drain-source breakdown voltage B of the lateral power MOS can be set.
When Vdss is compared with the reverse breakdown voltage Vr of the constant voltage diode 44, the drain-source breakdown voltage BVdss of the lateral power MOS always becomes larger than the reverse breakdown voltage Vr as shown in Expression (9).

Further, in the first embodiment of the present invention, the difference between the drain-source breakdown voltage BVdss of the lateral power MOS and the reverse breakdown voltage Vr is equal to or higher than the threshold voltage Vth of the OR circuit 45. 2 p base region (PB
A + PBA2) 7 is set as the impurity density. Accordingly, the drain-source voltage Vds of the lateral power MOS becomes (drain-source breakdown voltage BVdss)-(O
When an attempt is made to make a state transition to the threshold voltage Vth) of the R circuit 45, the constant voltage diode 44 turns on. As a result, when the drain-source voltage Vds rises to the breakdown voltage BVdss, the OR circuit 45 outputs a logic signal “1” and causes the lateral power MOS to transition to the conductive state. In response, the drain-source voltage Vds is clamped, so that the voltage does not further rise. As a result, the lateral power MOS can be prevented from being destroyed due to overvoltage.

Here, the drain-source breakdown voltage BVdss
And the variation of the reverse breakdown voltage Vr. As described above, the breakdown voltage BVdss depends on the impurity density and thickness of the n-well 3 serving as the drift region and the first p-base region (P
BA) 4 is determined by the impurity density and thickness. on the other hand,
The reverse breakdown voltage Vr of the constant voltage diode 44 is determined by the impurity density and the thickness of the n-well 3 serving as a cathode region. In the first embodiment, the lateral power MO
S and the constant voltage diode 44 are both elements formed by a diffusion process. Therefore, the manufacturing method of both devices is almost the same, and one electrode of each device is a common electrode. Further, the other electrode is also arranged in close proximity, and the steps other than the step of implanting additional ions to shift the reverse breakdown voltage of both electrodes by the threshold voltage Vth (= 2.5 V) of the OR circuit 45 are common steps. . As a result, a correlation is established between the relative variation between the drain-source breakdown voltage BVdss and the reverse breakdown voltage Vr, and the relative variation can be essentially reduced.

Next, assuming the worst case, consider the case where the clamp voltage is maintained at 37 V or more. In this case, if the minimum value of the reverse breakdown voltage is Vr (min), the drain-source voltage Vds (min) is as follows: Vds (min) = 37V <Vth + Vr (min)... 10) When Vth = 2.5 V, the minimum value Vr (min) of the reverse breakdown voltage is Vr (min)> 34.5 V. on the other hand,
When the reverse breakdown voltage is at the minimum value Vr (min) and the drain-source breakdown voltage BVdss of the lateral power MOS
Even in the case of (min), it is necessary to satisfy Vds <BVdss.

The absolute variation of the reverse breakdown voltage Vr is ± 1.
Assuming that the relative variation between the drain-source breakdown voltage BVdss and the reverse breakdown voltage Vr is ± 5%, the drain-source voltage Vds is: Vds = Vth + Vr (min) = 2.5 + 34.5 = 37V ... (11) That is, when the relative variation of BVdss when the reverse breakdown voltage Vr is minimum is minimum, BVdss> 37V
Should be satisfied. Therefore, when the reverse breakdown voltage Vr is the center value, the center value of the drain-source breakdown voltage BVdss is: BVdss (typ) = 37 ÷ 0.9 ÷ 0.95 = 43.3 V (43.3 V) 12)

Further, even when the reverse breakdown voltage Vr (max) and the drain-source breakdown voltage BVdss (min), Vds <BVdss must be satisfied. That is,
The reverse breakdown voltage Vr (typ) is as follows: Vr (typ) = 37 ÷ 0.9 = 41.1V (13) Further, the reverse breakdown voltage Vr (max) is as follows: Vr (max) = 41.1 · 1.1 = 45.2V (14) That is, Vds = Vth + Vr (max) = 2.5 + 45.2 = 47.7 V (15)

Thus, when the relative variation in the drain-source breakdown voltage BVdss when the reverse breakdown voltage Vr is maximum is minimum, the drain-source breakdown voltage BVdss> 47.
What is necessary is that 7 V is established. Therefore, when the reverse breakdown voltage Vr is the center value, the center value of the drain-source breakdown voltage BVdss is: BVdss (typ) = 47.7 ÷ 1.1 ÷ 0.95 = 45.7V・ (16) Since the value is larger than the previous 43.3V, 45.7
V is the required breakdown voltage under center conditions.

That is, the same operation range can be ensured even with a lateral power MOS having a withstand voltage lower by about 20% than the withstand voltage of the power MOS of 54.4 V shown in the conventional example. Generally, the withstand voltage of the power MOS and the on-resistance per unit area are in an opposite relationship. That is, if a transistor with a lower breakdown voltage can be used, for example, the thickness of the drift region can be reduced, so that the thickness of the n-well can be reduced and the on-resistance per unit area can be reduced. As a result, if the chip area is the same, a larger current can flow, and if the current value is the same, the chip area can be reduced.
That is, it is not necessary to increase the area of the transistor more than is originally required. By reducing the chip area, the cost of the semiconductor integrated circuit can be reduced.

Next, a method of manufacturing a semiconductor integrated circuit according to the first embodiment of the present invention will be described.

(A) Impurity density 1 × 10 ¹⁴ cm ^{-3 to} 2 ×
A p substrate 1 of about 10 ¹⁸ cm ⁻³ is prepared. By thermal oxidation
A first oxide film having a thickness of 350 nm to 1 μm is formed on a p-substrate 1, and a diffusion window is opened in the first oxide film. An n-type impurity is selectively introduced from the diffusion window. For example, antimony ion (Sb ⁺ ) is used as an n-type impurity at an acceleration energy of about 50 to 150 KeV and a dose of about 3 × 1.
Ion implantation is performed under conditions of 0 ^{15 to} 3 × 10 ¹⁶ cm ⁻² , and thermal diffusion is performed at a substrate temperature of about 1100 ° C. to 1200 ° C. for a predetermined time to form an n-diffusion layer (NBL) 2. Then the first
The oxide film is removed, and a p epitaxial growth layer 11 having a thickness of 10 μm to 100 μm is grown on the p substrate 1 by vapor phase epitaxial growth. At this time, in the vapor phase epitaxial growth, monosilane (SiH ₄ ), dichlorosilane (SiH ₂ Cl ₂ ), and trichlorosilane (Si
HCl ₃ ) or silicon tetrachloride (SiCl ₄ ) at a substrate temperature of 1 using hydrogen (H ₂ ) or the like as a carrier gas.
The growth may be performed at 050 ° C. to 1250 ° C. In order to form a p-type semiconductor region, a predetermined amount of a dopant gas such as a gas containing a small amount of diborane (B ₂ H ₆ ) may be added during growth by controlling the gas in a predetermined amount by a mass flow controller or the like. Alternatively, it may be grown using a liquid source such as trichlorosilane (SiHCl ₃ ) containing a small amount of boron (B) as a dopant, such as silicon tetrachloride (SiCl ₄ ).

(B) Next, a second oxide film having a thickness of 350 nm to 1 μm is formed on the p epitaxial growth layer 11. Then, a diffusion window is opened in the second oxide film, and an n-type impurity for forming an n-type semiconductor region (NWL) 3 is introduced from the diffusion window. For example, after forming this diffusion mask, ions of phosphorus ions (P ⁺ ) are selectively implanted under the conditions of an acceleration energy of about 100 KeV to 2 MeV and a dose of about 5 × 10 ^{12 to} 5 × 10 ¹³ cm ⁻² . Heat treatment (drive-in) is performed at a substrate temperature of about 1100 ° C. to 1200 ° C. for a predetermined diffusion time. This diffusion time may be determined in consideration of the thickness of the p epitaxial growth layer 11. As a result, the bottom of n well region (NWL) 3 reaches n buried layer (NBL) 2. In addition, n sinker (NS
In the case where K) 9 is formed of n diffusion regions, a diffusion mask is similarly formed for n sinker (NSK) 9 before diffusion (drive-in) of n well region (NWL) 3 and phosphorus ions (P It is necessary to selectively implant an n-type impurity ion such as ⁺ ) into a region where a drain cell is to be formed. The conditions of this ion implantation are, for example, acceleration energy: about 100 KeV to 2 MeV, and dose: about 5 × 1.
0 ^{15 to} 5 × 10 ¹⁶ cm ⁻² . By doing so, the heat treatment (drive-in) for a predetermined diffusion time allows the n sinker (N) to be formed simultaneously with the bottom of the n well region (NWL) 3.
SK) 9 reaches n buried layer (NBL) 2. Thus, the n buried layer 2 is an n well (NWL)
It is formed at a position sandwiched between the region 3 and the p substrate 1.

(C) Next, a third oxide film having a thickness of 350 nm to 1 μm is formed on the entire surface of the p epitaxial growth layer 11 on which the n-well (NWL) region 3 is formed. Then, a diffusion window is opened in the third oxide film by using a photolithography technique, and an intermediate stage region between the first p base region (PBA) 4 and the second p base region is formed from the diffusion window. _Is introduced at a first dose Φ _PBA . For example, boron ions (B ⁺ ) as p-type impurities are accelerated at an energy of about 30 to 100 KeV,
First dose amount Φ _PBA : about 1 × 10 ^{13 to} 5 × 10 ¹⁴ cm
Ion implantation is performed under the condition of ^-2 . Next, the top of the first p base region (PBA) 4 is covered with a photoresist,
Dose Φ _{PBA2 in} the intermediate stage region of the p base region
Of p-type impurities are additionally introduced. For example, boron ions (B ⁺ ) as p-type impurities are accelerated at an energy of about 30 to _{100 KeV, and a} second dose Φ _{PBA2 is} about 5 × 10 ¹²
The ion implantation is performed under the condition of about 2 × 10 ¹⁴ cm ⁻² . Thereafter, thermal diffusion is performed at a substrate temperature of about 1050 ° C. to 1200 ° C. for a predetermined time, and a predetermined depth, for example, a depth of 1 μm to 2 μm.
A first p base region (PBA) 4 of about 0 μm and a second
To form a p base region (PBA + PBA2) 7. Note that the first and second dose amounts here are merely examples, and are specifically determined by individual design specifications.
That is, what is the drain-source breakdown voltage BVdss of the lateral power MOS, and how much the constant voltage diode 44
The reverse breakdown voltage Vr may be determined.

(D) The photoresist used for the additional ion implantation for the second dose amount _ΦPBA2 is removed, and the diffusion window formed in the third oxide film is used for forming the first p base. A part (peripheral portion) of the diffused window is further covered with a new photoresist, and p-type impurities for forming the anode contact region 8 and the base contact region 6 are introduced. For example, boron ions (B ⁺ ) as p-type impurities
The ion implantation is performed under the conditions of an acceleration energy of about 20 to 50 KeV and a dose of about 1 × 10 ^{15 to} 5 × 10 ¹⁶ cm ⁻² . Thereafter, heat treatment is performed at a substrate temperature of about 800 ° C. to 900 ° C. for a predetermined time.

(E) After the third oxide film is removed, and after predetermined cleaning for removing heavy metals and the like, gate oxidation is performed to form a gate insulating film (a fourth insulating film) having a thickness of 30 nm to 150 nm.
An oxide film). The gate oxidation may be dry oxidation, wet oxidation by burning hydrogen (H ₂ ), or may be performed by mixing hydrochloric acid (HCl) during dry oxidation. Thereafter, polycrystalline silicon is deposited on the entire surface of the gate insulating film by low pressure CVD or normal pressure CVD. This low pressure CVD
Alternatively, n-doped polysilicon may be directly deposited by using an n-type dopant gas containing phosphine (PH ₃ ) or the like during normal pressure CVD. Then, using a photolithography technique and reactive ion etching (RIE), patterning is performed in the shape of the polysilicide 18.

(F) A fifth oxide film is deposited on the polysilicon 18 by low pressure CVD or normal pressure CVD. And
Using photolithography technology and RIE, the upper portion of the sinker (NSK) 9 and the first p base region (PB
A) Open a diffusion window at the top of 4. At this time, the fifth oxide film is left in the center of the first p base region (PBA) 4. This is for making the planar shape of the source region 5 a donut shape. Then, a diffusion window having an area larger than that of the first p base region (PBA) 4 is opened so that the polysilicon 18 is also exposed. An n-type impurity for forming the n source region 5 and the sinker contact region 10 is introduced from the diffusion window. Arsenic ions (As ⁺ ) are used as n-type impurity ions at an acceleration energy of about 30 to 8
0 KeV, dose amount: about 1 × 10 ^{15 to} 4 × 10 ¹⁶ cm ⁻²
Ion implantation is performed under the conditions of
Thermal diffusion is performed at 000 ° C for a predetermined time. In order to form the n source region 5 shallowly, rapid annealing (RTA) may be performed using an infrared (IR) lamp.

(G) Thereafter, the first interlayer insulating film 3 is formed on the entire surface.
1 is formed by a CVD method or the like. Then, an anode contact hole, a sinker contact hole, and a source contact hole are opened in the first interlayer insulating film 31 by using a photolithography technique. After opening contact holes, doped polysilicon, tungsten (W),
Refractory metals such as titanium (Ti) and molybdenum (Mo);
These refractory metal silicide sides (WSi ₂ , TiS
i ₂ , MoSi ₂ ), or a polycide using these silicides is deposited by a CVD method, a sputtering method, or a vacuum evaporation method such as electron beam (EB) evaporation. Then, the contact plugs 12, 13, 1 as shown in FIG.
4 is patterned. Further, an oxide film (NSG film) and a PS film are formed on the contact plugs 12, 13, and 14.
A second interlayer insulating film 32 made of a G film, a BPSG film, or a composite film thereof is deposited by a CVD method. Thereafter, by heating at a temperature of 850 ° C. to 950 ° C., a heat flow (reflow) is generated, and a highly uneven portion of the second interlayer insulating film 32 is flattened. In some cases, the surface may be flattened by chemical mechanical polishing (CMP). afterwards,
A contact hole is opened in the second interlayer insulating film 32 by photolithography and RIE. further,
Al such as Al-Si, Al-Cu, Al-Si-Cu by sputtering or vacuum evaporation such as EB evaporation
Deposit the alloy. Then, the Al wirings 15, 16, and 17 are patterned by photolithography and RIE (see FIG. 1). On this, NSG film, PSG
If a final passivation film 33 such as a film, a BPSG film, a silicon nitride film (Si ₃ N ₄ film), or a polyimide film is deposited, the semiconductor integrated circuit according to the first embodiment of the present invention is completed.

The above manufacturing method is an example. Accordingly, the dose Φ
_This has been described above by paying attention to the step of introducing the additional p-type impurity for _PBA2 to form the first p-base region (PBA) 4 and the second p-base region (PBA + PBA2) 7 having different impurity densities. It goes without saying that various conventionally known methods other than the method can be adopted. In order to form the first p base region (PBA) 4 to have a greater diffusion depth than the second p base region (PBA + PBA 2) 7, first,
First, a first p base region (PBA) is formed in a third oxide film.
4 is opened only to form a diffusion window for forming the first p base region (PBA) 4 from the diffusion window.
Type impurities are introduced (ion implantation) and the substrate temperature is about 900 ° C
Thermal diffusion is performed at a temperature of 1150 ° C. for a predetermined time. Then, this time, the second p base region (PBA + P
A diffusion window for forming BA2) 7 is opened, and a p-type impurity for forming second p base region (PBA + PBA2) 7 is introduced (ion implantation) from the diffusion window. After this, the substrate temperature is about 1050 ° C. to 1200 ° C.
By performing the thermal diffusion for a predetermined time, the first p base region (PBA) 4 and the second p base region (PBA) 4 having different depths are obtained.
+ PBA2) 7 can be formed.

As described above, according to the first embodiment of the present invention, both the lateral power MOS and the constant voltage diode can be formed by the diffusion process for the same n-well (NWL) region 3. In a certain case, the heat treatment step can be the same. That is, the first p base region (P
BA) 4 and second p base region (PBA + PBA2)
The manufacturing process of the two devices (lateral power MOS and constant voltage diode) using the same can be made substantially common. As a result, the drain of the lateral power MOS
Correlation is established between the relative variation between the source breakdown voltage BVdss and the reverse breakdown voltage Vr of the constant voltage diode, and the relative variation can be essentially reduced. As a result, it is not necessary to increase the area of the lateral power MOS, and the chip area of the semiconductor integrated circuit can be reduced and the integration density can be increased.

(Second Embodiment) FIG. 3 is a sectional structural view of a semiconductor integrated circuit mounted with an active clamp circuit according to a second embodiment of the present invention. A circuit diagram of a main part of the active clamp circuit according to the second embodiment is shown in FIG.
It is the same as the circuit diagram shown in FIG. 2 described in the embodiment,
The structure of the transistor to be protected from surge voltage is different. That is, in the semiconductor integrated circuit according to the second embodiment of the present invention, as an example of the transistor, an n-channel trench gate power MOS transistor (hereinafter, simply referred to as a “trench
Power MOS ". ) Will be described.

As shown in FIG. 3, the semiconductor integrated circuit having the active clamp circuit according to the second embodiment of the present invention has an n-well (NWL) 3 as an n-type semiconductor region.
And a first element disposed inside the n-well (NWL) 3.
P base region (PBA) 4 and second p base region (PBA + PBA 2) 7 and first p base region (PB)
A) an n-type source region 5 disposed on the surface of
, A p-type anode contact region 8 disposed on the surface of the p base region (PBA + PBA2) 7, a first p base region (PBA) 4 and a second p base region (PBA +
An N-type drain / cathode region (n-buried region: NBL) 2 disposed below the PBA 2) 7 and a first p-base region (PBA) 4 are disposed near the first p-type region.
A gate structure 18 for controlling a current flowing through the base region (PBA) 4. n-well (NWL) 3
Is a p-epitaxial growth layer (p-epi layer) 11 formed over the p-substrate 1 via the buried region (NBL) 2
Are formed selectively inside the. The p-type anode contact region 8 is formed in the second p base region (PBA + PBA
2) If the impurity density of 7 is sufficiently high, it can be omitted. The gate structure includes a groove formed from the surface of the first p base region (PBA) 4 toward the bottom thereof, a gate insulating film formed on a side wall of the groove, and a control electrode 18 embedded in the groove. At least. The shape of the groove is not limited to the U-shaped groove shown in FIG. 3, but may be a V-shaped groove or an inverted mesa-shaped groove.
The control electrode 18 is a polysilicon made of a doped polysilicon film. The anode contact region 8 is a region having a higher impurity density than the second p base region (PBA + PBA2) 7. Since the drain / cathode region 2 is formed as a buried region (NBL), an n-type lead region (sinker) 9 reaching the drain / cathode region (NBL) 2 from the surface of the n-well (NWL) 3 is formed. I have more. First p base region (PB
A) Inside of 4, a first p base region (PB
A) A base contact region 6 having a higher impurity density than 4 is formed. The source region 5 and the base contact region 6 of the trench power MOS are connected to each other by using an aluminum wiring 15 via a contact plug 12 to form a source electrode. Anode contact area 8
Are connected to the aluminum wiring 16 via the contact plug 14 to form an anode electrode. Further, the aluminum wiring 17 serving as the drain / cathode electrode is connected to the contact plug 13 via a contact hole opened in the second interlayer insulating film 32. The contact plugs 12, 13 and 14 are made of a high melting point metal such as doped polysilicon or tungsten (W), titanium (Ti), molybdenum (Mo) or the like embedded in a contact hole opened in the first interlayer insulating film 31. What is necessary is just to comprise. Alternatively, these refractory metal silicides (WSi ₂ , Ti
Si ₂ , MoSi ₂ ) or polycide using these silicides may be embedded. The aluminum wiring 16 is connected to the contact plug 14 via a contact hole opened in the second interlayer insulating film 32. Aluminum wiring 1
A passivation film 33 is deposited on 5, 16, 17 and the second interlayer insulating film 32. However, the metal wiring structure shown in the cross-sectional view of FIG. 3 is an example, and the contact plugs 12, 13, and 14 are omitted, and the aluminum wiring 15, 1
It is possible to make ohmic contacts 6 and 17 directly to the semiconductor region. In FIG. 3, the aluminum wirings 15, 1
Although the structure is shown in which the metal wirings 6 and 17 have the same metal wiring level, the aluminum wiring 15 is provided in the first layer, and the aluminum wirings 16 and 17 in the second layer are formed via an interlayer insulating film thereover. Needless to say, the multi-layer wiring structure described above can be adopted.

In this semiconductor integrated circuit, the reverse breakdown voltage Vr of the diode 44 (see FIG. 2) formed between the anode contact region 8 and the drain / cathode region 2 is used.
Is a power MOS 42 comprising a drain / cathode combined region (NBL) 2, a gate structure 18 and a source region 5.
It is lower than the drain-source breakdown voltage BVdss of FIG.

As can be understood by referring to FIG. 2, the drain / cathode region (NBL) 2 is connected to the load element 43 through the n sinker (NSK) 9 and the aluminum wiring 17 serving as the drain / cathode electrode. Is electrically connected to Source region 5 is grounded via aluminum wiring 15. A control signal is input to the buried doped polysilicon gate electrode 18 constituting the trench gate structure via an OR circuit 45. Where this OR
The circuit 45 has at least first and second input terminals, a control signal is input to the first input terminal, and the anode contact region 8 is connected to the second input terminal. A second input terminal of the OR circuit 45, the resistor R ₁ which is grounded and the other end as shown in FIG. 2 are connected. A typical inductive load 43 is a load element connected to the common drain / cathode region (NBL) 2. However, the load element 43 shown in FIG. 2 may be a load element connected outside the semiconductor integrated circuit. Further, the OR circuit 45 is connected to Porishirigeto 18 or resistor R ₁ or the like connected to the second input terminal of the OR circuit 45 does not necessarily need to be mounted on the same semiconductor substrate (chip) monolithically. For example, on a ceramic substrate or a resin substrate, by mounting the chip (or a circuit element) equipped with OR circuits 45 and resistor R ₁ and the like, may be in the configuration of a hybrid integrated circuit.

The second p-base region is located at an intermediate stage region.
The p-type impurity is additionally introduced by ion implantation or the like at a dose Φ _PBA2 of
A) For the impurity density of 4, the second p base region (PBA + PB) serving as the anode region of the constant voltage diode 44
A2) The impurity density of 7 can be increased. In the second embodiment of the present invention, the n-well 3 in the drain region of the trench power MOS and the cathode region of the constant voltage diode 44 is used.
Is a common region, and both have the same impurity density and thickness. On the other hand, the impurity density of the anode region (PBA + PBA2) 7 of the constant voltage diode 44 is made higher than that of the first p base region (PBA) 4 of the trench power MOS. That is, as described in the first embodiment, simultaneously with the first p base region (PBA) 4, the impurity is first added to the intermediate stage region of the second p base region by the first dose Φ _PBA. After the introduction of the first p base region (P
If only the diffusion window of BA) 4 is closed and a predetermined impurity corresponding to the second dose Φ _PBA2 is selectively additionally introduced only into the intermediate stage region side of the second p base region, this second The impurity density of the second p base region (PBA + PBA2) 7 is increased by the dose amount Φ _PBA2 of 2. Thereafter, if both p bases are driven in at the same time, the thickness (diffusion depth) becomes substantially the same. Thus, when the drain-source breakdown voltage BVdss of the trench power MOS is compared with the reverse breakdown voltage Vr of the constant voltage diode 44, the trench power M is always calculated as shown in equation (9).
The drain-source breakdown voltage BVdss of the OS can be made higher than the reverse breakdown voltage Vr.

As in the first embodiment, in the second embodiment of the present invention, the difference between the drain-source breakdown voltage BVdss of the trench power MOS and the reverse breakdown voltage Vr is determined by the OR circuit 45. The impurity density of the second p base region (PBA + PBA2) 7 is set to be equal to or higher than the threshold voltage Vth. In response, trench power MO
When the voltage Vds between the drain and source of S attempts to make a state transition to (drain-source breakdown voltage BVdss)-(threshold voltage Vth of the OR circuit 45), the constant voltage diode 44 turns on. As a result, as in the first embodiment, when the drain-source voltage Vds rises to the breakdown voltage BVdss, the OR circuit 45 outputs a logic signal “1” and makes the trench power MOS transition to the conductive state. In response, the drain-source voltage Vds is clamped, so that the voltage does not further rise. As a result, destruction of the trench power MOS due to overvoltage can be prevented.

Hereinafter, the consideration of the variation is the same as that of the first embodiment, and there is no problem even if the breakdown voltage of the trench power MOS is reduced by the reduced variation. In other words, a trench power MOS with a lower breakdown voltage
However, a similar operation range can be secured. As a result, the thickness of the drift region can be reduced. That is, since the thickness of the n-well can be reduced, the on-resistance per unit area can be reduced. As a result, a larger current can flow if the chip area is the same, and the chip area can be further reduced if the current value is the same. Therefore, the second aspect of the present invention
According to the embodiment, it is not necessary to increase the area of the transistor more than originally required. By reducing the area occupied by the transistors, the chip can be downsized, and the cost of the semiconductor integrated circuit can be reduced.

Next, the method for manufacturing a semiconductor integrated circuit according to the second embodiment of the present invention includes steps common to the method for manufacturing a semiconductor integrated circuit according to the first embodiment. That is, an n diffusion layer (NBL) 2 is formed on a p substrate 1, a p epitaxial growth layer 11 is formed on the p substrate 1, and an n well region (NWL) 3 and an n sinker (NSK) are formed in the p epitaxial growth layer 11. 9), and further, a first p base region (PBA) 4 and a second p base region (PBA + PBA).
2) Up to the point where 7 is formed, it may be the same as the method of manufacturing the semiconductor integrated circuit according to the first embodiment. Thereafter, (a) a photoresist film is applied to the entire surface, and a diffusion window is opened above the sinker (NSK) 9 and above the first p base region (PBA) 4 by using a photolithography technique. The third oxide film on the sinker (NSK) 9 is removed by etching. On the other hand, the first p base region (PB
A) The photoresist film is left in a plurality of islands inside 4. This is for making the planar shape of the source region 5 a donut shape. An n-type impurity for forming the n source region 5 and the sinker contact region 10 is introduced from the diffusion window. Since the n source region 5 is formed in a very shallow region, arsenic ions (As ⁺ ) having a small diffusion coefficient are used as n-type impurities at an acceleration energy of about 30 to 80 KeV and a dose of about 1 × 10 ^{15 to} 4 ×. 10 ¹⁶
Ion implantation is performed under the condition of cm ⁻² , and thermal diffusion is performed at a substrate temperature of about 800 ° C. to 1000 ° C. for a predetermined time.

(B) It is preferable to use an oxide film as an etching mask for forming a trench (trench) having a large aspect ratio as shown in FIG. For this reason,
The third oxide film is removed, and a fourth oxide film (cover film) is formed on the entire surface above the p epitaxial growth layer 11. The thickness of the fourth oxide film (cover film) may be determined in consideration of the depth of the trench and the etching selectivity between silicon and the oxide film. And, using photolithography technology,
The cover film is patterned into a shape corresponding to the pattern of the U-shaped gate portion. This patterning of the cover film may be performed by RIE using a photoresist as a mask. Then, the photoresist used for patterning the cover film is removed,
Silicon is anisotropically etched using the exposed cover film as a mask. Since the trench has a high aspect ratio, the anisotropic etching of silicon is performed by a mixed gas of SiCl ₄ and chlorine (Cl ₂ ), boron trichloride (BCl ₃ ) and C
RIE or ECR ion etching (or microwave plasma etching) using a mixed gas with l ₂ or sulfur fluoride (SF ₆ ) may be used. When performing anisotropic etching such as RIE or ECR ion etching, use of a side wall protective film or reducing the temperature of the substrate by -30.
By using a low-temperature control process at a temperature of from −140 ° C. to −140 ° C., the sidewalls of the trench can be machined vertically. As a result, as shown in FIG. 3, the first p base region (PBA)
4 is divided into four in the cross section, and a trench is formed between the two divided first p base regions (PBA) 4. The n source region 5 is separated and exposed above the sidewall of each trench by etching the trench.

(C) A thin oxide film (sacrificial oxide film) is formed on the side wall of the trench, and the sacrificial oxide film is removed. This process of forming and removing the sacrificial oxide film is performed when there is a concern about damage due to excessive discharge energy at the time of etching the trench, or when there is a concern about contamination of the sidewall of the trench with a heavy metal or an etching gas component. Yes, and can be omitted in some cases. In any case, after cleaning the side wall of the trench, gate oxidation is performed to form a U-type gate insulating film having a thickness of 30 nm to 150 nm as shown in FIG. The gate oxidation may be dry oxidation, wet oxidation by burning hydrogen (H ₂ ), or may be performed by mixing hydrochloric acid (HCl) during dry oxidation. (D) As shown in FIG. 3, a control electrode (U-type gate electrode) 18 is formed by burying n-type polycrystalline silicon (n ⁺ doped polysilicon) in the trench. n
⁺ Doped polysilicon is formed by depositing polysilicon to which impurities are not added by low-pressure CVD or normal pressure CVD, and then introducing n-type impurities such as vapor phase diffusion (predeposition) using phosphorus oxychloride (POCl ₃ ). Can be formed. Instead of gas phase diffusion (predeposition), ion implantation of n-type impurity ions such as P and As may be used. Alternatively, a phosphine (P
It is also possible to directly deposit n ⁺ -doped polysilicon using an n-type dopant gas containing H ₃ ) or the like. FIG.
As shown in the figure, in order to embed n ⁺ doped polysilicon in the U groove, after CVD of n ⁺ doped polysilicon,
What is necessary is just to etch back the surface. Alternatively, the surface may be planarized using CMP, and n ⁺ -doped polysilicon may be embedded in the trench.

(E) Thereafter, the first interlayer insulating film 3 is formed on the entire surface.
1 is formed by a CVD method or the like, but the subsequent steps are the same as the steps (g) and thereafter of the first embodiment, and therefore the description thereof is omitted.

As described above, according to the manufacturing method of the second embodiment of the present invention, both the trench power MOS and the constant voltage diode can be formed in the same n-well (NWL) region 3 by the diffusion process. I can do it. In a certain case, the heat treatment step can be the same. That is, the first p base region (PBA) 4 and the second p base region (PBA)
BA + PBA2) 7 can be used in substantially the same manufacturing process for two devices (trench power MOS and constant voltage diode). As a result, a correlation is established between the relative variation between the drain-source breakdown voltage BVdss of the trench power MOS and the reverse breakdown voltage Vr of the constant voltage diode, and the relative variation can be essentially reduced. As a result, the trench power M
It is not necessary to increase the area of the OS, so that the chip area of the semiconductor integrated circuit can be reduced and the integration density can be increased.

(Third Embodiment) FIG. 4 is a sectional structural view of a main part constituting a semiconductor integrated circuit having an active clamp circuit according to a third embodiment of the present invention. The circuit diagram of the main part of this active clamp circuit is the same as the circuit diagram shown in FIG.

As an example of the power MOS transistor S42 shown in the circuit of FIG.
In the description of the embodiment, “vertical power MOS”
Abbreviated. ) Will be described.

As shown in FIG. 4, a semiconductor integrated circuit having an active clamp circuit according to the third embodiment of the present invention has an n-type epitaxial growth layer 3 as an n-type semiconductor region, and an inside of the n-type epitaxial growth layer 3. The first p base region (PBA) 4 and the second p base region (PBA + PBA 2) 7 arranged, and the n-type source region 5 arranged on the surface of the first p base region (PBA) 4
A p-type anode contact region 8 disposed on the surface of the second p base region (PBA + PBA2) 7;
N-type drain / cathode region (n-substrate) 21 disposed below the p base region (PBA) 4 and the second p base region (PBA + PBA 2) 7, and the first p base region (PBA) 4 And a gate structure 18 for controlling a current flowing through the first p-base (PBA) region 4. The p-type anode contact region 8 includes a second p-base region (PBA + PBA2) 7
Can be omitted if the impurity density is sufficiently high. The gate structure includes at least a gate insulating film formed on the surface of the first p base region (PBA) 4 and a control electrode 18 formed on the gate insulating film. The control electrode 18 is a polysilicon made of a doped polysilicon film. The anode contact region 8 has the second p
The p region has a higher impurity density than the base region (PBA + PBA2) 7. Since the drain / cathode region is formed on the back surface side of the semiconductor substrate 21, the metal electrode (drain / cathode electrode) 39 is connected to the drain / cathode region 21 so as to make ohmic contact.
Inside the first p base region (PBA) 4, a base contact region 6 having a higher impurity density than that of the first p base region (PBA) 4 is further formed. Vertical power M
The source region 5 of the OS and the base contact region 6 are connected to each other using the aluminum wiring 15 via the contact plug 12 to form a source electrode. The anode contact region 8 is connected to the aluminum wiring 16 via the contact plug 14 to form an anode electrode. The contact plugs 12 and 14 are made of doped polysilicon or a high melting point metal such as tungsten (W), titanium (Ti), molybdenum (Mo) or the like embedded in a contact hole opened in the first interlayer insulating film 31. do it. Alternatively, these refractory metal silicide side (WSi ₂ , T
iSi ₂ , MoSi ₂ ) or polycide using these silicides may be embedded. The aluminum wiring 16 is connected to the contact plug 14 via a contact hole opened in the second interlayer insulating film 32. Aluminum wiring 1
A passivation film 33 is deposited on the layers 5, 16 and the second interlayer insulating film 32. However, the metal wiring structure shown in the cross-sectional view of FIG.
And 14 can be omitted, and the aluminum wirings 15 and 16 can be directly brought into ohmic contact with the semiconductor region. Further, FIG. 4 shows a structure in which the aluminum wirings 15 and 16 are at the same metal wiring layer level. Obviously, a multilayer wiring structure such as forming the aluminum wiring 16 can be adopted.

In this semiconductor integrated circuit, the reverse breakdown voltage V of the diode 44 (see FIG. 2) formed between the anode contact region 8 and the drain / cathode region 21 is set.
r is a vertical power MO including a drain / cathode region (n-substrate) 21, a gate structure 18, and a source region 5.
The drain-source breakdown voltage BVdss of S42 (see FIG. 2)
And has a relationship satisfying the expression (9).

As can be understood with reference to FIG. 2, the drain / cathode region 21 (n-substrate) is electrically connected to the load element 43 via the drain / cathode electrode 39. The source region 5 is grounded via an aluminum wiring 15, and the polysilicon 1 forming the gate structure is formed.
A control signal is input to 8 via an OR circuit 45. Here, the OR circuit 45 has at least first and second input terminals, a control signal is input to the first input terminal, and the anode contact region 8 is connected to the second input terminal. A second input terminal of the OR circuit 45, the resistor R ₁ which is grounded and the other end as shown in FIG. 2 are connected.
A typical inductive load 43 is a load element connected to the drain / cathode shared region (n-substrate) 21.
However, the load element 43 shown in FIG. 2 may be a load element connected outside the semiconductor integrated circuit. Further, the OR circuit 45 is connected to Porishirigeto 18 or resistor R ₁ or the like connected to the second input terminal of the OR circuit 45 does not necessarily need to be mounted on the same semiconductor substrate (chip) monolithically. For example, on a ceramic substrate or a resin substrate, in the form of a so-called hybrid integrated circuit may be mounted to the OR circuit 45 and the resistor R ₁ and the like. For example, in the third embodiment of the present invention, the drain / cathode region (n-substrate) 21 is a metal wiring formed on a ceramic substrate or a lead led to the outside of the package via the drain / cathode electrode 39. And can be connected to the load element 43 via the metal wiring and the lead.

A second dose Φ is applied to the second p base region 7.
_{By performing} additional ion implantation with _PBA2 , the impurity density of the second p-base region (PBA + PBA2) 7 serving as the anode region of the constant voltage diode 44 is reduced with respect to the impurity density of the first p-base region (PBA) region 4. Can be higher. In the third embodiment of the present invention, since the n-epitaxial growth layer 3 constituting the drift region of the vertical power MOS and the cathode region of the constant voltage diode 44 is a common region, both have the same impurity density and thickness. On the other hand, the impurity density of the second p base region (PBA + PBA2) 7 which is the anode region of the constant voltage diode 44 is made higher than that of the first p base region (PBA) 4 of the vertical power MOS. That is, a p-type impurity is first introduced by the first dose Φ _{PBA into} the second p-base region formation planned region simultaneously with the first p-base region (PBA) 4, and then the second p-base region is formed.
_Is selectively introduced additionally only into the second p base region side, the impurity density of the second p base region is increased by the amount of the second dose Φ _PBA2. Will be higher. If both p bases are driven in at the same time, the thickness (diffusion depth) becomes substantially the same. Thus, the drain-source breakdown voltage BV of the vertical power MOS
Comparing dss with the reverse breakdown voltage Vr of the constant voltage diode 44, the vertical power MO
The drain-source breakdown voltage BVdss of S can be made higher than the reverse breakdown voltage Vr.

Further, in the third embodiment of the present invention, the difference between the drain-source breakdown voltage BVdss of the vertical power MOS and the reverse breakdown voltage Vr is equal to or higher than the threshold voltage Vth of the OR circuit 45. The second p base region (PBA +
The impurity density of PBA2) 7 is set. In response,
The constant voltage diode 44 turns on when the drain-source voltage Vds of the vertical power MOS tries to make a state transition to (drain-source breakdown voltage BVdss)-(threshold voltage Vth of the OR circuit 45). As a result, when the drain-source voltage Vds rises to the breakdown voltage BVdss, the OR circuit 45 outputs a logic signal “1” and makes the vertical power MOS transition to the conductive state. In response, the drain-source voltage Vds is clamped, so that the voltage does not further rise. As a result, destruction of the vertical power MOS due to overvoltage can be prevented.

Hereinafter, consideration of the variation is the same as in the first embodiment. As a result, the power M shown in the conventional example
A similar operation range can be ensured even in a vertical power MOS having a lower withstand voltage than the withstand voltage of the OS. If a transistor having a lower breakdown voltage can be used, the thickness of the n-epitaxial growth layer 3 can be reduced, so that the on-resistance per unit area can be reduced. As a result, a larger current can flow if the chip area is the same, and the chip area can be further reduced if the current value is the same. That is, it is not necessary to increase the area of the transistor more than is originally required. By reducing the area occupied by transistors,
The size of the semiconductor integrated circuit chip is reduced, and the cost of the semiconductor integrated circuit can be reduced.

Next, a method of manufacturing a semiconductor integrated circuit according to the third embodiment of the present invention will be described.

(I) First, an n substrate 21 having an impurity density of about 1 × 10 ¹⁸ cm ^{−3 to} 1 × 10 ²¹ cm ⁻³ is prepared. This n
As shown in FIG. 4, an impurity density of 1 × 10 ¹² cm ^{−3 to} 8 × 10 ¹⁵ cm ^{−3 is formed} on the substrate 21 by vapor phase epitaxial growth.
In this case, an n-type epitaxial growth layer 3 having a thickness of 10 μm to 100 μm is grown. Alternatively, in order to realize a vertical power MOS having a high withstand voltage, an impurity density of 6 × 10 ¹¹ cm
^{-3 to} 8 × 10 ¹⁹ cm ^-3 and thickness of 300 μm to 1 m
An n-type substrate is prepared, and an n-type impurity is diffused over the entire back surface of the n-type substrate 3 to obtain an impurity density of 1 × 10 ¹⁸ cm ^{−3 to} 8 × 1.
The drain / cathode region 21 having a depth of about 0 ²⁰ cm ⁻³ and a depth of 5 μm to 30 μm may be formed.

(Ii) The n epitaxial growth layer 3
A first oxide film is formed thereon, and a diffusion window is opened in the first oxide film using photolithography technology, a diffusion window is opened in the first oxide film, and a first p-base is formed from the diffusion window. A p-type impurity for forming an intermediate stage region between the region (PBA) 4 and the second p base region is introduced at a first dose Φ _PBA . Next, the upper part of the first p base region (PBA) 4 is covered with a photoresist, and an additional p-type impurity for the second dose Φ _PBA2 is introduced into the intermediate stage region of the second p base region. Thereafter, the substrate temperature is about 1050 ° C.
At 0 ° C., heat diffusion is performed for a predetermined time, and a predetermined depth, for example,
A first p base region (P) having a depth of about 1 μm to about 20 μm
BA) 4 and second p base region (PBA + PBA2)
7 is the same as the step (c) of the first embodiment in which the gate 7 is formed. In order to form the first p base region (PBA) 4 to have a deeper diffusion depth than the second p base region (PBA + PBA 2) 7, first, the first p base region (PBA + PBA 2) 7 must have the first p base region in the first oxide film. Only the diffusion window for forming the base region (PBA) 4 is opened, and the first p base region (P
A p-type impurity for forming BA) 4 is introduced (ion implantation), and thermal diffusion is performed at a substrate temperature of about 900 ° C. to 1150 ° C. for a predetermined time. Then, the second oxide film is
A diffusion window for forming the p base region (PBA + PBA2) 7 is opened, and a p-type impurity for forming the second p base region (PBA + PBA2) 7 is introduced (ion implantation) from the diffusion window. Thereafter, if thermal diffusion is performed at a substrate temperature of about 1050 ° C. to 1200 ° C. for a predetermined time, a first p base region (PBA) 4 and a second p base region (PBA + PBA 2) 7 having different depths are formed. it can. Since the third embodiment has a vertical structure, the first and second structures are used.
Unlike the embodiment, the step of introducing an n-type impurity for the n-sinker (NSK) 9 is unnecessary.

(Iii) Subsequent steps are substantially the same as the steps after (d) of the first embodiment, and thus duplicated description will be omitted. However, the step of forming the contact plug 13 and the Al wiring 17 in the step (g) of the first embodiment is unnecessary. Instead, finally, a multilayer metal film such as chromium (Cr) nickel (Ni) silver (Ag) is formed on the n-substrate 21.
It is necessary to form a drain / cathode electrode 39 by depositing the film on the back surface by sputtering or vacuum evaporation and performing heat treatment (sintering). Above,
Although the semiconductor integrated circuit according to the third embodiment of the present invention is completed, the drain / cathode electrode 39 may be formed on the back surface of the n-substrate 21 by alloying a Mo plate or a W plate.

As in the first and second embodiments, according to the third embodiment of the present invention relating to the above manufacturing method, both the vertical power MOS and the constant voltage diode can be manufactured in the same heat treatment step. Both the vertical power MOS and the constant voltage diode can be formed by a diffusion process for the same n epitaxial growth layer 3. In a certain case, the heat treatment step can be the same. That is, the first p base region (P
BA) 4 and second p base region (PBA + PBA2)
The manufacturing process of two devices (vertical power MOS and constant voltage diode) using the same can be made substantially common. As a result, the drain-source breakdown voltage BVdss of the vertical power MOS and the reverse breakdown voltage Vr of the constant voltage diode are obtained.
Therefore, a correlation is established with the relative variation with respect to, and the relative variation can be essentially reduced. As a result, it is not necessary to increase the area of the vertical power MOS more than is originally required, so that the chip area of the semiconductor integrated circuit can be reduced and the integration density can be increased.

(Other Embodiments) As described above, the present invention has been described with reference to the first to third embodiments. However, it should be understood that the description and drawings constituting a part of this disclosure limit the present invention. should not do. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

For example, the active clamp circuit of the present invention has a circuit in which a resistor R ₁ (first resistor) having the other end grounded is connected to the second input terminal side of the OR circuit 45 as shown in FIG. It is not limited to the figures. As shown in FIG. 5, a second resistor R ₂ may be further inserted between the second input terminal of the OR circuit 45 and the anode region of the constant voltage diode 44. In this case, the second p base region (PB
Even when the dose [Phi _{PBA 2} of impurity implanted into A + PBA 2) is too large, the drain becomes clamped voltage - source voltage Vds, the second resistor R ₂ and the first value of the resistor R ₁ It can be changed by adjusting. That is,
The reverse breakdown voltage Vr of the diode 44 becomes too small, and the reverse breakdown voltage Vr and the n-type MOS transistor 42
Is the sum of the threshold voltage of Vth and Vth, the drain-source breakdown voltage B
Even if Vr + Vth≪BVdss with respect to Vdss, (17), the clamp voltage Vds is calculated as follows: Vds = Vr + Vth · ((R ₁ + R ₂ ) / R ₁ ) <BVdss (18) Thus, by further inserting the _second resistor R2, the second p base region (PBA +
The degree of freedom in selecting the dose _ΦPBA2 of the impurity to be implanted into PBA2) is increased. That is, if configured as shown in the circuit of FIG. 5, the reverse breakdown voltage Vr of the diode 44 the drain - no longer necessarily be introduced impurity at a dose [Phi _{PBA 2} designed to an optimum value to drop from source breakdown voltage BVdss , Other doses can be employed. For example, C
It is possible to divert a p-type impurity introduction step for a p-well forming a MOS and a p-type impurity introduction step for forming a base region of a bipolar transistor. in this way,
As another p-type impurity introduction step which is indispensable when manufacturing an integrated circuit can be used, the manufacturing cost can be further reduced.

The transistors to be protected by the present invention are not limited to the planar power MOS and the trench gate power MOS shown in the first to third embodiments. That is, the present invention can be applied to other types of transistors as long as the structure can share the n-type semiconductor region essentially serving as the drift region (drain region) and the n-type semiconductor region serving as the cathode of the constant voltage diode.

Further, the n-type semiconductor region, the first and second p-base regions, the n-type source region, or n
The number, position, shape, etc. of the constituent members such as the drain / cathode shared region of the mold are not limited to those described in the above-described first to third embodiments, but may be any numbers, positions, shapes, etc. suitable for carrying out the present invention. can do.

Further, the transistors to be protected in the first to third embodiments of the present invention may be MOSFETs or MOSSITs. By reducing the channel length (gate length) of the MOSFET so that the electric field on the drain side can control the height of the potential barrier provided on the entire surface of the source, MOSSIT is obtained. The potential barrier of the MOSSIT is a saddle point (saddle point) in a two-dimensional space defined by the gate potential and the drain potential, and its height can be controlled by the gate potential and the drain potential.
Therefore, the drain current-drain voltage characteristic of the MOSSIT increases exponentially as in the case of the three-pole type vacuum tube.
In the first to third embodiments, the power MOS transistor has been described. However, the present invention can be applied to a more general insulated gate transistor or a MIS transistor. That is, the gate insulating film is not limited to the silicon oxide film (SiO ₂ ), but the silicon nitride film (Si ₃
Of course, various insulating films such as an N ₄ film), a composite film of a Si ₃ N ₄ film and a SiO ₂ film, or a ferroelectric film such as a BSTO film can be used.

Further, in the first and second embodiments of the present invention, the structure in which the n-sinker 9 is formed from the impurity diffusion region is exemplified. However, a trench is formed in a portion where the n-sinker 9 is to be formed. A highly conductive material may be embedded therein. Examples of the highly conductive material include low-resistance polysilicon (doped polysilicon), high melting point metals such as W, Ti, and Mo, and silicides thereof (WSi ₂ , TiS).
i ₂ , MoSi ₂ ), etc., or polycide using these silicides can be used. With these highly conductive materials, the n-drain / cathode region (n-buried region) 2 and the drain / cathode electrode can be conducted. As a result, the resistance of the n sinker 9 can be reduced, so that the on-resistance of the element can be reduced. Also, since the impurity diffusion region always involves lateral diffusion, it occupies a wide diffusion region and has a low area efficiency. On the other hand, the n-sinker 9 using the trench can reduce the occupied area. Yes, it enables high integration density of elements and reduction in chip size. The n-drain / cathode region 2 may be made of a refractory metal such as W, Ti, or Mo, or a silicide thereof (WSi ₂ , TiSi ₂ , MoSi ₂ ). As a result, the on-resistance can be further reduced.

In the first to third embodiments of the present invention, the element isolation structure has not been described. However, the n-type semiconductor region 3 is surrounded by the p-type semiconductor region and is isolated from other elements and circuits. The structure of "pn junction isolation" may be used,
A structure of “dielectric isolation” may be used. In the latter case, for example, an n-type buried region 2 is locally formed on a p-type semiconductor substrate, an n-type semiconductor region is epitaxially grown thereon, and a trench reaching the semiconductor substrate after the epitaxial growth is formed. What is necessary is just to form in the n-type semiconductor region 3 so as to surround the buried region, and bury the dielectric in this trench. As the dielectric to be embedded in the trench, it is possible to use, for example, semi-insulating polysilicon (SIPOS) to which oxygen is added, in addition to an insulating film such as an oxide film. Further, an SOS structure in which the second main electrode region is formed on the sapphire substrate instead of the semiconductor substrate, or an SIS structure in which the second main electrode region is formed on the semiconductor substrate via the buried insulating film may be employed.

In the first to third embodiments, silicon has been described as a semiconductor material. However, other semiconductor materials such as silicon carbide (SiC) and gallium arsenide (GaAs) can be used. In a structure similar to a HEMT using a heterojunction such as AlGaAs / GaAs, a thin semiconductor layer (AlGaAs) having a wide bandgap has the same function as a gate oxide film (insulating film) of a MOS transistor. This is because a transistor having a structure can be broadly interpreted as an insulated gate transistor. Therefore, the present invention relates to such HEMTs and H
It should be noted that the present invention includes a semiconductor integrated circuit having an EMT-like heterojunction gate structure.
In this case, a trench is formed in the GaAs laminated structure, and a GaAs channel layer and AlGaAs are formed in the trench.
A structure in which a thin-film semiconductor layer is formed and a gate electrode is formed thereon is applicable.

Further, the present invention is suitable for an active clamp circuit for protecting a power semiconductor device having a high voltage of 600 V or more, further, 1 KV or more, but is not necessarily limited to a power semiconductor device. For example, the structure of the active clamp circuit of the present invention can be applied to a small signal element such as a logic integrated circuit.

As described above, the present invention naturally includes various embodiments and the like not described herein. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the claims that are appropriate from the above description.

[Brief description of the drawings]

FIG. 1 is a sectional structural view of a main part of a semiconductor integrated circuit on which an active clamp circuit according to a first embodiment of the present invention is mounted.

FIG. 2 is a circuit diagram of a main part of an active clamp circuit according to first to third embodiments of the present invention.

FIG. 3 is a sectional structural view of a main part of a semiconductor integrated circuit on which an active clamp circuit according to a second embodiment of the present invention is mounted.

FIG. 4 is a sectional structural view of a main part of a semiconductor integrated circuit on which an active clamp circuit according to a third embodiment of the present invention is mounted.

FIG. 5 is a circuit diagram of a main part of an active clamp circuit according to another embodiment of the present invention.

FIG. 6 is a sectional structural view of a semiconductor integrated circuit on which a conventional active clamp circuit is mounted.

FIG. 7 is a circuit diagram of a main part of a conventional active clamp circuit.

[Explanation of symbols]

1: substrate (p substrate) 2: drain / cathode combined region (n buried region: N
BL) 3 ... n-type semiconductor region: n-well region (NWL) or n-epitaxial growth layer 4 ... first p base region (PBA) 5 ... source region 6 ... base contact region 8 ... anode contact region 7 ... second P base region (PBA + PBA2) 9 ... n sinker (NSK) 10 ... sinker contact region 11 ... p epitaxial growth layer (p epi layer) 12,13,14 ... contact plug 15,16,17 ... aluminum wiring 18 ... polysilicon 21 ... n substrate 31 first interlayer insulating film 32 second interlayer insulating film 33 passivation film 39 drain / cathode electrode 41 control input terminal 42 power MOS transistor 43 load element 44, 51 to 57 constant voltage diode 45 ... OR circuit 50 ... buffer 58 ... diodes R ₀ , R ₁ , R ₂ … resistance

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) GB04 GB06 GC07 GC08 GD10 GJ02 GJ03 GJ05 GL02 GL03 GL05 GQ01 GR12 GR13

Claims (11)

[Claims] An n-type semiconductor region; first and second p-base regions disposed inside the semiconductor region; and an n-type source region disposed on a surface of the first p-base region. And n disposed below the first and second p base regions.
A drain / cathode dual-type region, and a gate structure disposed near the first p-base region and controlling a current flowing through the first p-base region, the second p-base region And a reverse breakdown voltage of a diode formed between the drain / cathode region and the drain / cathode region,
A semiconductor integrated circuit, which has a lower breakdown voltage than a drain-source voltage of a transistor having a gate structure and a source region. 2. The drain / cathode combined region is electrically connected to a load element, the source region is grounded,
2. The semiconductor integrated circuit according to claim 1, wherein a control signal is input to the gate structure via an OR circuit having first and second input terminals. 3. The control signal is input to the first input terminal, and the second input terminal and the second p base region are electrically coupled.
A semiconductor integrated circuit as described in the above. 4. A first resistor having the other end grounded is connected to the second input terminal, and a second resistor is connected between the second p base region and the second input terminal. 4. The semiconductor integrated circuit according to claim 2, wherein: 5. The semiconductor integrated circuit according to claim 1, wherein an impurity density of the first p base region is lower than an impurity density of the second p base region. circuit. 6. The diffusion depth of the first p base region is:
5. The semiconductor integrated circuit according to claim 1, wherein the diffusion depth is greater than a diffusion depth of the second p base region. 6. 7. The semiconductor integrated circuit according to claim 5, wherein a geometric shape of the first p base region is similar to a geometric shape of the second p base region. circuit. 8. The drain / cathode combined region is formed as a buried region, and from a surface of the semiconductor region,
8. The semiconductor device according to claim 1, further comprising an n-type lead region reaching the drain / cathode combined region.
The semiconductor integrated circuit according to any one of the above items. 9. The semiconductor device according to claim 1, wherein the drain / cathode region is formed on the back surface of the semiconductor substrate, and a metal electrode is in ohmic contact with the drain / cathode region. 3. The semiconductor integrated circuit according to claim 1. 10. The gate structure includes a groove formed from the surface of the first p base region to the bottom thereof, a gate insulating film formed on a side wall of the groove, and embedded in the groove. And at least one control electrode.
A semiconductor integrated circuit according to the item. 11. A step of depositing an n-type semiconductor region above an n-type drain / cathode combined region, and a first dose in a portion of the surface of the semiconductor region where first and second p-base regions are to be formed. Introducing a p-type impurity by an amount, selectively introducing a p-type impurity by a second dose into a portion where the second p-base region is to be formed, and: Forming a source region by introducing an n-type impurity into the surface of the semiconductor integrated circuit.