JP2003174164A - Vertical mos semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a vertical MOS semiconductor device which can operate at high speed with a low on-voltage and to provide its manufacturing method. <P>SOLUTION: This vertical MOS semiconductor device has a 2nd conductivity type 1st semiconductor region 12 formed below a thick part 3b of a gate insulating film, and a 1st conductivity type 2nd semiconductor region 11 formed in contact with the 1st semiconductor 12. Further, a 2nd conductivity type body region 4 and a 1st conductivity type source region 5 are provided in the 2nd semiconductor area 11 so as to form a channel 6 beneath a thin part 3a of the gate insulating film. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical MOS semiconductor device, and more particularly to a power MOSFET or an insulated gate bipolar transistor (IGBT) and its manufacturing method.

[0002]

2. Description of the Related Art Conventionally, as one of vertical MOS semiconductor devices of this type, a power MOS having a structure shown in a sectional view of FIG.
There is a FET. This MOSFE shown as the first conventional example
In T, N ^- type under the epitaxial layer 1 and the drain region 2 of N ⁺ -type is formed, N ^- -type epitaxial layer 1 gate electrode 7 through the thin gate insulating film 3 is formed on is formed There is. Then, a P-type body region 4 and an N ⁺ -type source region 5 are formed on the surface of the N ⁻ -type epitaxial layer 1 so as to form the channel portion 6 under the gate insulating film 3.

In this type of semiconductor device, low loss is strongly required. For that purpose, it is necessary to achieve both a small voltage drop in the semiconductor device at the time of conduction, that is, a small on-voltage and a high-speed switching. From such a viewpoint, a semiconductor device having a structure as shown in FIGS. 5 and 6 is proposed.

FIG. 5 shows a power MO shown as a second conventional example.
It is sectional drawing of SFET. In FIG. 5, N ^- type under the epitaxial layer 1 and the drain region 2 of N ⁺ -type is formed, N ^- -type epitaxial layer first gate electrode via a gate insulating film 3 thicker part on 7 are formed. Then, the thinned portion 3 of the gate insulating film 3
A P-type body region 4 and an N ⁺ -type source region 5 are formed on the surface of the N ⁻ -type epitaxial layer 1 so as to form the channel portion 6 under a. Further, on the surface of the N ⁻ type epitaxial layer 1, the N type diffusion region 21 is provided with the P type body region 4.
Are formed so as to be in contact with.

As a result, since a part of the gate insulating film 3 is thickened, the gate capacitance is reduced and high speed operation becomes possible. Moreover, the so-called J-FE is formed by the N-type diffusion region 21.
Since the T effect is weakened, it is possible to lower the on-voltage.

FIG. 6 shows an IGBT shown as a third conventional example.
FIG. In FIG. 6, N⁻Type epitaxial layer
Below 1 is an N-type buffer layer 13 and P⁺Type of drain region
Zone 2 is formed, N⁻On the epitaxial layer 1
Is a gate electrode 7 through a gate insulating film 3 which is partially thickened.
Are formed. The gate insulating film 3 is thin
N is formed so that the channel portion 6 is formed under the unfinished portion 3a.⁻
On the surface of the type epitaxial layer 1, a P type body region 4 and N
⁺The mold source region 5 is formed. Furthermore, N ⁻Type d
The surface of the epitaxial layer 1 is sandwiched between P-type body regions 4.
The P-type diffusion region 22 is formed at the separated position, and the P-type diffusion region 22 is formed.
At the position sandwiched between the region 22 and the P-type body region 4, the N-type expansion is performed.
A dispersed area 21 is formed. The P-type diffusion region 22
Is connected to the source potential in a region not shown
It

As a result, since a part of the gate insulating film 3 is thickened, the gate capacitance is reduced and high speed operation becomes possible. Further, due to the P-type diffusion region 22 connected to the source potential below the gate insulating film 3, the capacitance related to the gate insulating film becomes the gate-source capacitance, and the so-called Miller effect is eliminated. Therefore, it is advantageous for higher speed operation. On the other hand, the N-type diffusion region 21 causes the J-FE
Since the T effect is weakened, it is possible to lower the on-voltage.

Further, in the case of an IGBT with respect to a MOSFET, holes are injected from the P ⁺ type drain region 2 when conducting, and the N ⁻ type epitaxial layer 1 undergoes conductivity modulation to reduce the resistance and the on-state voltage is remarkably increased. Get smaller. In addition,
4 to 6, reference numeral 8 is an interlayer insulating film, 9 is a source electrode, and 10 is a drain electrode.

[0009]

As described above, various structures have been proposed for making the transistor shown in FIG. 4 compatible with both high-speed operation and low on-voltage. However, there are problems in any case. ing.

For example, in the MOSFET shown in FIG.
If the width of the thick portion 3b of the gate insulating film is wide, there is a problem that the field plate effect is lost and the breakdown voltage is lowered.

On the other hand, in the IGBT shown in FIG. 6, since the central P-type diffusion region 22 is fixed to the source potential, the electrons flowing from the channel portion 6 into the N-type diffusion region 21 are P-type diffusion region 22. Cannot pass through, but flows into the N ⁻ type epitaxial layer 1 through the narrow N type diffusion region 21. Therefore, even if the N-type diffusion region 21 has a high concentration, the effect of reducing the on-voltage is small. Further, if the width of the N-type diffusion region 21 is widened in order to lower the ON voltage, the gate capacitance will increase this time. further,
Some of the holes injected from the P ⁺ type drain region 2 escape from the P type diffusion region 22 connected to the source potential, and as a result, the N ⁻ type epitaxial layer 1 is formed.
However, since the degree of conductivity modulation is reduced, the effect of reducing the on-voltage is small.

An object of the present invention is to solve the above problems and to provide an excellent vertical MOS semiconductor device capable of high-speed operation with a low on-voltage and a manufacturing method thereof.

[0013]

In order to achieve the above object, a vertical MOS semiconductor device according to the present invention comprises a semiconductor portion of a first conductivity type, a drain region provided on one surface side of the semiconductor portion, A plurality of second conductivity type first semiconductor regions provided on the other surface side of the semiconductor portion, and the first semiconductor region on the other surface side of the semiconductor portion between the first semiconductor regions facing each other. Of the first conductivity type provided in contact with
A second semiconductor region and a first semiconductor region provided in the second semiconductor region.
2 conductive type body region, a first conductive type source region provided in the body region, on the surface of the first semiconductor region, the second semiconductor region, the body region and the source region A gate insulating film having a thick portion is formed substantially above the first semiconductor region, a gate electrode provided on the gate insulating film, and electrically connected to the body region and the source region. And a drain electrode electrically connected to the drain region. Further, as the manufacturing method thereof, a step of forming a structure in which the first conductivity type semiconductor portion has a drain region on one surface side thereof, a step of forming a first insulating film on the other surface side of the semiconductor portion, and Forming a plurality of openings in the first insulating film, and introducing a second conductivity type impurity into the semiconductor portion through the openings to form a plurality of second conductivity type first semiconductor regions And a step of forming a second insulating film on at least the first semiconductor region, and the predetermined removal of the first and second insulating films by selectively removing the first and second insulating films. And an etching step of remaining forming a thick gate insulating film at the position, introducing impurities of the first conductivity type into the semiconductor portion using the thick gate insulating film as a mask, and of the first conductivity type in contact with the first semiconductor region. Forming a second semiconductor region and the thick gate insulating film A step of forming a continuous thin gate insulating film, a step of forming a gate electrode on the thick gate insulating film and the thin gate insulating film, and a second step in the second semiconductor region using the gate electrode as a mask A step of introducing a conductivity type impurity to form a second conductivity type body region;
A step of introducing a first conductivity type impurity into the body region using the gate electrode as a selection mask to form a first conductivity type source region, and a source electrode electrically connected to the body region and the source region And a step of forming a drain electrode electrically connected to the drain region.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an N according to the first embodiment of the present invention.
It is sectional drawing which shows a channel type power MOSFET. First
N-channel power MOSFET according to one embodiment
Then N⁻N under the epitaxial layer 1⁺Mold dray
Area 2 is provided and N ⁻Type epitaxial layer 1
From the surface of the P type diffusion region 12 and the N type diffusion region 11 are
It is formed so that it touches the sea. Furthermore, N-type diffusion area
A P-type body region 4 is formed inside the region 11, and a P-type body region 4 is formed.
N inside the area 4⁺The mold source region 5 is formed
There is. N⁺From the surface of the mold source region 5 to the P-type diffusion region 12
Gate insulating film 3 is formed over the surface of the
The surface of the region 12 has its thickened portion 3b
There is. In addition, the P-type body region 4 and N⁺In the mold source area 5
In addition to the source electrode 9 to be connected, N⁺Type of drain region
Of the drain electrode 10 and the gate insulating film 3 connected to the region 2
Gate electrodes 7 are provided on the upper side.

With such a structure, the P-type diffusion region 1 under the gate insulating film 3 is in an electrically floating state.
Since the breakdown voltage is prevented from decreasing by 2, the width of the thickened portion 3b of the gate insulating film 3 can be sufficiently widened. As a result, the gate capacitance can be significantly reduced.

Further, since the P-type diffusion region 12 exists up to immediately below the step portion 3d between the thick portion 3b and the thin portion 3a of the gate insulating film 3, the electric field strength in the gate insulating film at the step portion 3d is also relaxed. It This makes it possible to prevent problems such as deterioration of breakdown voltage and dielectric breakdown.

Further, the N-type diffusion region 11 surrounding the P-type body region 4 weakens the J-FET effect and enables a lower ON voltage.

FIG. 2 shows an N according to the second embodiment of the present invention.
It is sectional drawing which shows a channel type IGBT. In N-channel IGBT according to a second embodiment, N ^- -type N-type buffer layer 13 and the P ⁺ -type drain region 2 under the epitaxial layer 1 is provided, N ^- -type surface of the epitaxial layer 1 From the P-type diffusion region 12 and the N-type diffusion region 11
Are formed so as to be in contact with each other. Here, the depth of the P-type diffusion region 12 is deeper than the depth of the N-type diffusion region 11. Further, a P-type body region 4 is formed inside the N-type diffusion region 11, and an N-type body region 4 is formed inside the P-type body region 4.
^{A +} type source region 5 is formed. A gate insulating film 3 is formed from the surface of the N ⁺ type source region 5 to the surface of the P type diffusion region 12, and the surface of the P type diffusion region 12 has a thickened portion 3b. Here, the cross-sectional shape of the step portion 3d from the thin portion 3a to the thick portion 3b of the gate insulating film 3 is a curved shape as compared with the case of FIG. In addition to the source electrode 9 connected to the P type body region 4 and the N ⁺ type source region 5, the drain electrode 10 connected to the P ⁺ type drain region 2 and the gate electrode on the gate insulating film 3 7 are provided respectively.

N according to the first embodiment of the present invention shown in FIG.
In addition to the effect in the channel type power MOSFET,
It is possible to have the advantages described below.

First, by making the cross-sectional shape from the thin portion 3a to the thick portion 3b of the gate insulating film into a curved shape, the electric field strength in the gate insulating film at the step portion 3d can be more relaxed. . In addition, the gate insulating film 3
A gate electrode 7 provided on the gate electrode 7 and a source electrode 9 provided on the gate electrode 7 via an interlayer insulating film 8;
It is possible to prevent so-called step breakage from occurring on the step portion 3d of the gate insulating film.

Next, the N-type diffusion region 11 surrounding the P-type body region 4 enables a lower ON voltage in the case of an IGBT. This is because the potential barrier formed by the N-type diffusion region 11 suppresses the holes injected from the P ⁺ -type drain region 2 from leaking to the P-type body region 4 having the source potential, and the N ⁻ -type epitaxial region. As a result of more holes being accumulated in layer 1, N ⁻
This is because conductivity modulation in the epitaxial layer 1 is promoted.

Further, the inventor of the present invention has found that the deep P-type diffusion region 12 formed in contact with the N-type diffusion region 11 increases the short-circuit tolerance t _{SC of the} IGBT.
Here, the short-circuit tolerance t _SC is the time required for the IGBT to be destroyed when the load connected to the IGBT is short-circuited. Hereinafter, this point will be described.

When the load is short-circuited while the IGBT is conducting, the power supply voltage supplied to the load is directly applied between the drain region and the source region of the IGBT,
A saturation current corresponding to this voltage level flows through the IGBT. The temperature of the IGBT rises rapidly due to the Joule heat under the condition of high voltage and large current. On the other hand, IGBT
In this structure, there is a parasitic thyristor composed of four layers of N ⁺ type source region 5, P type body diffusion region 4, N ⁻ type epitaxial layer 1 and P ⁺ type drain region 2. I
When the GBT is conductive, a hole current passes through the P-type body region 4 and flows to the source electrode 9. Then, the voltage drop across the P-type body region 4 by the hole current is formed by the N ⁺ -type source region 5 and the P-type body region 4 N ⁺ · P
If the built-in potential at the junction is exceeded, N ⁺
Electrons are injected from the type source region 5 into the P type body region 4, and the parasitic thyristor is turned on. When the parasitic thyristor turns on, a larger current flows, and the device is destroyed. Therefore, even in an IGBT having a structure in which the parasitic thyristor does not turn on during normal operation, the built-in potential at the N ⁺ · P junction decreases because the element temperature rises sharply when the load is short-circuited, and eventually the parasitic thyristor decreases. Turns on and is destroyed.

FIG. 7 and FIG. 8 conceptually show the position of the current path inside the element and the point where the heat generation temperature becomes maximum when the load is short-circuited, based on the simulation results. FIG. 7 shows an N-channel type power M according to the first embodiment of the prior art.
This is a case of an IGBT conforming to the structure of OSFET, and FIG.
Is an N-channel type IGB according to the second embodiment of the present invention.
The case of T is shown.

In the case of FIG. 7, current concentrates on the N ⁻ type epitaxial layer 1 in the central portion sandwiched between the two opposing P type body regions 4, and the heat generation temperature becomes maximum at that position. On the other hand, in the case of FIG. 8, the current concentration portion is branched to the left and right of the P-type diffusion region 12. Since the P-type diffusion region 12 is in an electrically floating state, a sufficient current flows through the P-type diffusion region 12 during normal operation in which the drain-source voltage is small. As it grows, it becomes more difficult to flow inside.

As a result of the simulation conducted by the inventor of the present application, the maximum heat generation temperature in FIG. 8 was about 30 ° C. lower than the maximum heat generation temperature in FIG. 7. That is, since the maximum exothermic temperature at the time of current concentration is relieved load short circuit by the structure of the present invention is suppressed, N ⁺ -type source region 5 and P
It is considered that the decrease in the built-in potential at the N ⁺ .P junction with the type body region 4 is also reduced and the short-circuit withstand capacity t _SC is increased.

Further, as a result of the P-type diffusion region 12 being formed in contact with the N-type diffusion region 11, the P-type diffusion region 12 is formed.
It is also important that the lateral diffusion of P is suppressed and the distance between the P type diffusion region 12 and the P type body region 4 is sufficiently secured. It can be seen from FIG. 8 that, when this distance is reduced, the maximum heat generation point at the time of load short circuit comes close to the N ⁺ .P junction, and the short circuit withstand capacity t _SC is decreased conversely.

Next, a preferred method of manufacturing the N-channel type IGBT according to the second embodiment of the present invention shown in FIG. 2 will be described with reference to FIGS. 9 to 15.

First, P ⁺ which becomes the P ⁺ type drain region 2
A semiconductor portion including the N-type buffer layer 13 and the N ⁻ type epitaxial layer 1 is formed on the type semiconductor substrate by epitaxial growth. Here, it goes without saying that another forming method may be used. For example, an N-type buffer layer and a P ⁺ -type drain region may be formed by diffusion on an N ⁻ -type semiconductor substrate.

Next, on the surface of the N ^-- type epitaxial layer 1, a primary oxide film 31 having a thickness of about 8000 angstroms is formed.
Are formed by thermal oxidation. Then, the P-type diffusion region 1 is formed at a desired position on the oxide film by a photo and etching process.
An opening for forming 2 is formed, and boron is ion-implanted (FIG. 9).

Although not shown in the figure, this step can be performed simultaneously with the step of forming the field ring in the termination region of the device. At this time, for example, when the impurity concentration of the field ring is set to be higher than that of the P-type diffusion region 12, a photolithography process that does not require a high alignment precision is used to collectively cover the area other than the opening for forming the field ring. By masking with a resist and performing an additional boron ion implant.

Then, a secondary oxide film 32 having a thickness of about 6000 Å is formed in the opening by thermal oxidation.
At this time, the thickness of the oxide film which is not opened is 10
It will be about 000 angstroms. 1150 ° C
Drive-in diffusion for about 2 hours (Fig. 10).

Next, by a photo and etching process,
An opening for forming the N type diffusion region 11 is formed in the oxide film. In the future, the side wall of the opening will become a step portion 3d between the thin portion 3a and the thick portion 3b of the gate insulating film.
Therefore, in the main etching step, by using isotropic etching such as wet etching, it becomes possible to give a curvature to the cross-sectional shape of the step portion 3d. As a result, the relaxation of the electric field strength in the gate insulating film and the prevention of step breakage of the source electrode 9 are achieved (FIG. 11). Further, by providing this opening at a position substantially adjacent to the opening for the P-type diffusion region 12, the junction boundary formed by the N-type diffusion region 11 and the P-type diffusion region 12 is gate-insulated. It comes to be located immediately below the step portion 3d of the film.

Next, a thin oxide film 14 having a thickness of about 500 Å is formed on the main opening, and phosphorus is ion-implanted (FIG. 12). Then, drive-in diffusion is performed at 1150 ° C. for about 6 hours. Thin oxide film 1 at this time
4 has the effect of suppressing defects during ion implantation and of preventing the silicon surface from being nitrided and adversely affecting the subsequent formation of a thin gate oxide film when nitrogen gas is used in the drive-in diffusion process. .

Next, after removing the thin oxide film 14 by an etching process, an oxide film having a thickness of about 1000 angstroms which becomes the thin portion 3a of the gate insulating film is formed again. Then, a polycrystalline silicon film having a thickness of about 6000 Å serving as the gate electrode 7 is deposited on the entire gate insulating film 3 (FIG. 13). By covering the thin gate insulating film with the gate electrode material immediately after its formation as in this step, it is possible to reduce the chance of contaminants adhering to the interface between the gate insulating film and the gate electrode.
This is effective in preventing the electrical characteristics of the gate insulating film from being significantly deteriorated.

Next, by the photo and etching process,
An opening for forming the P-type body region 4 is formed in the oxide film and the polycrystalline silicon film on the N-type diffusion region 11, and boron is ion-implanted (FIG. 14). Here, by using a resist mask formed by a further photographic process, boron ion implantation is added only to the central portion of the P-type body region 4 to reduce the lateral resistance of the P-type body region 4 immediately below the N ⁺ type source region 5. It can be structured. Subsequently, drive-in diffusion is performed at 1150 ° C. for about 1 hour.

Next, arsenic is implanted by using a resist mask by a photolithography process, and then heat treatment is performed to form N ^+.
The mold source region 5 is formed (FIG. 15).

Subsequently, after depositing an interlayer insulating film 8 having a thickness of about 10000 angstrom, an opening for contact is formed by a photo and etching process, and a source electrode 9 is formed as an N ⁺ type source region 5 and a P type body. It is electrically connected to both of the regions 4. Further, the drain electrode 10 is electrically connected to the drain region 2 to complete the IGBT of FIG.

FIG. 3 shows an N according to the third embodiment of the present invention.
It is sectional drawing which shows a channel type IGBT. By changing the pattern of the opening of the oxide film for forming the P type diffusion region 12, it becomes possible to form the thicker portion 3c in the gate insulating film.

[0041]

According to the present invention, even if the width of the thick portion of the gate insulating film is increased in order to reduce the gate capacitance, an electrically floating state is formed immediately below that portion with a substantially equal width. The certain first semiconductor region does not reduce the breakdown voltage. Further, a second semiconductor formed in contact with the first semiconductor region
J-FET effect is reduced by the semiconductor region of
In the case of BT, conductivity modulation is further promoted. Therefore,
It is possible to provide a vertical MOS semiconductor device that can operate at high speed with a low ON voltage.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an N-channel power MOSFET according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing an N-channel IGBT according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing an N-channel type IGBT according to a third embodiment of the present invention.

FIG. 4 is a cross-sectional view showing an N-channel type power MOSFET according to a first embodiment of the prior art.

FIG. 5 is a cross-sectional view showing an N-channel power MOSFET according to a second embodiment of the prior art.

FIG. 6 is a sectional view showing an N-channel type IGBT according to a third embodiment of the prior art.

FIG. 7 is a diagram conceptually showing a current path and a position of a maximum heat generation point at the time of load short circuit of the IGBT according to the structure of the N-channel type power MOSFET according to the first embodiment of the prior art.

FIG. 8 is a diagram conceptually showing a current path and a position of a maximum heat generation point when a load is short-circuited in the N-channel IGBT according to the second embodiment of the present invention.

FIG. 9 is a diagram illustrating a manufacturing process of the vertical MOS semiconductor device of the present invention.

FIG. 10 is a diagram illustrating a manufacturing process of the vertical MOS semiconductor device of the present invention.

FIG. 11 is a diagram illustrating a manufacturing process of the vertical MOS semiconductor device of the present invention.

FIG. 12 is a diagram illustrating a manufacturing process of the vertical MOS semiconductor device of the present invention.

FIG. 13 is a diagram illustrating a manufacturing process of the vertical MOS semiconductor device of the present invention.

FIG. 14 is a diagram illustrating a manufacturing process of the vertical MOS semiconductor device of the present invention.

FIG. 15 is a diagram illustrating a manufacturing process of the vertical MOS semiconductor device of the present invention.

[Explanation of symbols]

1 N ⁻ Type Epitaxial Layer 2 Drain Region 3 Gate Insulating Film 3a Thin Gate Insulating Layer 3b Thick Gate Insulating Layer 3c Thicker Gate Insulating Layer 3d Gate Insulating Step 4 P Type Body Region 5 N ⁺ Type source region 6 channel part 7 gate electrode 8 interlayer insulating film 9 source electrode 10 drain electrodes 11, 21 N type diffusion regions 12, 22 P type diffusion region 13 N type buffer layer 14 thin oxide film 31 primary oxide film 32 secondary Oxide film

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/78 658G

Claims (7)

[Claims] 1. A semiconductor portion of a first conductivity type, a drain region provided on one surface side of the semiconductor portion, and a plurality of first semiconductors of a second conductivity type provided on the other surface side of the semiconductor portion. A region, a second semiconductor region of a first conductivity type provided in contact with the first semiconductor region on the other surface side of the semiconductor portion between the first semiconductor regions facing each other, and the second semiconductor region. A second conductivity type body region provided in the semiconductor region, and a first conductivity type source region provided in the body region,
The first semiconductor region, the second semiconductor region, the body region and the source region are formed on the surface of the first semiconductor region.
A gate insulating film having a thick portion substantially above the semiconductor region, a gate electrode provided on the gate insulating film, and a source electrode electrically connected to the body region and the source region, A vertical MOS semiconductor device having a drain electrode electrically connected to the drain region. 2. The vertical MOS semiconductor device according to claim 1, wherein the depth of the first semiconductor region is equal to or greater than the depth of the second semiconductor region. 3. The vertical MOS semiconductor device according to claim 1, wherein the drain region is of a first conductivity type. 4. The vertical MOS semiconductor device according to claim 1, wherein the drain region is of a second conductivity type. 5. A step of forming a semiconductor region of a first conductivity type having a drain region on one surface side thereof, a step of forming a first insulating film on the other surface side of the semiconductor portion; Forming a plurality of openings in the insulating film, and introducing impurities of the second conductivity type into the semiconductor portion through the openings,
A step of forming a plurality of first semiconductor regions of the second conductivity type,
Forming a second insulating film on at least the first semiconductor region, and selectively removing the first and second insulating films to form a thick film at a predetermined position substantially above the first semiconductor region. An etching step of remaining forming a gate insulating film, a first conductive type impurity is introduced into the semiconductor portion using the thick gate insulating film as a mask, and a first contact with the first semiconductor region is made.
Forming a conductive type second semiconductor region, forming a thin gate insulating film continuous with the thick gate insulating film, and forming a gate electrode on the thick gate insulating film and the thin gate insulating film And a step of introducing a second conductivity type impurity into the second semiconductor region by using the gate electrode as a mask to form a second conductivity type body region, and the body using the gate electrode as a selection mask. Introducing a first conductivity type impurity into the region to form a first conductivity type source region, a step of forming a source electrode electrically connected to the body region and the source region, and the drain region And a step of forming a drain electrode electrically connected to the vertical MOS semiconductor device. 6. The vertical MO according to claim 5, wherein the etching process uses wet etching.
S Semiconductor device manufacturing method. 7. The impurity of the first conductivity type in the step of forming the second semiconductor region is performed through another thin insulating film that is removed before forming the thin gate insulating film. 7. The method for manufacturing a vertical MOS semiconductor device according to claim 5, wherein: