JPH0485956A - Semiconductor bidirectional switch - Google Patents

Abstract

PURPOSE:To decrease ON resistance by surrounding transistors with channel cut regions and N<+> drift regions of the same conductivity type as a drift region and thereby separating a pair of MOS transistors composing a semiconductor bidirectional switch from each other. CONSTITUTION:An N/N<+> substrate is anisotropically etched to make grooves 11 at positions in where conductive channel cut regions 8 are to be formed. Conductive channel cut regions 8 are formed in the grooves 11 by deposition and etching back of amorphous silicon or polysilicon doped into N form and a gate oxide film 5 is formed. The polysilicon is deposited and patterned to form gate wirings 6 and boron ions are implanted with the gate wirings 6 used as masks to form channel regions 3. Source regions 4 are formed by selectively implanting phosphorus ions and arsenic ions. Layer insulating films 7 are deposited, contact holes 12 are made, and wirings 9 are formed. Thereby cell density is heightened and ON resistance is decreased through microstructure.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to semiconductor bidirectional switches, and in particular to improving latch-up withstand voltage and reducing parasitic M in semiconductor bidirectional switches.
Related to technologies such as O5 suppression.

[Prior art]

A conventional semiconductor bidirectional switch is described, for example, in U.S. Pat. No. 4,558,243.

FIG. 6 is a sectional view of the semiconductor bidirectional switch described above.

The apparatus of FIG. 6 grows an n-type drift region 222 on a p-type substrate 224, and the n-type drift region
Two DMOs that share the same device structure and have the same device structure
S transistors T□ and T2 are formed and connected in series drain-to-drain. In addition, n
The shaped drift region 222 functions as a common drain of T and T2.

In the above device, two gates G1, G2 are applied with a positive voltage Vc to each source 248, 250, T1, T2 (71 channels 214°216 are formed, two sources 248, 250 Conductive state (on) between
becomes. On the other hand, if Ov or a negative voltage is applied to the two gates G1 and G2, the channels 214 and 216 are cut,
There is no conduction between the two sources 248 and 250 (off).

In the above configuration, two DMO5)-transistor T□,
There are two PN junctions 2 between the sources 248 and 250 of T2.
18 and 220 are inserted in opposite directions, and as a result, it has a reverse blocking characteristic, so it can be used for alternating current switching applications.

However, the configuration shown in FIG. 6 has a problem in that there is a large amount of leakage current due to the parasitic MO5 when it is off.

As an improved device, U.S. Patent No. 4,571゜60
No. 6 is proposed.

FIG. 7 is a cross-sectional view of the improved device described above.

In the device of FIG. 6, two channel regions 20
6 and 208, a parasitic P-channel MO5FET using the n-type drift region 204 as a base was likely to be formed, which caused leakage when turned off. Therefore, as in the device shown in FIG. 7, the parasitic MO8 can be cut by embedding an insulator 110 deep from the surface between the two transistors T1 and T2.

Moreover, the embedding of the insulator 110 described above is also effective in improving the withstand voltage of the device and injecting minority carriers during switching transients.

That is, in FIG. 7, if we consider the case where a positive potential is applied to the source 146 of T2 and a negative potential is applied to the source 144 of T1, the potential difference between the sources 146 and 144 is almost equal to the channel region 122 of T1 and the n-drift. Area 104
The depletion layer spans the PN junction between n-drift region 1
It protrudes to the 04 side, but is shielded by the buried insulating layer 110 and the T
It becomes difficult to reach the channel region 124 of No. 1. Therefore, the bunch-through withstand voltage is improved.6 Also, in order for this device to switch from on to off, it is sufficient to apply a voltage Va higher than the threshold voltage to each of the two gates G□ and G26. but.

When the gate G starts up faster due to timing problems or external noise.

Conduction of channel 140 causes channel region 12 of T2 to
Holes, which are minority carriers, are injected from the n-drift region 104 into the n-drift region 104. Without the insulator 110, the holes described above would diffuse into the channel region 122 of T1 and risk causing latch-up, but in the structure of FIG. The latch-up immunity is improved because the diffusion of There is also an advantage.

[The problem that the invention attempts to solve]

By the way, the semiconductor bidirectional switch shown in Figures 6 and 7 is basically two MOSFETs connected in series, so although it is superior in that it does not have the forward drop of a PN junction like a thyristor, it is not normally used. MOSFET
It has the disadvantage that the on-resistance per unit area is higher than that of other types.

In particular, although the configuration shown in FIG. 7 has the above-mentioned excellent effects, it also has the drawback of worsening the on-resistance. That is, in the structure of FIG. 7, when both channels 140 and 142 are conductive, #! The n-drift region 104 under the edge 110 has a narrow path, which causes an increase in resistance.

Further, the above-mentioned latch-up suppression also has the following problems. That is, considering the case where the P-type substrate 108 is used in a floating state, holes flow into the P-type substrate 108, causing an increase in the potential here, and the P-type substrate 108 becomes higher in potential than the n-drift region 104, causing the P-type substrate 108 to have a higher potential than the n-drift region 104.
Hole injection from the shaped substrate 108 into the n-drift region 104 occurs again. Therefore, the holes eventually flow into the channel region 122 and 124-404-10
As a 6-layer thyristor of 8-104-140-126 (pnpnpn), it had the drawback of causing latch-up.

In particular, when increasing the cell density in order to lower the on-resistance of this type of device, that is, miniaturizing the T and T2 and decreasing the distance d between them, the above points become an extremely large obstacle. was.

As mentioned above, in the conventional technology, ■ Parasitic M when off
There were problems such as an increase in leakage current due to O5, (1) an increase in on-resistance, and (2) a decrease in latch-up breakdown voltage.

The present invention has been made to solve the problems of the prior art as described above, and includes: cutting parasitic MO5 in a semiconductor bidirectional switch; promoting recombination of minority carriers;
The purpose of this is to provide a structure that can realize the following: ■Secure a conductive path.

[Means to solve the problem]

In order to achieve the above object, the present invention is configured as described in the claims.

That is, in the present invention, a high concentration region of the same conductivity type as the drift region is provided below the drift region, and a conductive channel cut region is further partitioned between the two transistors forming the semiconductor bidirectional switch. It is configured as follows.

[Effect]

When the two transistors that make up the semiconductor bidirectional switch become conductive, both the above-mentioned high concentration region and the conductive channel cut region become conductive paths, which significantly lowers the on-resistance compared to conventional methods. I can do it. Furthermore, latch-up during minority carrier injection, which has been a problem in the prior art, is completely prevented because minority carrier recombination occurs within the above-mentioned high concentration region and conductive channel cut region. Therefore, cell density can be improved by miniaturization, which makes it possible to further reduce on-resistance.

[Embodiments of the invention]

FIG. 1 is a sectional view of an embodiment of the present invention.

In FIG. 1, 1 is a high impurity concentration N'' drift region, 2 is an N drift region, 3 is a P type channel region, and 4 is an N+ source region. A gate wiring IIA6 is provided.

Further, numeral 8 denotes a conductive channel cut region, which is the key point of the present invention, and surrounds each transistor when viewed from the top of the figure. Specifically, non-single crystal poly-Si (metal is also acceptable) or amorphous Si.
Configure using. The conductivity type is N, which is the same as N drift region 2.
It is the shape.

Non-single crystals like the ones above structurally have a large amount of deep levels (
Therefore, the minority carriers recombine and disappear in the conductive channel cut region 8, and if the impurity is heavily doped, an inversion layer is also less likely to be formed. On the other hand, since the conductivity type is the same as that of the N drift region 2, electrons can freely come and go. Therefore, the above ■～■
can achieve the purpose of

Note that as another method, defects may be selectively introduced using, for example, an electron beam.

Also, if the thickness of the N drift region 2 is relatively thin (
For example, in the case of an AC application of several tens of volts, the necessary breakdown voltage can be obtained with a few micrometers), direct doping with a high concentration of N-type impurity can be used instead. Such a high concentration of N-type impurities suppresses the generation of parasitic P channels and promotes recombination of minority carriers to prevent latch-up. It is also possible to lower the on-resistance of the device. Furthermore, if the thickness of the N drift region 2 is thin, the diffusion depth can be made shallow, so that lateral diffusion due to doping can be suppressed to a level that does not cause any practical problems.

Next, the effect will be explained.

FIG. 2 is a diagram showing the wiring state of the device.

(a) shows a cross-sectional view, and (b) shows an equivalent circuit diagram.

In FIG. 2, mutually adjacent DMOS transistors T
□, T2 are separated by the aforementioned conductive channel region 8. As shown in the equivalent circuit, it is composed of two drain-to-drain MOSs as in the conventional case. The method of use is the same as before.

When gate voltage Va is applied to gates G0 and G2, 5T
1, the channel of T2 turns on and becomes conductive. At this time, since both the conductive channel cut region 8 and the N+ drift region 1 serve as conductive paths, the on-resistance can be significantly lowered compared to the conventional method. Also.

Latch-up during minority carrier injection, which has conventionally been a problem, is completely prevented because minority carrier recombination occurs within the conductive channel cut region 8 and the N+ drift region 1. Therefore, cell density can be improved by miniaturization, which makes it possible to further reduce on-resistance.

Next, FIG. 3 is a sectional view of a second embodiment of the present invention.

This embodiment has a structure in which the bottom of the channel region 3a is diffused so as to be in contact with the N+ drift region 1.

In this structure, the PN junction formed between the channel region 3a and the N+ drift region 1 is located directly below the source contact, so that it can be used as a clamping Zener diode with a small dynamic resistance rd against an excessive surge voltage exceeding the withstand voltage. It can be used as Further, when the channel region 3a and the N drift region 2 are transiently in a forward bias state, holes are directly injected from the channel region 3a into the N+ drift region 1, which has a high recombination rate, which is advantageous in preventing latch-up. It is. It also contributes to shortening the storage time caused by these minority carriers.

Next, FIG. 4 is a sectional view of a third embodiment of the present invention. This embodiment is a development of the embodiment shown in FIG. 3, and has a structure in which a high concentration body region is provided from the channel region 3 to the center of the cell. With such a structure, the dynamic resistance rg' of the Zener diode can be further reduced, so that the effect explained in FIG. 3 can be enhanced.

Next, FIG. 5 is a diagram showing an example of the manufacturing process of the device shown in FIG. 1. Note that, of course, the method for manufacturing the structure of the present invention is not limited to this example.

The manufacturing method shown in FIG. 5 will be briefly explained below.

First, as shown in (a), an N/N+ substrate is prepared, and a groove 11 is formed in a portion where the conductive channel cut region 8 is to be formed by anisotropic etching (for example, reactive ion etching). This groove 11 is formed up to a part of the N1 drift region 1 as shown in the figure. In addition, N
It goes without saying that the + drift region 1 is not limited to one semiconductor substrate, and may be an N+ buried layer in applications such as normal integrated circuits.

Next, as shown in (b), a conductive channel cut region 8 is formed in the trench 11 by depositing and etching back N-type doped amorphous silicon or polysilicon.

Thereafter, the surface is oxidized to form a gate oxide film 5.

Note that when N1 diffusion is used as the conductive channel cut region 8, it can be formed by skipping the step (a) above and selectively performing ion implantation diffusion here. Further, when electron beam irradiation is used, it may be selectively irradiated after the electrode step (f) described below is completed.

Next, as shown in (c), polysilicon is deposited and patterned to form gate wiring 6, and then gate wiring I! Using 6 as a mask, boron ions are implanted to form a channel region 3.

Next, as shown in (d), ions of phosphorus or arsenic are selectively implanted to form a source region 4.

Next, as shown in (e), an insulating film between the eyebrows (for example, PSG
) 7, the contact hole 12 is opened.

Next, as shown in (f), a metal to be an electrode is deposited and then patterned to form a wiring 9.

Thereafter, by forming an ohmic contact between the wiring 9 and the semiconductor by sintering, the device shown in FIG. By configuring the pair of MOS transistors constituting the semiconductor bidirectional switch to be separated by surrounding them with a channel cut region and an N+ drift region of the same conductivity type, latch-up and parasitic MO
5 can be prevented and the on-resistance can be further reduced.
This effect can be obtained.

Further, in addition to the above-mentioned common effects, the embodiment shown in FIG. 3 has the effects of improving avalanche resistance, preventing latch-up, and shortening storage time.

In the embodiment of FIG. 4, an effect superior to that of the embodiment of FIG. 3 can be obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view of the first embodiment of the present invention, and FIG. 2 is a sectional view of the first embodiment of the present invention.
The wiring diagram and equivalent circuit diagram of the embodiment shown in the figure, FIG. 3 is a sectional view of the second embodiment of the present invention, and FIG. 4 is the third embodiment of the present invention.
FIG. 5 is a sectional view showing an example of the manufacturing process of the present invention, and FIGS. 6 and 7 are sectional views of a conventional example. <Explanation of symbols> 1... N+ drift region 2... N drift region 3... P-type channel region 3a... Channel region with a different structure 4... N+ source region 5... Gate oxide film 6... ... Gate wiring 7 ... Insulating film 8 ... Conductive channel cut region 9 ... Metal wire 0 ... Body region 1 ... Groove 2 for forming conductive channel cut region / Contact hole 3 ... ·channel

Claims (1)

[Scope of Claims] A channel region of a second conductivity type formed in a drain region of a first conductivity type, and a first conductivity type channel region formed in the channel region.
A first MISFET section having a source region of a conductivity type, and an insulated gate formed to cover surfaces of the source region, the channel region, and the drain region, and sharing the drain region of the first conductivity type. and the first M
A second MISF having almost the same structure as the ISFET section
ET section, in a so-called semiconductor bidirectional switch in which the source of the first MISFET is used as one terminal of the switch, and the source of the second MISFET is used as the other terminal of the switch, A first conductivity type layer having a high impurity concentration is provided below the drain region of the shape, and a conductive layer reaching the first conductivity type layer from the surface is provided between the first MISFET section and the second MISFET section. A semiconductor bidirectional switch characterized by having a channel cut area.