JP3301271B2 - Horizontal power MOSFET - Google Patents
Horizontal power MOSFETInfo
- Publication number
- JP3301271B2 JP3301271B2 JP12783395A JP12783395A JP3301271B2 JP 3301271 B2 JP3301271 B2 JP 3301271B2 JP 12783395 A JP12783395 A JP 12783395A JP 12783395 A JP12783395 A JP 12783395A JP 3301271 B2 JP3301271 B2 JP 3301271B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- conductivity
- concentration
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 22
- 238000009792 diffusion process Methods 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 13
- 230000015556 catabolic process Effects 0.000 description 5
- 238000000605 extraction Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、横型パワーＭＯＳＦＥ
Ｔ（ＬＤＭＯＳ）に関し、特にオン抵抗を低減するため
の構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal power MOSFET.
The present invention relates to T (LDMOS), and particularly to a structure for reducing on-resistance.
【０００２】[0002]
【従来の技術】従来のＬＤＭＯＳとしては、例えば本件
発明者らにより特願平６−１０９８４号で開示した図
７、図８に示すようなものがある。両図は、それぞれ断
面構造と平面パターン配置を示している。図７におい
て、Ｐ型半導体基板１の第１主面内に低抵抗領域となる
Ｎ+ 型埋込み層２が形成され、このＮ+ 型埋込み層２を
含むＰ型半導体基板１の第１主面上にＰ型エピタキシャ
ル層３が形成されている。Ｐ型エピタキシャル層３内に
Ｎ型ドレイン領域（Ｎ型半導体基体領域）４が形成され
ている。Ｎ型ドレイン領域４内にＰ型ベース領域５及び
高濃度Ｎ+ 型ドレイン領域８が形成され、さらにＮ+ 型
埋込み層２に達する導通領域としての高濃度Ｎ+ 型ドレ
イン取り出し領域７が形成されている。Ｐ型ベース領域
５内には高濃度Ｎ+ 型ソース領域６が形成されており、
高濃度Ｎ+ 型ソース領域６とＮ型ドレイン領域４との間
のＰ型ベース領域５上にゲート絶縁膜９を介してゲート
電極１０が形成されている。上記のＰ型ベース領域５と
その領域内に形成された高濃度Ｎ+ 型ソース領域６と
は、全面に形成されたゲート電極１０膜に設けられたソ
ース開口部からの二重拡散により形成され、高濃度Ｎ+
型ドレイン領域８は、同じくゲート電極１０膜に設けら
れたドレイン開口部からの拡散により形成されている。
そして、第１層層間絶縁膜１１によりゲート電極１０と
絶縁されてソース電極１２及びドレイン電極１３が形成
され、第２層層間絶縁膜１４によりソース電極１２と絶
縁されてドレイン電極１３に接続された第２層ドレイン
電極１５が形成されている。2. Description of the Related Art As a conventional LDMOS, for example, there is one shown in FIGS. 7 and 8 disclosed in Japanese Patent Application No. 6-10984 by the present inventors. Both figures show a cross-sectional structure and a plane pattern arrangement, respectively. In FIG. 7, an N + -type buried layer 2 serving as a low-resistance region is formed in a first main surface of a P-type semiconductor substrate 1, and the first main surface of the P-type semiconductor substrate 1 including the N + -type buried layer 2 A P-type epitaxial layer 3 is formed thereon. An N-type drain region (N-type semiconductor substrate region) 4 is formed in the P-type epitaxial layer 3. A P-type base region 5 and a high-concentration N + -type drain region 8 are formed in the N-type drain region 4, and a high-concentration N + -type drain extraction region 7 as a conduction region reaching the N + -type buried layer 2 is formed. ing. A high concentration N + -type source region 6 is formed in the P-type base region 5,
A gate electrode 10 is formed on a P-type base region 5 between a high-concentration N + -type source region 6 and an N-type drain region 4 via a gate insulating film 9. The P-type base region 5 and the high-concentration N + -type source region 6 formed in the P-type base region 5 are formed by double diffusion from a source opening provided in a gate electrode 10 film formed on the entire surface. , High concentration N +
The type drain region 8 is formed by diffusion from a drain opening also provided in the gate electrode 10 film.
Then, the source electrode 12 and the drain electrode 13 were formed by being insulated from the gate electrode 10 by the first interlayer insulating film 11, and were connected to the drain electrode 13 by being insulated from the source electrode 12 by the second interlayer insulating film 14. A second layer drain electrode 15 is formed.
【０００３】図８は、ＭＯＳＦＥＴセルを構成するソー
スセル領域Ｓ及びドレインセル領域Ｄの平面配置を示し
ている。なお、ソースセル領域Ｓ及びドレインセル領域
Ｄとは、全面に形成したゲート電極１０膜に開けたソー
ス開口部及びドレイン開口部にそれぞれ対応する領域で
ある。ただし、実際上の開口部は、ソース電極１２及び
ドレイン電極１３とゲート電極１０との接触を避けるた
めに設けた第１層層間絶縁膜１１の開口部（ゲート電極
１０に設けた開口部よりもやや狭い）となる。図に示す
ように、ＭＯＳＦＥＴセル１個当たりソースセル領域Ｓ
が６×６個配列の正方形メッシュ状に所定のピッチで配
置されており、その中心の２×２個配列のソースセル領
域位置にドレインセル領域Ｄが配置されている。このよ
うなＭＯＳＦＥＴセル１個当たりのパターン配置を基本
として、繰り返しソースセル領域Ｓとドレインセル領域
Ｄが配置されている。FIG. 8 shows a plan layout of a source cell region S and a drain cell region D constituting a MOSFET cell. The source cell region S and the drain cell region D are regions respectively corresponding to a source opening and a drain opening formed in the gate electrode 10 film formed on the entire surface. However, the actual opening is formed in the opening of the first interlayer insulating film 11 provided to avoid contact between the source electrode 12 and the drain electrode 13 and the gate electrode 10 (in comparison with the opening provided in the gate electrode 10). Slightly narrower). As shown, the source cell region S per MOSFET cell
Are arranged at a predetermined pitch in a 6 × 6 array of square meshes, and a drain cell region D is arranged at the center of the 2 × 2 array of source cell regions. Based on such a pattern arrangement per MOSFET cell, a source cell region S and a drain cell region D are repeatedly arranged.
【０００４】次に、上記従来のＬＤＭＯＳの動作を説明
する。第２層ドレイン電極１５とソース電極１２との間
に正電圧が印加された状態で、ゲート電極１０にしきい
値以上の電圧が印加されるとゲート電極１０直下のＰ型
ベース領域５の表面がＮ型に反転しチャネルが形成され
る。ドレインセル領域Ｄの周辺部に対向したソースセル
領域Ｓでは高濃度Ｎ+ 型ドレイン領域８から電流がＮ型
ドレイン領域４内に拡がり、上記チャネルを経由して高
濃度Ｎ+ 型ソース領域６に電流が流れる。またドレイン
セル領域Ｄの周辺部に対向していない、即ちドレインセ
ル領域Ｄから離れているソース領域Ｓでは、高濃度Ｎ+
型ドレイン領域８から高濃度Ｎ+ 型ドレイン取り出し領
域７に電流が流れ、引き続きＮ+ 型埋込み層２を横方向
に流れ、さらにＮ型ドレイン領域４を縦方向に流れチャ
ネルを経由して高濃度Ｎ+ 型ソース領域６に電流が流れ
る。Next, the operation of the conventional LDMOS will be described. When a voltage equal to or higher than the threshold value is applied to the gate electrode 10 in a state where a positive voltage is applied between the second layer drain electrode 15 and the source electrode 12, the surface of the P-type base region 5 immediately below the gate electrode 10 becomes The channel is inverted to N-type to form a channel. In the source cell region S opposed to the peripheral portion of the drain cell region D, a current spreads from the high-concentration N + -type drain region 8 into the N-type drain region 4, and flows into the high-concentration N + -type source region 6 via the channel. Electric current flows. In the source region S not facing the peripheral portion of the drain cell region D, that is, in the source region S remote from the drain cell region D, the high concentration N +
A current flows from the drain region 8 to the high-concentration N + drain extraction region 7, subsequently flows laterally through the N + -type buried layer 2, further flows vertically through the N-type drain region 4, and flows through the channel. A current flows through the N + type source region 6.
【０００５】従来のＬＤＭＯＳにおいては、ソース電極
１２、ゲート電極１０、ドレイン電極１３の各電極が半
導体基板の同一主面上にあるので、複数の出力ＭＯＳＦ
ＥＴを１チップ化することができるという利点があり、
これと同時に、所定の間隔で配置されたソースセル領域
Ｓの一部をドレインセル領域Ｄに置き換えてソースセル
領域Ｓの高集積化を可能としオン抵抗の低減を図ってい
る。In the conventional LDMOS, since each electrode of the source electrode 12, the gate electrode 10, and the drain electrode 13 is on the same main surface of the semiconductor substrate, a plurality of output MOSFs are provided.
There is an advantage that ET can be made into one chip,
At the same time, a part of the source cell region S arranged at a predetermined interval is replaced with a drain cell region D to enable high integration of the source cell region S and reduce on-resistance.
【０００６】[0006]
【発明が解決しようとする課題】従来のＬＤＭＯＳで
は、Ｐ型ベース領域とＮ型ドレイン領域の間にできる空
乏層によりゲート電極下方のＮ型ドレイン領域部分の抵
抗が大きくなるという、いわゆるＪ−ＦＥＴ効果による
抵抗を低減するために一定値以上のゲート長が必要とな
っている。しかしながらゲート長が長くなると、ゲート
電極下方のＮ型ドレイン領域部分自身の抵抗が増してオ
ン抵抗を低減させるのに限界があった。このように、従
来のＬＤＭＯＳではオン抵抗を低減させるのに限界があ
り、より一層のオン抵抗低減技術が求められていた。In a conventional LDMOS, a depletion layer formed between a P-type base region and an N-type drain region increases the resistance of an N-type drain region below a gate electrode. In order to reduce the resistance due to the effect, a gate length exceeding a certain value is required. However, when the gate length is increased, the resistance of the N-type drain region below the gate electrode itself increases, and there is a limit in reducing the on-resistance. As described above, there is a limit in reducing the on-resistance in the conventional LDMOS, and a further on-resistance reduction technique has been demanded.
【０００７】本発明は、上記に鑑みてなされたもので、
耐圧を低下させることなく、より一層オン抵抗を低減す
ることのできる横型パワーＭＯＳＦＥＴを提供すること
を目的とする。[0007] The present invention has been made in view of the above,
It is an object of the present invention to provide a lateral power MOSFET that can further reduce the on-resistance without lowering the withstand voltage.
【０００８】[0008]
【課題を解決するための手段】上記課題を解決するため
に、請求項１記載の発明は、ドレイン領域となる第１導
電型の半導体基体領域の第１主面側にゲート絶縁膜を介
して形成されたゲート電極と、該ゲート電極に設けられ
たソース開口部からの二重拡散により形成された第２導
電型ベース領域及び該第２導電型ベース領域内に形成さ
れた高濃度第１導電型ソース領域と、前記ゲート電極に
設けられたドレイン開口部から前記半導体基体領域に電
気的に導通をとるために形成された高濃度第１導電型ド
レイン領域と、前記半導体基体領域における前記第１主
面側とは反対側の第２主面側に形成された低抵抗領域
と、該低抵抗領域と前記高濃度第１導電型ドレイン領域
とを低抵抗で導通させる導通領域とを備え、前記ゲート
電極、前記高濃度第１導電型ソース領域に接続されたソ
ース電極及び前記高濃度第１導電型ドレイン領域に接続
されたドレイン電極の各電極が前記第１主面側に設けら
れた横型ＭＯＳＦＥＴの構造を有するセルが同一チップ
上に複数個配置されるとともに、該複数個のセルの平面
的な配置パターンは前記ソース開口部に対応するソース
セル領域と前記ドレイン開口部に対応するドレインセル
領域とが規則的に所定のピッチで配置されており、かつ
１つのセルには中央部に配置された１つのドレインセル
領域の周りに複数個のソースセル領域が２列以上隣り合
って設けられた構成を有する横型パワーＭＯＳＦＥＴに
おいて、隣り合う前記第２導電型ベース領域の各間にお
ける前記半導体基体領域の第１主面側に高濃度第１導電
型領域を形成してなることを要旨とする。According to a first aspect of the present invention, there is provided a semiconductor device, comprising: a first conductive type semiconductor substrate region serving as a drain region; A gate electrode formed, a second conductivity type base region formed by double diffusion from a source opening provided in the gate electrode, and a high concentration first conductivity formed in the second conductivity type base region. A source region, a high-concentration first-conductivity-type drain region formed to electrically conduct from the drain opening provided in the gate electrode to the semiconductor base region, and a first conductive type drain region formed in the semiconductor base region. A low resistance region formed on the second main surface side opposite to the main surface side, and a conduction region for conducting the low resistance region and the high-concentration first conductivity type drain region with low resistance, Gate electrode, said high concentration A cell having a lateral MOSFET structure in which a source electrode connected to a conductive type source region and a drain electrode connected to the high-concentration first conductive type drain region are provided on the first main surface side is the same chip A plurality of cells are arranged on the substrate, and the planar arrangement pattern of the plurality of cells is such that a source cell region corresponding to the source opening and a drain cell region corresponding to the drain opening are regularly arranged at a predetermined pitch. In one cell, a plurality of source cell regions are adjacent to each other in two or more rows around one drain cell region arranged in the center.
And a high-concentration first conductivity type region is formed on the first main surface side of the semiconductor base region between each of the adjacent second conductivity type base regions. Is the gist.
【０００９】請求項２記載の発明は、ドレイン領域とな
る第１導電型の半導体基体領域の第１主面側にゲート絶
縁膜を介して形成されたゲート電極と、該ゲート電極に
設けられたソース開口部からの二重拡散により形成され
た第２導電型ベース領域及び該第２導電型ベース領域内
に形成された高濃度第１導電型ソース領域と、前記ゲー
ト電極に設けられたドレイン開口部から前記半導体基体
領域に電気的に導通をとるために形成された高濃度第１
導電型ドレイン領域と、前記半導体基体領域における前
記第１主面側とは反対側の第２主面側に形成された低抵
抗領域と、該低抵抗領域と前記高濃度第１導電型ドレイ
ン領域とを低抵抗で導通させる導通領域とを備え、前記
ゲート電極、前記高濃度第１導電型ソース領域に接続さ
れたソース電極及び前記高濃度第１導電型ドレイン領域
に接続されたドレイン電極の各電極が前記第１主面側に
設けられた横型ＭＯＳＦＥＴの構造を有するセルが同一
チップ上に複数個配置されるとともに、該複数個のセル
の平面的な配置パターンは前記ソース開口部に対応する
ソースセル領域と前記ドレイン開口部に対応するドレイ
ンセル領域とが規則的に所定のピッチで配置されてお
り、かつ１つのセルには中央部に配置された１つのドレ
インセル領域の周りに複数個のソースセル領域が２列以
上隣り合って設けられた構成を有する横型パワーＭＯＳ
ＦＥＴにおいて、隣り合う前記第２導電型ベース領域の
各間に対応する前記低抵抗領域上に高濃度第１導電型凸
状領域を形成してなることを要旨とする。According to a second aspect of the present invention, there is provided a gate electrode formed on a first main surface side of a semiconductor substrate region of a first conductivity type serving as a drain region via a gate insulating film, and provided on the gate electrode. A second conductivity type base region formed by double diffusion from a source opening, a high-concentration first conductivity type source region formed in the second conductivity type base region, and a drain opening provided in the gate electrode High-concentration first portion formed to electrically connect the portion to the semiconductor base region from the portion.
A conductive type drain region, a low resistance region formed on a second main surface side of the semiconductor substrate region opposite to the first main surface side, the low resistance region and the high concentration first conductivity type drain region. And a conduction region that conducts with low resistance between the gate electrode, the source electrode connected to the high concentration first conductivity type source region, and the drain electrode connected to the high concentration first conductivity type drain region. A plurality of cells having a lateral MOSFET structure in which electrodes are provided on the first main surface side are arranged on the same chip, and a planar arrangement pattern of the plurality of cells corresponds to the source opening. A source cell region and a drain cell region corresponding to the drain opening are regularly arranged at a predetermined pitch, and one cell is provided around one drain cell region arranged at a central portion. Lateral power MOS in which a plurality of source cell region has a structure provided to be adjacent to two or more rows
In the FET, a high-concentration first-conductivity-type convex region is formed on the low-resistance region corresponding to each space between adjacent second-conductivity-type base regions.
【００１０】請求項３記載の発明は、上記請求項１又は
２記載の横型パワーＭＯＳＦＥＴにおいて、前記高濃度
第１導電型領域又は前記高濃度第１導電型凸状領域は、
前記高濃度第１導電型ドレイン領域と、当該高濃度第１
導電型ドレイン領域と対向する前記第２導電型ベース領
域との間には形成せず、かつ前記高濃度第１導電型領域
又は前記高濃度第１導電型凸状領域と前記高濃度第１導
電型ドレイン領域との距離は、前記高濃度第１導電型ド
レイン領域と、当該高濃度第１導電型ドレイン領域と対
向する前記第２導電型ベース領域間の距離以上に形成し
てなることを要旨とする。According to a third aspect of the present invention, in the lateral power MOSFET according to the first or second aspect, the high-concentration first-conductivity-type region or the high-concentration first-conductivity-type convex region includes:
The high-concentration first conductivity type drain region;
The high-concentration first conductivity-type region or the high-concentration first-conductivity-type convex region is not formed between the second-conductivity-type base region and the second-conductivity-type base region facing the first-conductivity-type drain region. The distance between the high-concentration first-conductivity-type drain region and the second-conductivity-type base region opposed to the high-concentration first-conductivity-type drain region is formed. And
【００１１】[0011]
【作用】請求項１記載の発明において、隣り合う第２導
電型ベース領域の各間におけるドレイン領域となる第１
導電型半導体基体領域の第１主面側に高濃度第１導電型
領域を形成することにより、ゲート長をある一定値以上
としても、ゲート電極下方の第１導電型半導体基体領域
自身の第１主面側部分の抵抗が減少して一層オン抵抗を
低減させることが可能となる。According to the first aspect of the present invention, a first region serving as a drain region between adjacent second conductivity type base regions is provided.
By forming the high-concentration first conductivity type region on the first main surface side of the conductivity type semiconductor substrate region, even if the gate length is set to a certain value or more, the first conductivity type semiconductor substrate region itself below the gate electrode can be used. The resistance of the main surface side portion is reduced, so that the on-resistance can be further reduced.
【００１２】請求項２記載の発明において、隣り合う前
記第２導電型ベース領域の各間に対応する低抵抗領域上
に高濃度第１導電型凸状領域を形成することにより、ゲ
ート長をある一定値以上としても、ゲート電極下方の第
１導電型半導体基体領域自身の低抵抗領域側部分の抵抗
が減少して一層オン抵抗を低減させることが可能とな
る。In the invention according to claim 2, the gate length is increased by forming a high-concentration first-conductivity-type convex region on a low-resistance region corresponding to between each of the adjacent second-conductivity-type base regions. Even when the value is equal to or more than a certain value, the resistance of the first conductive type semiconductor base region below the gate electrode on the low resistance region side is reduced, so that the on-resistance can be further reduced.
【００１３】請求項３記載の発明において、高濃度第１
導電型領域又は高濃度第１導電型凸状領域を、高濃度第
１導電型ドレイン領域と、当該高濃度第１導電型ドレイ
ン領域と対向する第２導電型ベース領域との間には形成
せず、かつ高濃度第１導電型領域又は高濃度第１導電型
凸状領域と高濃度第１導電型ドレイン領域との距離を、
その高濃度第１導電型ドレイン領域と、当該高濃度第１
導電型ドレイン領域と対向する第２導電型ベース領域間
の距離以上に形成することにより、ドレイン・ソース間
等の耐圧を低下させることなく、より一層オン抵抗を低
減することが可能となる。According to the third aspect of the present invention, the high concentration first
A conductive region or a high-concentration first-conductivity-type convex region is formed between the high-concentration first-conductivity-type drain region and the second-conductivity-type base region facing the high-concentration first-conductivity-type drain region. And the distance between the high-concentration first conductivity type region or the high-concentration first conductivity-type convex region and the high-concentration first conductivity-type drain region,
The high-concentration first-conductivity-type drain region;
By forming the conductive region to be longer than the distance between the conductive type drain region and the opposing second conductive type base region, it is possible to further reduce the on-resistance without lowering the breakdown voltage between the drain and the source.
【００１４】[0014]
【実施例】以下、本発明の実施例を図面に基づいて説明
する。図１〜図３は、本発明の第１実施例を示す図であ
る。なお、図１〜図３及び後述の各実施例を示す図にお
いて前記図７、図８における部材及び部位と同一ないし
均等のものは、前記と同一符号を以って示し、重複した
説明を省略する。Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 show a first embodiment of the present invention. In FIGS. 1 to 3 and the drawings showing each embodiment to be described later, the same or equivalent members as those in FIGS. 7 and 8 are denoted by the same reference numerals as those described above, and redundant description is omitted. I do.
【００１５】図１に示すように、本実施例では、隣り合
うＰ型ベース領域５の各間におけるＮ型ドレイン領域４
の表面側に高濃度Ｎ+ 型領域１６が形成されている。こ
のような構成とすることによって、ゲート長をある一定
値以上としても、ゲート電極１０下方のＮ型ドレイン領
域４自身の表面側部分の抵抗が減少して一層オン抵抗を
低減することができる。As shown in FIG. 1, in the present embodiment, an N-type drain region 4 is provided between adjacent P-type base regions 5.
A high concentration N + -type region 16 is formed on the surface side of. With such a configuration, even if the gate length is set to a certain value or more, the resistance of the surface side portion of the N-type drain region 4 below the gate electrode 10 itself is reduced, so that the on-resistance can be further reduced.
【００１６】図２は、高濃度Ｎ+ 型領域１６の形成位置
を平面パターンで示している。同図（ａ）に示すよう
に、ソースセル領域Ｓとソースセル領域Ｓの間（正確に
はＰ型ベース領域５とＰ型ベース領域５の間）の領域に
高濃度Ｎ+ 型領域１６が形成されている。但し、ソース
セル領域Ｓの周辺でドレインセル領域Ｄと対向する領域
には高濃度Ｎ+ 型領域１６は形成していない。また同図
（ｂ）に示されているが、高濃度Ｎ+ 型領域１６とドレ
インセル領域Ｄ（正確には高濃度Ｎ+ 型ドレイン領域
８）間の距離ａは、高濃度Ｎ+ 型領域１６が形成されな
い場合と比較してドレイン・ソース間等の耐圧が低下し
ないだけの距離とする。例えば距離ａをドレインセル領
域Ｄとそれに対向するソースセル領域Ｓとの間の距離ｂ
以上にすれば耐圧の低下は起こらない。FIG. 2 shows the formation positions of the high-concentration N + -type regions 16 in a plane pattern. As shown in FIG. 3A, a high-concentration N + -type region 16 is provided in a region between the source cell regions S (more precisely, between the P-type base regions 5 and 5). Is formed. However, the high-concentration N + -type region 16 is not formed in a region around the source cell region S and facing the drain cell region D. As shown in FIG. 3B, the distance a between the high-concentration N + -type region 16 and the drain cell region D (more precisely, the high-concentration N + -type drain region 8) is equal to the high-concentration N + -type region. The distance is set such that the breakdown voltage between the drain and the source does not decrease as compared with the case where 16 is not formed. For example, the distance a is the distance b between the drain cell region D and the opposing source cell region S.
By doing so, the breakdown voltage does not decrease.
【００１７】ここでソースセル領域Ｓとソースセル領域
Ｓの間の領域に高濃度Ｎ+ 型領域を形成することがスペ
ース的に又はプロセス的に困難な場合には、図３に示す
ように、４つのソースセル領域Ｓに囲まれた領域にのみ
高濃度Ｎ+ 型領域１６ａを形成する。この場合も図２の
場合と同様に、高濃度Ｎ+ 型領域１６ａが形成されない
場合と比較して耐圧を低下させない範囲に高濃度Ｎ+ 型
領域１６ａを形成する。このような構造にすることによ
ってもゲート電極１０下方のＮ型ドレイン領域４自身の
表面側部分の抵抗が減少して一層オン抵抗を低減するこ
とができる。Here, when it is difficult to form a high-concentration N + type region in the region between the source cell regions S in terms of space or process, as shown in FIG. The high-concentration N + -type region 16a is formed only in the region surrounded by the four source cell regions S. Also in this case, as in the case of FIG. 2, the high-concentration N + -type region 16a is formed in a range where the breakdown voltage is not reduced as compared with the case where the high-concentration N + -type region 16a is not formed. Even with such a structure, the resistance of the surface side portion of the N-type drain region 4 below the gate electrode 10 itself is reduced, so that the on-resistance can be further reduced.
【００１８】図４には、本発明の第２実施例を示す。本
実施例では、高濃度Ｎ+ 型領域１６を形成する領域は第
１実施例の場合と同様であるが、ゲート電極１０ａに間
隔を設けることで、高濃度Ｎ+ 型領域１６を高濃度Ｎ+
型ドレイン領域８又は高濃度Ｎ+ 型ソース領域６と同時
に形成することが可能となる。したがってマスク枚数を
増やすことなく高濃度Ｎ+ 型領域１６を形成することが
でき、第１実施例と同様の効果が得られる。FIG. 4 shows a second embodiment of the present invention. In this embodiment, the region for forming the high-concentration N + -type region 16 is the same as that in the first embodiment, but by providing an interval between the gate electrodes 10a, the high-concentration N + -type region 16 is formed. +
It can be formed simultaneously with the type drain region 8 or the high concentration N + type source region 6. Therefore, the high-concentration N + -type region 16 can be formed without increasing the number of masks, and the same effect as in the first embodiment can be obtained.
【００１９】図５には、本発明の第３実施例を示す。上
述の第１及び第２の実施例では、高濃度Ｎ+ 型領域をＮ
型ドレイン領域４の表面側に形成したが、本実施例では
高濃度Ｎ+ 型凸状領域１７をＮ+ 型埋込み層２上に形成
している。高濃度Ｎ+ 型凸状領域１７を形成する平面パ
ターン配置上の位置は、図２で示したようにソースセル
領域Ｓとソースセル領域Ｓの間の領域や、図３で示した
ように４つのソースセル領域Ｓに囲まれた領域であり、
高濃度Ｎ+ 型凸状領域１７を形成することにより耐圧が
低下しないような範囲に形成する。このような構成にす
ることによって、ゲート長をある一定値以上としても、
ゲート電極１０下方のＮ型ドレイン領域４自身のＮ+ 型
埋込み層２側部分の抵抗が減少して一層オン抵抗を低減
させることができる。FIG. 5 shows a third embodiment of the present invention. In the first and second embodiments described above, the high-concentration N + type
Although formed on the surface side of the mold drain region 4, in this embodiment, the high-concentration N + -type convex region 17 is formed on the N + -type buried layer 2. The position of the high-concentration N + -type convex region 17 on the plane pattern arrangement may be a region between the source cell regions S as shown in FIG. 2 or a region between the source cell regions S as shown in FIG. Area surrounded by two source cell areas S,
The high-concentration N + -type convex region 17 is formed in a range where the withstand voltage does not decrease. With this configuration, even if the gate length is set to a certain value or more,
The resistance of the N + -type buried layer 2 side portion of the N-type drain region 4 below the gate electrode 10 itself is reduced, so that the on-resistance can be further reduced.
【００２０】図６には、本発明の第４実施例を示す。本
実施例は第１実施例と第３実施例を合わせたもので、Ｎ
型ドレイン領域４の表面側に高濃度Ｎ+ 型領域１６を形
成し、これと対向するようにＮ+ 型埋込み層２上に高濃
度Ｎ+ 型凸状領域１７を形成したものである。このよう
な構成にすることでさらにオン抵抗を低減することがで
きる。FIG. 6 shows a fourth embodiment of the present invention. This embodiment is a combination of the first embodiment and the third embodiment.
A high-concentration N + -type region 16 is formed on the surface side of the mold drain region 4, and a high-concentration N + -type convex region 17 is formed on the N + -type buried layer 2 so as to face the high-concentration N + -type region 16. With such a configuration, the on-resistance can be further reduced.
【００２１】[0021]
【発明の効果】以上説明したように、請求項１記載の発
明によれば、隣り合う第２導電型ベース領域の各間にお
けるドレイン領域となる第１導電型半導体基体領域の第
１主面側に高濃度第１導電型領域を形成したため、ゲー
ト長をある一定値以上としても、ゲート電極下方の第１
導電型半導体基体領域自身の第１主面側部分の抵抗が減
少して一層オン抵抗を低減させることができる。As described above, according to the first aspect of the present invention, the first main surface side of the first conductive type semiconductor substrate region serving as the drain region between the adjacent second conductive type base regions. Since the high-concentration first conductivity type region is formed in the first region, even if the gate length is set to a certain value or more, the first region below the gate electrode can be removed.
The resistance at the first main surface side portion of the conductive semiconductor substrate region itself is reduced, so that the on-resistance can be further reduced.
【００２２】請求項２記載の発明によれば、隣り合う第
２導電型ベース領域の各間に対応する低抵抗領域上に高
濃度第１導電型凸状領域を形成したため、ゲート長をあ
る一定値以上としても、ゲート電極下方の第１導電型半
導体基体領域自身の低抵抗領域側部分の抵抗が減少して
一層オン抵抗を低減させることができる。According to the second aspect of the present invention, since the high-concentration first-conductivity-type convex region is formed on the low-resistance region corresponding to each space between the adjacent second-conductivity-type base regions, the gate length is fixed. Even when the value is equal to or more than the value, the resistance of the first conductive type semiconductor substrate region below the gate electrode on the low resistance region side is reduced, so that the on-resistance can be further reduced.
【００２３】請求項３記載の発明によれば、高濃度第１
導電型領域又は高濃度第１導電型凸状領域は、高濃度第
１導電型ドレイン領域と、当該高濃度第１導電型ドレイ
ン領域と対向する第２導電型ベース領域との間には形成
せず、かつ高濃度第１導電型領域又は高濃度第１導電型
凸状領域と高濃度第１導電型ドレイン領域との距離は、
高濃度第１導電型ドレイン領域と、当該高濃度第１導電
型ドレイン領域と対向する第２導電型ベース領域間の距
離以上に形成したため、ドレイン・ソース間等の耐圧を
低下させることなく、より一層オン抵抗を低減すること
ができる。According to the third aspect of the present invention, the high concentration first
The conductive type region or the high-concentration first-conductivity-type convex region is formed between the high-concentration first-conductivity-type drain region and the second-conductivity-type base region facing the high-concentration first-conductivity-type drain region. And the distance between the high concentration first conductivity type region or the high concentration first conductivity type convex region and the high concentration first conductivity type drain region is:
Since the high-concentration first-conductivity-type drain region and the second-conductivity-type base region opposed to the high-concentration first-conductivity-type drain region are formed at a distance equal to or greater than that, the breakdown voltage between the drain and the source can be reduced. The on-resistance can be further reduced.
【図１】本発明に係る横型パワーＭＯＳＦＥＴの第１実
施例を示す縦断面図である。FIG. 1 is a longitudinal sectional view showing a first embodiment of a lateral power MOSFET according to the present invention.
【図２】上記第１実施例におけるドレインセル、ソース
セルの平面パターン配置を示す平面図である。FIG. 2 is a plan view showing a planar pattern arrangement of a drain cell and a source cell in the first embodiment.
【図３】上記第１実施例におけるドレインセル、ソース
セルの平面パターン配置の他の例を示す平面図である。FIG. 3 is a plan view showing another example of a planar pattern arrangement of a drain cell and a source cell in the first embodiment.
【図４】本発明の第２実施例を示す縦断面図である。FIG. 4 is a longitudinal sectional view showing a second embodiment of the present invention.
【図５】本発明の第３実施例を示す縦断面図である。FIG. 5 is a longitudinal sectional view showing a third embodiment of the present invention.
【図６】本発明の第４実施例を示す縦断面図である。FIG. 6 is a longitudinal sectional view showing a fourth embodiment of the present invention.
【図７】従来の横型パワーＭＯＳＦＥＴを示す縦断面図
である。FIG. 7 is a longitudinal sectional view showing a conventional horizontal power MOSFET.
【図８】上記従来例におけるドレインセル、ソースセル
の平面パターン配置を示す平面図である。FIG. 8 is a plan view showing a planar pattern arrangement of a drain cell and a source cell in the conventional example.
２ Ｎ+ 型埋込み層（低抵抗領域） ４ Ｎ型ドレイン領域（Ｎ型半導体基体領域） ５ Ｐ型ベース領域 ６ 高濃度Ｎ+ 型ソース領域 ７ 高濃度Ｎ+ 型ドレイン取り出し領域（導通領域） ８ 高濃度Ｎ+ 型ドレイン領域 ９ ゲート絶縁膜 １０ ゲート電極 １２ ソース電極 １３ ドレイン電極 １６ 高濃度Ｎ+ 型領域 １７ 高濃度Ｎ+ 型凸状領域2 N + -type buried layer (low-resistance region) 4 N-type drain region (N-type semiconductor substrate region) 5 P-type base region 6 High-concentration N + -type source region 7 High-concentration N + -type drain extraction region (conduction region) 8 High-concentration N + -type drain region 9 Gate insulating film 10 Gate electrode 12 Source electrode 13 Drain electrode 16 High-concentration N + -type region 17 High-concentration N + -type convex region
フロントページの続き (56)参考文献 特開 昭57−37875（ＪＰ，Ａ) 特開 平２−36561（ＪＰ，Ａ) 特開 平３−87070（ＪＰ，Ａ) 特開 平３−257969（ＪＰ，Ａ) 特開 平５−82782（ＪＰ，Ａ) 特開 平４−258173（ＪＰ，Ａ) 特開 昭59−217368（ＪＰ，Ａ) 特開 昭60−249366（ＪＰ，Ａ) 特開 平６−120510（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/78 H01L 21/336 Continuation of the front page (56) References JP-A-57-37875 (JP, A) JP-A-2-36561 (JP, A) JP-A-3-87070 (JP, A) JP-A-3-257969 (JP) JP-A-5-822782 (JP, A) JP-A-4-258173 (JP, A) JP-A-59-217368 (JP, A) JP-A-60-249366 (JP, A) 6-120510 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 29/78 H01L 21/336
Claims (3)
基体領域の第１主面側にゲート絶縁膜を介して形成され
たゲート電極と、該ゲート電極に設けられたソース開口
部からの二重拡散により形成された第２導電型ベース領
域及び該第２導電型ベース領域内に形成された高濃度第
１導電型ソース領域と、前記ゲート電極に設けられたド
レイン開口部から前記半導体基体領域に電気的に導通を
とるために形成された高濃度第１導電型ドレイン領域
と、前記半導体基体領域における前記第１主面側とは反
対側の第２主面側に形成された低抵抗領域と、該低抵抗
領域と前記高濃度第１導電型ドレイン領域とを低抵抗で
導通させる導通領域とを備え、前記ゲート電極、前記高
濃度第１導電型ソース領域に接続されたソース電極及び
前記高濃度第１導電型ドレイン領域に接続されたドレイ
ン電極の各電極が前記第１主面側に設けられた横型ＭＯ
ＳＦＥＴの構造を有するセルが同一チップ上に複数個配
置されるとともに、該複数個のセルの平面的な配置パタ
ーンは前記ソース開口部に対応するソースセル領域と前
記ドレイン開口部に対応するドレインセル領域とが規則
的に所定のピッチで配置されており、かつ１つのセルに
は中央部に配置された１つのドレインセル領域の周りに
複数個のソースセル領域が２列以上隣り合って設けられ
た構成を有する横型パワーＭＯＳＦＥＴにおいて、隣り
合う前記第２導電型ベース領域の各間における前記半導
体基体領域の第１主面側に高濃度第１導電型領域を形成
してなることを特徴とする横型パワーＭＯＳＦＥＴ。A gate electrode formed on a first main surface side of a semiconductor substrate region of a first conductivity type serving as a drain region via a gate insulating film; A second conductive type base region formed by heavy diffusion, a high-concentration first conductive type source region formed in the second conductive type base region, and a semiconductor substrate region from a drain opening provided in the gate electrode; A high-concentration first-conductivity-type drain region formed for electrical conduction to the semiconductor substrate region; and a low-resistance region formed on a second main surface side of the semiconductor substrate region opposite to the first main surface side. And a conduction region for conducting the low-resistance region and the high-concentration first-conductivity-type drain region with low resistance, wherein the gate electrode, a source electrode connected to the high-concentration first-conductivity-type source region, and High concentration first conductivity type Each of the drain electrodes connected to the drain region has a horizontal MO provided on the first main surface side.
A plurality of cells having the structure of the SFET are arranged on the same chip, and a planar arrangement pattern of the plurality of cells is a source cell region corresponding to the source opening and a drain cell corresponding to the drain opening. Regions are regularly arranged at a predetermined pitch, and in one cell, a plurality of source cell regions are provided adjacent to each other in two or more rows around one drain cell region arranged in the center. In the lateral power MOSFET having the above configuration, a high-concentration first conductivity type region is formed on the first main surface side of the semiconductor base region between the adjacent second conductivity type base regions. Horizontal power MOSFET.
基体領域の第１主面側にゲート絶縁膜を介して形成され
たゲート電極と、該ゲート電極に設けられたソース開口
部からの二重拡散により形成された第２導電型ベース領
域及び該第２導電型ベース領域内に形成された高濃度第
１導電型ソース領域と、前記ゲート電極に設けられたド
レイン開口部から前記半導体基体領域に電気的に導通を
とるために形成された高濃度第１導電型ドレイン領域
と、前記半導体基体領域における前記第１主面側とは反
対側の第２主面側に形成された低抵抗領域と、該低抵抗
領域と前記高濃度第１導電型ドレイン領域とを低抵抗で
導通させる導通領域とを備え、前記ゲート電極、前記高
濃度第１導電型ソース領域に接続されたソース電極及び
前記高濃度第１導電型ドレイン領域に接続されたドレイ
ン電極の各電極が前記第１主面側に設けられた横型ＭＯ
ＳＦＥＴの構造を有するセルが同一チップ上に複数個配
置されるとともに、該複数個のセルの平面的な配置パタ
ーンは前記ソース開口部に対応するソースセル領域と前
記ドレイン開口部に対応するドレインセル領域とが規則
的に所定のピッチで配置されており、かつ１つのセルに
は中央部に配置された１つのドレインセル領域の周りに
複数個のソースセル領域が２列以上隣り合って設けられ
た構成を有する横型パワーＭＯＳＦＥＴにおいて、隣り
合う前記第２導電型ベース領域の各間に対応する前記低
抵抗領域上に高濃度第１導電型凸状領域を形成してなる
ことを特徴とする横型パワーＭＯＳＦＥＴ。2. A gate electrode formed on a first main surface side of a semiconductor substrate region of a first conductivity type serving as a drain region with a gate insulating film interposed therebetween, and a gate electrode formed on a source opening provided in the gate electrode. A second conductive type base region formed by heavy diffusion, a high-concentration first conductive type source region formed in the second conductive type base region, and a semiconductor substrate region from a drain opening provided in the gate electrode; A high-concentration first-conductivity-type drain region formed for electrical conduction to the semiconductor substrate region; and a low-resistance region formed on a second main surface side of the semiconductor substrate region opposite to the first main surface side. And a conduction region for conducting the low-resistance region and the high-concentration first-conductivity-type drain region with low resistance, wherein the gate electrode, a source electrode connected to the high-concentration first-conductivity-type source region, and High concentration first conductivity type Each of the drain electrodes connected to the drain region has a horizontal MO provided on the first main surface side.
A plurality of cells having the structure of the SFET are arranged on the same chip, and a planar arrangement pattern of the plurality of cells is a source cell region corresponding to the source opening and a drain cell corresponding to the drain opening. Regions are regularly arranged at a predetermined pitch, and in one cell, a plurality of source cell regions are provided adjacent to each other in two or more rows around one drain cell region arranged in the center. In the lateral power MOSFET having the configuration described above, a high-concentration first-conductivity-type convex region is formed on the low-resistance region corresponding to between each of the adjacent second-conductivity-type base regions. Power MOSFET.
度第１導電型凸状領域は、前記高濃度第１導電型ドレイ
ン領域と、当該高濃度第１導電型ドレイン領域と対向す
る前記第２導電型ベース領域との間には形成せず、かつ
前記高濃度第１導電型領域又は前記高濃度第１導電型凸
状領域と前記高濃度第１導電型ドレイン領域との距離
は、前記高濃度第１導電型ドレイン領域と、当該高濃度
第１導電型ドレイン領域と対向する前記第２導電型ベー
ス領域間の距離以上に形成してなることを特徴とする請
求項１又は請求項２記載の横型パワーＭＯＳＦＥＴ。3. The high-concentration first-conductivity-type region or the high-concentration first-conductivity-type convex region includes the high-concentration first-conductivity-type drain region and the high-concentration first-conductivity-type drain region. A distance between the high-concentration first conductivity-type region or the high-concentration first conductivity-type convex region and the high-concentration first conductivity-type drain region is not formed between the second conductivity-type base region and the high-concentration first conductivity-type convex region. 2. The high-concentration first-conductivity-type drain region and the second-conductivity-type base region facing the high-concentration first-conductivity-type drain region. 2. The lateral power MOSFET according to 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12783395A JP3301271B2 (en) | 1995-05-26 | 1995-05-26 | Horizontal power MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12783395A JP3301271B2 (en) | 1995-05-26 | 1995-05-26 | Horizontal power MOSFET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08321606A JPH08321606A (en) | 1996-12-03 |
| JP3301271B2 true JP3301271B2 (en) | 2002-07-15 |
Family
ID=14969797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12783395A Expired - Lifetime JP3301271B2 (en) | 1995-05-26 | 1995-05-26 | Horizontal power MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3301271B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4526179B2 (en) * | 2000-11-21 | 2010-08-18 | 三菱電機株式会社 | Semiconductor device |
| JP2008305881A (en) * | 2007-06-06 | 2008-12-18 | Nec Electronics Corp | Semiconductor device |
| JP5739657B2 (en) * | 2010-12-24 | 2015-06-24 | 新電元工業株式会社 | Manufacturing method of semiconductor device |
-
1995
- 1995-05-26 JP JP12783395A patent/JP3301271B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08321606A (en) | 1996-12-03 |
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