JP3346076B2 - Power MOSFET - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a horizontal power MOSFET.
In particular, the present invention relates to an LDMOS having a configuration capable of reducing on-resistance.

[0002]

2. Description of the Related Art As an example of a conventional LDMOS, one having a configuration as shown in FIG. 14 is known. In the figure, an N ⁺ -type buried layer 2 is formed in a main surface of a P-type substrate 1, and a P-type epitaxial layer 3 is formed on one main surface of the P-type substrate 1. N in the P-type epitaxial layer 3
A p-type drain region 4 is formed, and a p-type base region 5 and a high-concentration n ⁺ -type drain region 8 are further formed in the n-type drain region 4. A high-concentration N ⁺ -type source region 6 is formed in the P-type base region 5, and a P-type base between the high-concentration N ⁺ -type source region 6 and the N-type drain region 4 is formed. A gate electrode 10 is formed on the region 5 with a gate insulating film 9 interposed therebetween. Further, a source electrode 12 and a drain electrode 13 are formed insulated from the gate electrode 10 by the first interlayer insulating film 11. The high-concentration N ⁺ -type drain extraction region 7 is formed so as to reach the N ⁺ -type buried layer.

When a voltage is applied to the gate electrode 10 with a voltage applied between the drain electrode 13 and the source electrode 12, the surface of the P-type base region 5 immediately below the gate electrode 10 is inverted to N-type. , N-type channels are formed. A current flows vertically from the high-concentration N ⁺ -type drain region 8 through the high-concentration N ⁺ -type drain extraction region 7, through the N ⁺ -type buried layer 2, through the N-type drain region 4, and the P-type base region 5. Flows into the high-concentration N ⁺ -type source region 6 through the channel region inverted to N-type.

In the structure of this embodiment, since the source electrode, the gate electrode, and the drain electrode are on the same main surface of the semiconductor substrate, there is an effect that a plurality of output transistors can be integrated into one chip. However, since the source electrode and the drain electrode are formed in a stripe shape, the wiring resistance is large, and at the same time, it is difficult to achieve high integration of the channel, and there is a limit in reducing the on-resistance of the device.

As a second example of a conventional LDMOS, one having a configuration as shown in FIG. 15 is known (US Pat. No. 5,129,929).
No. 89). Here, (a) shows the element cross-sectional structure, and (b) shows the planar structure. As shown in FIG. 1A, a source electrode 12 and a second-layer drain electrode 15 are formed insulated by a second-layer interlayer insulating film 14, and as shown in FIG. It is arranged in a hexagon around it.

In this example, by forming the source electrode and the drain electrode in a two-layer structure, the source opening and the drain opening can be formed in a cell shape, and a hexagonal arrangement is adopted. Therefore, there is an effect that the element can be highly integrated and the on-resistance can be reduced. However, in this example, the number ratio between the source cells and the drain cells is 2: 1 and it is difficult to reduce the channel resistance, and there is a limit in reducing the on-resistance.

[0007]

The prior art has the above-mentioned problems. SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art and to provide an LDMOS having a configuration capable of reducing the on-resistance.

[0008]

An object of the present invention is to provide a gate electrode formed on a first principal surface side of a first conductivity type semiconductor substrate serving as a drain region via a gate insulating film, and a gate electrode provided on the gate electrode. A second conductivity type base region formed by double diffusion from the source opening, a high concentration first conductivity type source region formed in the base region, and a drain provided in the gate electrode. A high-concentration first-conductivity-type drain region formed for electrical conduction from the opening to the semiconductor substrate, wherein all of the gate electrode, source, and drain electrodes are on the first main surface side. The so-called horizontal power MOSFET provided has a two-layer wiring structure having a portion in which the source electrode and the drain overlap vertically, and a second main surface opposite to the first main surface of the semiconductor substrate. A low-resistance region formed, and a conduction region for conducting the low-resistance region and the drain electrode with low resistance, wherein the drain opening and the source opening are regularly formed at a predetermined pitch. A source opening formed so as to surround the periphery of the drain opening along a shape similar to the frame of the drain opening, the source opening surrounding the drain opening and the periphery of the drain opening. A gate electrode connecting region for connecting a gate electrode between the drain opening and a gate opening between another drain opening and a source opening surrounding the periphery of the drain opening; and A source opening formed to surround the periphery of the opening, and the drain opening
A power MOSFT in which a plurality of source openings are formed between a source opening formed so as to surround the periphery of another drain opening adjacent to the power MOSFT, or
A power MOSFE having a shape in which each side of the source opening is bent in a plane pattern viewed from the main surface side.
T can be achieved.

[0009]

The operation of the above structure is as follows. The source cell is formed so as to surround the periphery of the opening of the drain cell, so that the degree of channel integration can be improved and the connection region of the gate electrode is provided. However, the above problem can be solved by providing a low resistance N ⁺ type buried layer and a high concentration N ⁺ type drain extraction region.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a power MOSFET having the configuration of the present invention will be specifically described with reference to embodiments.

[0011]

Embodiment 1 FIG. 1 shows a schematic configuration of an embodiment of the present invention. In the figure, (b) is a plane pattern layout, and (a) is AA 'of (b).
It is sectional drawing. First, to describe the configuration (a), N ⁺ -type buried layer in one major surface of the P-type substrate 1 2
Is formed on one main surface of the P-type substrate 1.
A type epitaxial layer 3 is formed. Further, an N-type drain region 4 is formed in the P-type epitaxial layer 3. Further, a P-type base region 5 is provided in the N-type drain region 4.
And a high-concentration N ⁺ -type drain region 8 is formed. Further, a high-concentration N ⁺ -type source region 6 is formed in the P-type base region 5, and a P-type source region 5 between the high-concentration N ⁺ -type source region 6 and the N-type drain region 4 is formed. above,
A gate electrode 10 is formed via a gate insulating film 9. Further, the gate electrode 10 is formed by the first interlayer insulating film 11.
A source electrode 12 and a drain electrode 13 are formed insulated from each other, and a second layer drain electrode 15 is formed insulated from the source electrode 12 by the second interlayer insulating film 14. (B) is a diagram showing the planar arrangement of the source and drain cells. The source cell S is arranged so as to surround the periphery of the drain cell D, and the gate electrode connection region G is formed. It is formed. Based on this pattern arrangement, source cells and drain cells are repeatedly arranged.

When a voltage higher than a threshold is applied to the gate electrode 10 while a positive voltage is applied between the second layer drain electrode 15 and the source electrode 12, the surface of the P-type base region 5 immediately below the gate electrode 10 becomes N The mold is inverted and a channel is formed. In the source cell region facing the drain cell, the current spreads from the high-concentration N ⁺ -type drain region 8 into the N-type drain region 4, and passes through the channel to the high-concentration N ⁺ -type source region 6.
Current flows through In the source cell region not facing the drain cell, a current flows vertically from the high-concentration N ⁺ -type drain region 8 to the high-concentration N ⁺ -type drain extraction region 7, and then flows laterally through the N ⁺ -type buried layer 2. Further, a current flows in the N-type drain region 4 in the vertical direction, and a current flows to the high-concentration N ⁺ -type source region 6 via the channel.

In the above example, the source cell and the drain cell are represented by squares. However, the diffusion concentration is lower at the corners of the cell than at the linear portion of the cell. In some cases, the current flow may be uneven. In such a case, by forming the corners of the cell corners as regular polygons or curves, the profile of the diffusion concentration can be made uniform, and the current distribution can be improved.

In this embodiment, for example, FIG.
As shown in (2), among the source cells arranged in 4 × 4 rows, 2 × 2 central source cells can be formed as a drain cell region, and the periphery of the drain cell can be partially formed as a source cell region. . The buried layer and the drain electrode
The connection is made electrically low resistance by the high-concentration N ⁺ -type drain extraction region 7 formed by diffusion, and therefore, deep diffusion is required. At this time, at the same time, the high-concentration N ⁺ -type drain extraction region also spreads in the horizontal direction. To increase the drain opening area, the area of 2 × 2 source cells is used as the drain opening area. I have. At this time, the number ratio between the source cells and the drain cells is equivalent to 3: 1, the degree of channel integration is improved, and low on-resistance can be achieved. Here, the distance between adjacent source cells cannot be reduced more than necessary because the JFET resistance between the P-type base regions increases. Thus, when the particular L _g> L _s relationship between the gate length L _g and the source length L _s shown in (a) of FIG, circumferential length of the channel by placing the source cell to surround the drain cells This increases the on-resistance easily.

In addition, the distance between the source cell and the drain cell can be reduced to such an extent that the breakdown voltage does not decrease, and the size of the drain cell is formed to be larger than the area equivalent to the area of 2 × 2 source cells. This can reduce the resistance of the high-concentration N ⁺ -type drain extraction region.

[0016]

Embodiment 2 FIG. 2 shows a configuration of a second embodiment of the present invention.
2 shows a plan layout view of the source and drain cells.

Here, the on-resistance of the repeating basic pattern arrangement of the first embodiment and the present embodiment will be considered. First,
For the first embodiment, its on-resistance can be represented by the net shown in FIG. In the figure, arrow X indicates the resistance of the current path flowing through the channel of the source cell facing the drain cell, and R _X1 indicates the channel resistance and the high concentration N ⁺ from the channel.
This is the sum with the spreading resistance up to the drain region of the die. An arrow Y is the resistance of the current path flowing through the channel of the source cell that does not face the drain cell, R _Y1 is the channel resistance, storage layer resistance, the sum of the resistance of the JFET resistance and N-type drain region, R _{implantation 1} the resistance of the N ⁺ -type buried layer, R _preparative is the resistance of the high-concentration N ⁺ -type drain region.

Next, the on-resistance of the repeated basic pattern arrangement of this embodiment can be represented by a net shown in FIG. Here, R _Z1 is the resistance of the current path flowing through the channel of the second source cell not facing the drain cell,
This is the sum of channel resistance, storage layer resistance, JFET resistance, and resistance of the N-type drain region. Further, R _{buried 2} is the resistance of the buried layer.

FIG. 5 shows the relationship between the sheet resistance and the ON resistance of the N ⁺ type buried layer 2 in the first embodiment, this embodiment, and the second conventional example. In this calculation, the gate oxide film thickness is 500 mm, the threshold voltage is 1.7 V, and the gate applied voltage is 12
The specific resistance of the V and N-type drain regions is 0.4 Ωcm, and the depth of the N-type drain region is 4 μm. L _s = 6 μm,
L _{g was set to} 5 μm, and the calculation was made assuming that the extraction resistance per drain cell was 5Ω.

By providing a high-concentration N ⁺ -type drain extraction region, lowering the resistance of the N ⁺ -type buried layer and employing the pattern arrangement of the present invention, it is possible to improve the degree of channel integration and greatly increase the on-resistance. It becomes possible to reduce to. In the pattern arrangement of the present embodiment, the degree of channel integration is improved as compared with the pattern arrangement of the first embodiment, and the channel resistance can be reduced as compared with the case of the first embodiment. However, in the case of the present embodiment, the current path through the buried layer is increased and the resistance of the buried layer is increased as compared with the case of the first embodiment. The configuration of the first embodiment can reduce the on-resistance of the element.

As can be seen from FIG. 5, the lower the sheet resistance of the N ⁺ -type buried layer 2 is, the lower the channel resistance is by increasing the number of source cells surrounding the drain cells. It is advantageous in lowering.
That is, as the resistance on the drain side (the resistance of the N ⁺ type buried layer + the resistance of the drain extraction region) decreases, the channel resistance decreases as the source cell density increases, and the overall resistance can be reduced.

Conversely, if the sheet resistance is above a certain value, even if the number of source cell columns is increased and the channel resistance is reduced,
Rather, the on-resistance of the entire device increases due to the effect of the increase in resistance due to the increase in the distance between the source cell and the drain. Therefore, if the sheet resistance is above a certain value, reduce the number of source cell columns,
Keeping the distance between the source cell and the drain as short as possible can reduce the on-resistance of the entire device. Therefore, the number of source cell columns may be appropriately selected according to the sheet resistance of the N ⁺ type buried layer 2 and the resistance of the drain extraction region.

As described above, according to the present invention, an LDMOS is provided with a low-resistance buried region and a diffusion layer for making the low-resistance buried region and the drain electrode conductive with low resistance. By arranging the source cell so as to surround the cell, the degree of integration of the channel can be significantly improved, and the on-resistance of the element can be drastically reduced.

[0024]

Third Embodiment FIG. 6 shows the configuration of a third embodiment of the present invention. In the figure, a low-resistance silicide layer 16 is formed on one main surface of a P-type substrate 1. By forming the low-resistance silicide layer 16, the resistance of the N ⁺ -type buried layer can be reduced, and the on-resistance of the device can be reduced. The low-resistance silicide layer 16 is formed by forming the low-resistance silicide layer 16 on the P-type substrate 1 by a known method, and then performing wafer bonding with the second P-type substrate and polishing to a predetermined thickness. Obtainable.

[0025]

Embodiment 4 The configuration of a fourth embodiment of the present invention will be described with reference to FIG. In the figure, a trench is formed in the N-type drain region 4, and a low-resistance conductive layer 17 of, for example, low-resistance polycrystalline silicon or Al is formed in the trench, thereby forming a drain electrode 13 and an N ⁺ -type buried layer. The layer 2 is electrically connected. In the configuration of this embodiment, the resistance of the drain extraction region can be reduced, and the on-resistance of the element can be reduced. Further, since the drain extraction region is formed by the trench, the high concentration N
There is no need for diffusion like the ⁺ -type drain extraction region 7, so that the region of the drain cell can be reduced, the degree of integration of elements can be improved, and low on-resistance can be achieved.

[0026]

Fifth and Sixth Embodiments Fifth and sixth embodiments of the present invention will be described with reference to FIG. 8 (plan view) and FIG. 9 (plan view).
The cross-sectional structure taken along the line AA 'in FIGS. 8 and 9 is the same as that in FIG. In the configuration of FIG. 8, two gate connection regions are formed facing the sides of the square drain cell, and in the configuration of FIG. 9, two gate connection regions are formed facing the vertices of the square drain cell. Have been.
In the case of these configurations, since the gate connection region is formed at two places, the gate resistance can be reduced.
The effect is that the switching speed of the power MOSFET can be improved.

[0027]

Seventh Embodiment A seventh embodiment of the present invention will be described with reference to FIG. The cross-sectional structure taken along line AA ′ in FIG.
It has the same structure as (a). In the configuration of FIG. 10, circular source cells are arranged in a regular hexagonal band around a regular hexagonal drain cell. By forming the drain shape as a regular hexagon as in this embodiment, the area of the source cell region can be sufficiently increased while maintaining the distance between the source cells and the drain cells necessary for preventing the withstand voltage between the drain and the source of the element from being lowered. This is the closest pattern arrangement that can be used.

[0028]

Embodiment 8 An eighth embodiment of the present invention will be described with reference to FIG. In the figure, (b) is a plan pattern layout diagram, (a) is a diagram showing a cross-sectional structure taken along BB 'of (b), and (b) is a cross-sectional structure taken along AA' of Example 1. Same as a). In the section AA ′, the P-type base region 5 and the high-concentration N ⁺ -type source region 6 are connected to the source electrode at the same time.
There was a limit to reducing L _s . However, section BB '
Since unnecessary connection between the P-type base region and the source electrode in, enables reduction of the source length L _s, the result,
Since the zigzag source region as shown in FIG. 11 can be used, the peripheral length of the channel per unit area can be improved, and the on-resistance of the element can be further reduced.

[0029]

Embodiment 9 A ninth embodiment of the present invention will be described with reference to FIG. In the drawings, (b) is a plan pattern layout diagram, and (a) is a cross-sectional structure diagram along CC ′ in (b). Note that the cross-sectional structure taken along the line BB 'in (b) is the same as that in (a) of FIG. In this embodiment, source cells are arranged so as to surround three drain cells, and are repeatedly arranged based on the pattern. In this embodiment, the P-type base region and the source electrode 'connected by cross-section portion cross section B-B' section C-C is reduced to the source length L _s, to reduce the repetition pitch of the basic pattern Therefore, the peripheral length of the channel per unit area can be improved, and the on-resistance of the device can be further reduced.

[0030]

[Embodiment 10] A tenth embodiment of the present invention will be described with reference to FIG. In the drawing, the cross-sectional structure taken along the line AA ′ is the same as FIG. In this embodiment, the drain cells are regularly arranged in the source cells arranged in a stripe shape. In the case of the present embodiment, two rows of stripe-shaped source cells are arranged between the drain cells. However, as described in the description of FIG. 5, the stripe-shaped source cells are arranged depending on the sheet resistance of the buried layer. The number of shape source columns can be changed.

[0031]

As described above, as described above, the power MOSFET
By using the MOSFET according to the present invention as a structure of the present invention, it was possible to solve the problems of the prior art and provide an LDMOS having a structure capable of reducing the on-resistance. That is, to improve the integration density of the channel by forming a source cell so as to surround the periphery of the opening of the drain cell and a connecting region of the gate electrode, the low-resistance N ⁺ -type buried layer and a high concentration N By providing a ⁺ -type drain extraction region, the problems of the prior art could be solved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment, (a) is a cross-sectional view,
(B) is a plan pattern layout , and (c) is other than the drain region.
FIG . 3 is a plan view showing the shape of the pattern .

FIG. 2 is a plan pattern layout diagram of a second embodiment.

FIG. 3 is a diagram showing an on-resistance of a repeated basic pattern arrangement of the first embodiment by a resistance net.

FIG. 4 is a diagram showing an on-resistance of a repeated basic pattern arrangement according to a second embodiment by a resistance net;

FIG. 5 is a diagram showing the relationship between the ON resistance and the sheet resistance of an N ⁺ type buried layer.

FIG. 6 is a cross-sectional view illustrating a configuration of a third embodiment.

FIG. 7 is a cross-sectional view illustrating a configuration of a fourth embodiment.

FIG. 8 is a diagram illustrating a planar pattern arrangement according to a fifth embodiment.

FIG. 9 is a diagram illustrating a planar pattern arrangement according to a sixth embodiment.

FIG. 10 is a diagram showing a planar pattern arrangement according to a seventh embodiment.

FIGS. 11A and 11B are diagrams showing a configuration of an eighth embodiment, in which FIG.
(b) is a plan pattern layout diagram.

FIGS. 12A and 12B are diagrams showing a configuration of Example 9; FIG.
(b) is a plan pattern layout diagram.

FIG. 13 is a diagram showing a plane pattern arrangement according to a tenth embodiment.

FIG. 14 is a sectional view showing a configuration of a first conventional example.

15A and 15B are diagrams showing a configuration of a second conventional example, in which FIG. 15A is a cross-sectional view, and FIG. 15B is a plan pattern layout diagram.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P type substrate, 2 ... N ⁺ type buried layer, 3 ... P type epitaxial layer, 4 ... N type drain region, 5 ... P type base region, 6 ... High concentration N ⁺ type source region, 7 ... High concentration N ⁺ Type drain extraction region, 8 ... high concentration N ⁺ type drain region, 9
... gate insulating film, 10 ... gate electrode, 11 ... first layer interlayer insulating film, 12 ... source electrode, 13 ... drain electrode, 14 ... second layer interlayer insulating film, 15 ... second layer drain electrode, 16 ... low resistance Silicide layer, 17 ... Low resistance conductive layer.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-1-119177 (JP, A) JP-A-2-36561 (JP, A) JP-A-3-257969 (JP, A) JP-A-4- 123456 (JP, A) JP-A-4-171764 (JP, A) JP-A-5-82278 (JP, A) JP-A-51-110279 (JP, A) JP-A-53-112680 (JP, A) JP-A-57-37875 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 29/78 652 H01L 21/336

Claims (2)

(57) [Claims] 1. A gate electrode formed on a first main surface side of a semiconductor substrate of a first conductivity type serving as a drain region via a gate insulating film, and a gate electrode formed on the gate electrode through a source opening provided in the gate electrode. A second conductive type base region formed by diffusion, a high-concentration first conductive type source region formed in the base region, and a drain opening also provided in the gate electrode are electrically connected to the semiconductor substrate. A high-concentration first-conductivity-type drain region formed in order to establish electrical conduction, wherein the gate electrode, source and drain electrodes are all provided on the first main surface side, so-called lateral power.
The MOSFET has a two-layer wiring structure having a portion in which the source electrode and the drain electrode are vertically overlapped,
A low-resistance region formed on a second main surface opposite to the first main surface of the semiconductor substrate, and a conduction region for conducting the low-resistance region and the drain electrode with low resistance, The drain opening and the source opening are regularly arranged at a predetermined pitch, and the source opening is formed so as to surround the periphery of the drain opening along a shape similar to the frame of the drain opening. A gate electrode between the drain opening and a source opening surrounding the drain opening, and a gate electrode between another drain opening and the source opening surrounding the drain opening. a gate electrode connecting region for connection, and so as to surround the source opening portion formed so as to surround the periphery of the drain opening, the periphery of the other of the drain opening adjacent to the drain opening Between the source opening made, the power MOSFET, wherein a plurality of source openings are formed. 2. The power MOSFET according to claim 1, wherein the source opening has a zigzag shape in a plane pattern viewed from the first main surface side.