JPH09153615A - High breakdown voltage semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high breakdown voltage semiconductor device in which the channel width below a gate electrode may be enlarged without increasing the contact resistance of a source electrode, by forming a channel between adjacent first conduction type source layers. SOLUTION: A plurality of island-like first conduction type source layers 3 are formed on the surface of a second conduction type base layer, and gate electrodes are formed between the adjacent first conduction type source layers 3. Therefore, channels are formed also between the first conduction type source layers 3. Thus, the effective channel width may be enlarged in comparison with a conventional high breakdown voltage semiconductor device in which a gate electrode 8 and hence a channel are formed only between the first conduction type source layer 3 and a first conduction type drift layer 5. Therefore, lower on-resistance may be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage semiconductor device, and more particularly to a lateral high breakdown voltage semiconductor device having an island-shaped source electrode.

[0002]

2. Description of the Related Art Conventionally, a power IC is known in which a high breakdown voltage semiconductor element used for a high breakdown voltage drive circuit and a low breakdown voltage semiconductor element used for a low breakdown voltage drive circuit are formed on the same substrate. And many uses are considered.
High breakdown voltage MOS used in the output stage of this type of power IC
FETs are required to have low on-resistance.

FIG. 21 is a plan view showing the element structure of this type of high breakdown voltage MOSFET, and FIG. 22 is a plan view of FIG.
It is a sectional view taken along the line XXII.

In the figure, reference numeral 101 indicates a high-resistance p-type semiconductor substrate, and a p-type semiconductor substrate 101 has a p-type on its surface.
The mold base layer 102 is selectively formed. A low resistance n-type source layer 103 is formed on the surface of the p-type base layer 102. p-type base layer 1 of p-type semiconductor substrate 101
On the surface different from 02, a low resistance n-type drain layer 10 is formed.
4 are provided. The n-type drain layer 104 is formed in the high-resistance n-type drift layer 105.

Gate oxidation is performed on the surface of the p-type base layer 102 sandwiched between the n-type source layer 103 and the n-type drift layer 105 and a part of the surface of the n-type drift layer 105 adjacent to this surface. Film 106 and field oxide film 1
The gate electrode 108 is formed via 07. Further, reference numeral 109 indicates a source electrode in contact with the n-type source layer 103, and reference numeral 110 indicates the n-type drain layer 1.
The drain electrode in contact with 04 is shown.

The plane shape of these layers and electrodes is a stripe shape as shown in FIG.

High breakdown voltage MOSFET configured as described above
Since the n-type drain layer 104 is formed in the n-type drift layer 105, the breakdown voltage is higher than that of a normal MOSFET.

[0008]

However, FIG.
And in the conventional high breakdown voltage MOSFET shown in FIG. 22,
In order to increase the current capacity while maintaining the same area, it is necessary to increase the current density per unit area. In other words, it is necessary to reduce the on resistance. To reduce the on-resistance, it is effective to widen the effective channel width. However, the conventional high breakdown voltage M shown in FIGS.
In the OSFET, the width of the channel region formed under the gate electrode 108 is constant. Therefore, there is a problem that a sufficiently low on-resistance cannot be obtained.

Next, the conventional high breakdown voltage MOSF as described above is used.
The ET wiring method will be described. Conventional high voltage MOS
In the FET, as shown in FIG. 21, the source electrode 109, the gate electrode 108, and the drain electrode 110 are arranged in a stripe shape.

Each of these electrodes 108 to 110 functions as a lower layer wiring, and each lower layer wiring is individually connected to each pad (not shown) through the upper layer wiring. There are two types of structures, a parallel wiring system and an orthogonal wiring system, as the two-layer wiring composed of the lower layer wiring and the upper layer wiring.

The parallel wiring system shows a structure in which the upper layer wiring is arranged parallel to the longitudinal direction of the lower layer wiring, and has an advantage that the contact area between the lower layer wiring and the upper layer wiring can be widened. However, in the parallel wiring method, since the upper layer wiring is generally formed of aluminum having a large film thickness, it is necessary to make a large gap between the wirings. Therefore, even if the element is miniaturized, the pitch between the source and the drain is small. There is a problem that cannot be done.

On the other hand, the orthogonal wiring system shows a structure in which upper layer wirings So and Do are arranged perpendicularly to the longitudinal direction of the lower layer wirings (109, 110) as shown in FIG. Can be set to an arbitrary value, which has an advantage that the pitch between the source and the drain can be reduced with the miniaturization of the element.

However, in the orthogonal wiring system, the through hole between the lower layer wiring (109, 110) and the upper layer wiring So, Do, the lower layer wiring and the n-type source layer 103 or n.
When the contact hole with the type drain layer 104 is arranged so as to overlap, as shown in FIG. 24, a recess is formed in the lower wiring surface of the contact hole region, and the impurity Ip remains in this recess, There is a problem of increasing wiring resistance. Therefore, in the orthogonal wiring method, there is a restriction that the through hole and the contact hole cannot be arranged in an overlapping manner.

However, according to this restriction, even if the through hole is formed so as not to overlap the contact hole, the lower layer wiring (109, 110) and the upper layer wiring So,
The area of the through hole from Do is reduced, which causes a problem of increasing the wiring resistance of the through hole. Further, if the area of the contact hole is reduced in order to increase the area of the through hole, the contact resistance will increase, and as a result, the on-resistance of the entire device will increase.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a high breakdown voltage semiconductor device capable of obtaining a low ON resistance.

More specifically, an object of the present invention is to provide a high breakdown voltage semiconductor device capable of expanding the channel width under the gate electrode without increasing the contact resistance of the source electrode.

Another object of the present invention is to provide a high breakdown voltage semiconductor device as described above, which has a two-layer wiring having a low wiring resistance and is suitable for miniaturization and integration.

[0018]

In order to achieve the above object, in a first high breakdown voltage semiconductor device according to the present invention, a high resistance semiconductor layer and a first high resistance semiconductor layer selectively formed on the surface of the high resistance semiconductor layer. A first conductivity type drift layer, a drain layer formed on the surface of the first conductivity type drift layer, and a second conductivity type base layer selectively formed on the surface of the high resistance semiconductor layer,
A first conductivity type source layer formed in a plurality of islands on the surface of the second conductivity type base layer, and between the first conductivity type source layer and the first conductivity type drift layer and adjacent to each other. A gate electrode formed on the second conductive type base layer between the first conductive type source layers via a gate insulating film, a drain electrode contacting the drain layer, the first conductive type source layer and the second conductive layer. And a source electrode that contacts both of the conductivity type base layers.

According to the present invention, the first-conductivity-type source layer is formed on the surface of the second-conductivity-type base layer in the form of a plurality of islands, and the adjacent first-conductivity-type source layer is also gated. Since the gate electrode is formed, a channel is also formed between the first conductivity type source layers. Therefore, the effective channel width can be increased as compared with the conventional high breakdown voltage semiconductor device in which the gate electrode is formed only between the first conductivity type source layer and the first conductivity type drift layer to form the channel. Therefore, low on-resistance can be obtained.

A second high breakdown voltage semiconductor device according to the present invention is a high resistance semiconductor layer, a first conductivity type drift layer selectively formed on a surface of the high resistance semiconductor layer, and the first high resistance semiconductor layer.
A drain layer formed in a substantially stripe shape on the surface of the conductivity type drift layer, a second conductivity type base layer selectively formed on the surface of the high resistance semiconductor layer, and a second conductivity type base layer. Between a first conductivity type source layer formed on the surface and arranged in a plurality of islands substantially parallel to the stripe direction of the drain layer, and between the first conductivity type source layer and the first conductivity type drift layer And a gate electrode formed on the second conductive type base layer between the adjacent first conductive type source layers via a gate insulating film, a drain electrode in contact with the drain layer, and the first conductive type source layer. And a source electrode in contact with both the second conductive type base layer.

As described above, when the first conductivity type source layer is formed in a plurality of islands, the drain layer is formed in a substantially stripe shape as in the conventional case, and the first layer is formed substantially parallel to the stripe direction.
The conductive type source layers may be formed in an array. By using this form, the high breakdown voltage semiconductor device according to the present invention can be formed without significantly changing the conventional design.

Further, a third high breakdown voltage semiconductor device according to the present invention is a substrate, an insulating film formed on the substrate, a high resistance semiconductor layer formed on the insulating film, and the high resistance semiconductor. A first conductivity type drift layer selectively formed on a surface of the layer, a drain layer formed in a substantially stripe shape on the surface of the first conductivity type drift layer, and a surface of the high resistance semiconductor layer. Formed on the surface of the second conductivity type base layer and a first conductivity type source arranged in the form of a plurality of islands substantially parallel to the stripe direction of the drain layer. And a second conductive type base layer between the first conductive type source layer and the first conductive type drift layer and between the adjacent first conductive type source layers. Contact with the gate electrode and the drain layer That the drain electrode, and a source electrode that contacts both of the first conductivity type source layer and the second conductivity type base layer.

That is, a so-called SOI structure in which a high resistance semiconductor layer is formed on an insulating film formed on a substrate is applied. This facilitates isolation between elements, and makes it possible to have very effective resistance to noise. In this SOI structure, the first conductivity type drift layer is formed so as not to reach the insulating film.

In these high breakdown voltage semiconductor devices according to the present invention, the length of the gate electrode formed on the source layer of the first conductivity type in the stripe direction is x, and the direction of the source layer of the first conductivity type is the stripe direction. It is preferable from the viewpoint of reducing the ON resistance without increasing the contact resistance that the relationship of 4.5 μm ≦ x + y ≦ 100 μm is satisfied, where y is y.

Similarly, when the length in the stripe direction of the gate electrodes formed between the adjacent first conductivity type source layers is x, it is necessary that the relationship of 1.5 μm ≦ x ≦ 4 μm is satisfied. It is preferable from the viewpoint of reducing the on-resistance without increasing the resistance.

The first conductivity type drift layer may also be formed between the second conductivity type base layers so as to contact the gate insulating film. In this case, the channel resistance of the adjacent second conductivity type base layer portions can be reduced, and the channel between the source and drain and the threshold voltage can be easily aligned.

Further, the drain layer may be of the first conductivity type or the second conductivity type. The high breakdown voltage semiconductor device according to the present invention is a high breakdown voltage MOS device when the drain layer is of the first conductivity type.
It becomes an FET and becomes a high breakdown voltage IGBT when the drain layer is of the second conductivity type.

The high breakdown voltage semiconductor device according to the present invention is
The drain electrode is formed in an array in a plurality of islands, and further, a lower layer source wiring that electrically connects adjacent source electrodes via the upper side of the gate electrode without making contact with the gate electrode, and the lower layer. An upper layer source wiring having a longitudinal direction in a direction orthogonal to the source wiring and contacting an upper portion of the lower layer source wiring above the gate electrode, and the drain layer not being in contact with the drain layer above, A lower layer drain wiring electrically connecting adjacent drain electrodes, and an upper layer drain wiring having a longitudinal direction in a direction orthogonal to the lower layer drain wiring and contacting an upper portion of the lower layer drain wiring above the drain layer. It is also possible to adopt an orthogonal wiring structure provided with.

As a result, in addition to the effect of reducing the on-resistance of the element itself, the wiring resistance does not increase even if the orthogonal wiring structure is formed, so that the on-resistance can be further reduced.
Further, since the wiring resistance is not increased even if the orthogonal wiring structure is formed, it is suitable for miniaturization and integration.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
2A is a plan view showing the element structure of the high breakdown voltage MOSFET according to the embodiment of FIG. 2, and FIG. 2A is a sectional view taken along the line IIA-IIA of FIG. 2B is a sectional view taken along the line IIB-IIB of FIG. In the present embodiment, the first conductivity type is n-type and the second conductivity type is p-type. The same applies to the following embodiments.

In the figure, the p-type semiconductor layer 1 is a high-resistance p-type Si layer.
A p-type base layer 2 having a thickness of about 1 μm is selectively formed on the surface of the p-type semiconductor layer 1. p
An n-type source layer 3 having a low resistance and a thickness of about 0.3 μm is formed on the surface of the type base layer 2. The surface of the p-type semiconductor layer 1 different from the p-type base layer 2 has a low resistance and a thickness of 0.
The n-type drain layer 4 having a thickness of about 3 μm is formed in a substantially stripe shape. The n-type drain layer 4 is formed in the n-type drift layer 5 having a high resistance and a thickness of about 1.5 μm. As shown in FIG. 2A, on the surface of the p-type base layer 2 sandwiched by the n-type source layer 3 and the n-type drift layer 5, and on a part of the surface of the n-type drift layer 5 adjacent to this surface. The gate electrode 8 is formed via the gate oxide film 6 and the field oxide film 7. Below the gate electrode 8, p sandwiched between the n-type source layer 3 and the n-type drift layer 5 is formed.
The channel formed on the surface of the mold base layer 2 has a length of 0.7.
It is about μm.

Similarly, as shown in FIG. 2B, the gate electrode 8 is also formed on the surface of the p-type base layer 2 between the adjacent n-type source layers 3 via the gate oxide film 6. Has been formed. Among the dimensions of the gate electrode 8, the length x between the n-type source layers 3 along the stripe direction is about 2 μm. The n-type drift layer 5 is also formed between the n-type source layers 3. A source electrode 9 is formed on the n-type source layer 3. A drain electrode 10 is formed on the n-type drain layer 4. Further, a p-type contact layer 11 having a low resistance is formed under the center of the source electrode 9 to obtain a good contact.

Further, if the channel length is made too long, the on-resistance increases, so the thickness of the p-type base layer 2 formed by double diffusion is preferably 1.5 μm or less.

This high breakdown voltage MOSFET is characterized in that the n-type source layer 3 on the surface of the p-type base layer 2 is formed into a plurality of rectangular or square islands, and each of the island-shaped n-type source layers 3 has a stripe shape. That is, they are arranged and formed substantially parallel to the stripe direction of the drain layer 4.

In this high breakdown voltage MOSFET, since the n-type source layers 3 are arranged in an island shape, the gate electrode 8 can be formed between the adjacent n-type source layers 3 as shown in FIG. 2B. , A channel can be formed between the n-type source layers 3 on the surface of the p-type base layer 2 below the gate electrode 8, so that the effective channel width can be widened as compared with the conventional case.
On-resistance can be reduced.

Next, the conditions for widening the channel width required to reduce the on-resistance will be described. In order to increase the channel width, it is important to define the lengths x, y and z shown in FIG. However, x is the length of the gate electrode corresponding to the interval between the adjacent n-type source layers 3. y is the length along the stripe direction of the n-type source layer 3 surrounded by the gate electrode 8. z is the length of the gate electrode corresponding to the width of the adjacent n-type source layer 3, which is indicated by the direction orthogonal to x.

Here, x, y and z are expressed by the following equation (1).
From the viewpoint of reducing the on-resistance, it is preferable that the formula (5) be defined.

4.5 μm ≦ x + y ≦ 100 μm (1) 1.5 μm ≦ x ≦ 4 μm (2) 3 μm ≦ y ≦ 98.5 μm (3) 3 μm ≦ z ≦ 6 μm (4) x <z ... ( 5) When one pitch (x + y) composed of the length y of the n-type source layer 3 and the length x of the gate electrode 8 is larger than 100 μm,
The source electrode 9 becomes closer to the conventional stripe shape than the island shape according to the present invention. Therefore, the value of the on-resistance becomes almost the same as the conventional one, and the reduction amount of the on-resistance according to the present invention falls within the range of manufacturing error. Therefore, x + y is 100
It is preferably equal to or less than μm (x + y ≦ 100 μm ... the upper limit of the expression (1)).

If the length x is shorter than 1.5 μm, the channel width of the portion x becomes narrow and the channel resistance becomes high. Therefore, the length x is preferably 1.5 μm or more. Length x
When it exceeds 4 μm, the number of source electrodes 9 per unit area decreases, and as a result, the contact area of the source electrode 9 decreases and the contact resistance increases, so the length x is preferably 4 μm or less (1. 5 μm ≦ x ≦ 4 μm ...
Formula (2)).

Even if the length y is shorter than 3 μm, the contact area of the source electrode 9 is reduced and the contact resistance is increased. Therefore, the length y is preferably 3 μm or more. Further, x + y is preferably 100 μm or less, and the length x is preferably 1.5 μm or more, so that the length y is 98.m.
It is preferably 5 μm or less (3 μm ≦ y ≦ 98.5 μm ...
Equation (3)).

Since the length y is preferably 3 μm or more and the length x is preferably 1.5 μm or more, x + y is preferably 4.5 μm or more (4.5 μm ≦ x + y ...
(Lower limit of equation (1)).

In addition to this, when the length z exceeds 3 μm,
Since the contact resistance becomes high, the length z is preferably 3 μm or more. Since the on-resistance increases when the length z exceeds 6 μm, the length z is preferably 6 μm or less (3 μm ≦
z ≦ 6 μm (4)).

In the present invention, since the depth indicated by the length z is formed in the gate electrode 8 to widen the channel width, when x is compared with z, the present invention shows that x is long and z is short. Since such a channel width does not become wider than the conventional channel width, it is preferable to make z longer than x.

As described above, by complying with the equations (1) to (5), the high breakdown voltage MOSFE according to the present embodiment is obtained.
T can widen the effective channel width without increasing the contact resistance, and can easily and reliably reduce the on-resistance.

Further, in this high breakdown voltage MOSFET, since the area of the gate electrode 8 is larger than in the conventional case, the gate resistance can be reduced and the switching speed can be improved.

Further, the expression (2) defines that the interval between the n-type source layers 3 is 4 μm or less, which means that the high breakdown voltage MOSFET according to the present invention is formed finer than the vertical MOSFET. It is shown that. Because vertical MO
In the SFET, as shown in FIG. 3, the electron current due to the electrons injected from the adjacent n-type source layer 3'is concentrated in the portion 5a immediately below the gate electrode 8'to generate heat and the resistance of the element is increased. This is because it is necessary to set the distance between the n-type source layers 3 ′ to 5 μm or more in order to prevent this. That is,
The high breakdown voltage MOSFET according to the present invention is a vertical MOSFET.
Compared with, it is suitable for miniaturization and can be manufactured with a high degree of integration.

(Second Embodiment) Next, the second embodiment of the present invention will be described.
The high breakdown voltage MOSFET according to the embodiment will be described. FIG. 4 is a plan view showing the device structure of this high breakdown voltage MOSFET, and FIG. 5A is a sectional view taken along the line VA-VA in FIG. 5B is a sectional view taken along the line VB-VB of FIG. The same parts as those in FIGS. 1, 2A and 2B are designated by the same reference numerals and detailed description thereof will be omitted. Only different parts will be described here, but the same applies to the following embodiments. is there.

That is, the high breakdown voltage MO according to the present embodiment.
The SFET differs from that of the first embodiment in that FIG.
As shown in, adjacent p-type base layers 2 are formed apart from each other, and an n-type drift layer 5 is formed on the surface between the p-type base layers 2 so as to be exposed.

As a result, the channel resistance of this portion can be reduced. In addition, since the adjacent p-type base layers 2 are separated so as not to overlap each other, as shown in FIG.
It becomes easy to align the threshold voltage with the channel in the portion shown in (a).

As described above, according to the second embodiment, in addition to the effects of the first embodiment, the channel resistance of the adjacent p-type base layer 2 portions can be reduced, and the source-drain area can be reduced. The channel and the threshold voltage can be easily aligned.

(Third Embodiment) Next, the third embodiment of the present invention will be described.
The high breakdown voltage MOSFET according to the embodiment will be described. FIG. 6 is a plan view showing the device structure of this high breakdown voltage MOSFET, and FIG. 7A is a sectional view taken along the line VIIA-VIIA in FIG. FIG. 7B shows VII B-VII in FIG.
FIG. 3 is a cross-sectional view taken along line B.

High breakdown voltage MOSFET according to the present embodiment
Is different from the first embodiment in that a so-called SOI (silicon on ins) having a p-type semiconductor layer 1 on an oxide film 13 formed on a p-type Si substrate 12 and having a thickness of about 0.5 μm is used.
ulator) structure.

In this case, the thickness of the p-type semiconductor layer 1 is set to 2-5.
.mu.m, the thickness of the n-type drift layer 5 is 1.5 because the n-type drift layer 5 does not reach the oxide film 13.
μm or less is preferred. From the viewpoint of providing the element with a withstand voltage, the thickness of the n-type drift layer 5 is preferably 0.8 μm or more.

High breakdown voltage MOSFET according to the present embodiment
Is formed with such an SOI structure, elements can be easily separated from each other, and sufficient resistance to noise can be obtained.

Next, a high breakdown voltage MOSFE of this SOI structure
At T, the relationship between the ON resistance and the length of one pitch represented by x + y described above will be described with reference to FIG. FIG.
In the figure, the horizontal axis represents the impurity concentration of the n-type drift layer 5, and the vertical axis represents the relative value of the on-resistance. Further, FIG. 8 shows a comparison between the case where one pitch is 8.4 μm or 22.8 μm and the case where the source layer 3 has a stripe shape as in the conventional case. When 1 pitch is 8.4 μm, x = 2 μ
m and y = 6.4 μm. When one pitch is 22.8 μm, x = 2 μm. y = 20.8 μm.

As can be seen from FIG. 8, the n-type drift layer 5
The on-resistance is reduced in proportion to the increase of the impurity concentration and in proportion to the pitch shortness. Specifically, one pitch is 22.8 as compared with the ON resistance in the stripe shape.
When μm, the ON resistance is reduced by about 8%, and one pitch is 8.
At 4 μm, it is reduced by about 20%.

Although not shown, x = 2 μm. y = 3
When the pitch is 8 μm and one pitch is 40 μm, the on-resistance is reduced by about 5%. Furthermore, x = 2 μm. When y = 98 μm and one pitch is 100 μm, the on-resistance is reduced by about 2%. When one pitch exceeds 100 μm, the value of the on-resistance becomes almost the same as the conventional one, and the definition of the equation (1) is derived as described above. Note that the other formulas (2) to (5) are similarly derived.

That is, the high breakdown voltage MO according to the present embodiment.
The SFET is similar to the first embodiment in the formula (1)-
It is preferable to follow the rule shown in the equation (5).

As described above, according to the third embodiment, in addition to the effects of the first embodiment, the SOI structure allows the elements to be easily separated from each other and has sufficient resistance to noise. You can

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described.
The high breakdown voltage MOSFET according to the embodiment will be described with reference to FIG.

That is, the high breakdown voltage MO according to the present embodiment.
The SFET is a combination of the second and third embodiments, and in addition to the planar configuration shown in FIG.
The SOI structure shown in FIG. 9A instead of FIG. 9A and shown in FIG. 9B instead of FIG. 7B is formed, and adjacent p-type base layers 2 are formed apart from each other. The n-type drift layer 5 is exposed and formed on the surface between the p-type base layers 2.

With this structure, the effects of the second and third embodiments can be obtained at the same time.

(Fifth Embodiment) Next, the fifth embodiment of the present invention will be described.
FIG. 2 of the high breakdown voltage MOSFET according to the embodiment of FIG.
This will be described with reference to the sectional views of (a) and FIG. 2 (b). FIG. 10 is a plan view showing the element structure of this high breakdown voltage MOSFET.

That is, the high breakdown voltage MO according to the present embodiment.
The SFET is a modification of the first embodiment and is shown in FIG.
As shown in 0, the drain electrode 10 is formed in an island shape so as to face the source electrode 9.

With the above structure, the same effect as that of the first embodiment can be obtained.

The high breakdown voltage MOSFET having the planar structure shown in FIG. 10 is replaced with the sectional structure of FIGS. 2A and 2B, and any sectional structure of the second to fourth embodiments is used. Even if it is transformed into an element having, the same effect as that of the corresponding embodiment can be obtained. Note that the drain electrode 10 has an island shape in any modified configuration.

(Sixth Embodiment) Next, the sixth embodiment of the present invention will be described.
FIG. 2 of the high breakdown voltage MOSFET according to the embodiment of FIG.
This will be described with reference to the sectional views of (a) and FIG. 2 (b). 11 is a plan view showing the device structure of this high breakdown voltage MOSFET, and FIG. 12 is a sectional view taken along the line XII-XII in FIG.

That is, the high breakdown voltage MO according to the present embodiment.
The SFET is a modification of the first embodiment and is shown in FIG.
1, FIG. 12, FIG. 2 (a) and FIG. 2 (b),
The drain electrode 10 is formed in an island shape so as to face the source electrode 9, and the gate electrode is in a mesh shape so as to surround the island-shaped drain electrode 10 together with the surrounding n-type drift layer 4 and the n-type drain layer 5. Is formed in.

With the above structure, the same effect as in the first embodiment can be obtained, and the area of the gate electrode 8 can be increased, so that the switching speed can be improved.

Further, the high breakdown voltage MOSF according to the present embodiment.
Even if the ET is transformed into an element having any of the cross-sectional structures of the second to fourth embodiments instead of the cross-sectional structure shown in FIGS. 2A and 2B, the corresponding embodiment It is possible to obtain the same effect as described above, and further, it is possible to improve the switching speed as described above.

(Seventh Embodiment) Next, the seventh embodiment of the present invention will be described.
The high breakdown voltage MOSFET according to the embodiment will be described. 13 is a plan view showing the structure of this high breakdown voltage MOSFET, and FIG. 14 is a sectional view taken along the line XIV-XIV in FIG. FIG. 15 is a sectional view taken along line XV-XV of FIG.

That is, the high breakdown voltage MO according to the present embodiment.
The SFET is a high breakdown voltage MOSFET according to the fifth embodiment.
This is a configuration in which a two-layer wiring is formed on T.

Specifically, as shown in FIGS. 13 to 15, the insulating film 14 covering the gate electrode 8 and the upper part of the insulating film 14 above the gate electrode 8 are contacted so as to be insulated from the gate electrode 8. , A lower layer source wiring S1 for electrically connecting adjacent source electrodes 9 and the lower layer source wiring S1.
An upper-layer source wiring S2 having a longitudinal direction orthogonal to the upper electrode of the lower-layer source wiring S1 above the gate electrode 8, and an insulating film 15 covering the n-type drain layer around each drain electrode 10. , A lower layer drain wiring D1 which contacts the upper portion of the insulating film 15 above the n-type drain layer 4 so as to be insulated from the n-type drain layer 4 and electrically connects adjacent drain electrodes 10 to each other, and the lower layer drain wiring D1. It has a longitudinal direction orthogonal to D1 and includes an upper drain wiring D2 which contacts the upper portion of the lower drain wiring D1 above the n-type drain layer 4.

The lower layer wirings S1 and D1 and the upper layer wiring S
An interlayer insulating film 16 is formed between the electrodes 2 and D2.
Further, Al is used for each wiring S1, S2, D1, D2.

Here, the lower layer source wiring S1 and the lower layer drain wiring D1 are designed to have substantially the same width, for example, each has a width of 5 μm and is arranged alternately in parallel at intervals of 1 μm. Has been formed.

The source electrode 9 connected to the lower layer source wiring S1 has a length of 1 × 1 μm at the minimum although the length in the stripe direction differs depending on the pitch x + y described above.
The drain electrode 10 is also the same, and has an area of about 1 × 1 μm at the minimum.

Lower layer source wiring S1 and upper layer source wiring S2
The length of the through hole (TH) connecting to and is different in the stripe direction depending on the pitch x + y, but at least 1.6 ×
It has an area of about 1.6 μm. The size of the through hole connecting the lower layer drain wiring D1 and the upper layer drain wiring D2 is also the same, and the minimum area is about 1.6 × 1.6 μm.

The upper layer source wiring S2 and the upper layer drain wiring D2 have different dimensions depending on the pitch x + y.
Each has a width of 10 to 20 μm.

The feature of this high breakdown voltage MOSFET is that, in addition to the contents of the fifth embodiment described above, the lower layer source wiring S1 is used.
The orthogonal wiring structure is realized so that the through hole between the upper layer source wiring S2 and the upper layer source wiring S2 does not overlap with the contact hole between the lower layer wiring S1 and the n-type source layer 3.
An orthogonal wiring structure is also realized in which a through hole between the lower layer drain wiring D1 and the upper layer drain wiring D2 and a contact hole between the lower layer wiring D1 and the n-type drain layer 4 do not overlap each other.

In such an orthogonal wiring structure, on the source side, the island-shaped source electrode 9 is formed together with the lower layer source wiring S1 along the stripe direction, and a flat portion is formed between the source electrodes 9 on the lower layer source wiring S1. And the flat portion and the upper layer source wiring S2 are brought into contact with each other. The same applies to the drain side.

According to this orthogonal wiring structure, the source electrode 9
Of the lower layer source wiring S1 and the upper layer source wiring S2 per unit area without reducing the area (contact hole area) of
Since it is possible to increase the contact area (through-hole area) with, it is possible to reduce the ON resistance of the element without increasing the wiring resistance unlike the conventional case.

Similarly, the contact area (through hole area) between the lower layer drain wiring D1 and the upper layer drain wiring D2 per unit area can be increased without reducing the area of the drain electrode 10 (contact hole area). Therefore, unlike the prior art, it is possible to reduce the ON resistance of the element without increasing the wiring resistance.

As described above, according to the seventh embodiment, in addition to the effects of the fifth embodiment, a two-layer orthogonal wiring structure which can reduce the ON resistance of the element without increasing the wiring resistance is realized. can do. That is, it is possible to realize both a low on-resistance and a low wiring resistance, and to realize a high breakdown voltage MOSFET suitable for miniaturization and integration.

Further, the high breakdown voltage MOSF according to the present embodiment.
Instead of the sectional structure of FIG. 14, the ET is transformed into an apparatus having the sectional structure shown in any of FIGS. 16 to 18 by performing orthogonal wiring on the element corresponding to any of the second to fourth embodiments. Even in this case, in addition to the effect of this embodiment, the same effect as that of any of the second to fourth embodiments can be obtained. Note that the drain electrode 10 has an island shape in any modified configuration. In addition, the SO shown in FIG. 17 or FIG.
When it is transformed into the I structure, although not shown, the sectional structure of FIG. 15 also becomes the SOI structure.

(Eighth Embodiment) Next, the eighth embodiment of the present invention
FIG. 14 of the high breakdown voltage MOSFET according to the embodiment of FIG.
This will be described with reference to FIG.

FIG. 19 is a plan view showing the structure of this high breakdown voltage MOSFET, and FIG. 14 is a sectional view taken along the line XIV-XIV in FIG. 20 is a sectional view taken along the line XX-XX of FIG.

As shown in FIG. 19 and the like, in the high breakdown voltage MOSFET according to the present embodiment, the two-layer wiring according to the seventh embodiment is formed on the high breakdown voltage MOSFET according to the sixth embodiment. It is a composition.

With such a structure, the effects of the sixth and seventh embodiments can be obtained at the same time.

Further, the high breakdown voltage MOSF according to the present embodiment.
Instead of the sectional structure of FIG. 14, the ET is transformed into an apparatus having the sectional structure shown in any of FIGS. 16 to 18 by performing orthogonal wiring on the element corresponding to any of the second to fourth embodiments. Even in this case, in addition to the effect of this embodiment, the same effect as that of any of the second to fourth embodiments can be obtained. Note that any of the modified configurations has a planar structure shown in FIG. In addition, S shown in FIG. 17 or FIG.
When it is transformed into the OI structure, although not shown, the sectional structure shown in FIG. 20 also becomes the SOI structure.

(Other Embodiments) Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. For example, the n-type drain layer 4 and the n-type drift layer 5
A buffer layer may be provided between and. Also,
In each of the above embodiments, the MO having the n-type drain layer 4 is used.
The case where the SFET is formed has been described, but the drain layer 4 is assumed to be a p-type and an IGBT (insulated gate bipolar t
ransistor) may be formed.

In addition, the conductivity type of the semiconductor layer may be reversed from that of each embodiment, and a MOSFET in which the first conductivity type is p-type and the second conductivity type is n-type may be formed. Furthermore, this MOSF
The conductivity type of the drain layer of ET is reversed and the above-mentioned IGBT is used.
The IGBT may be formed of a semiconductor layer having a conductivity type opposite to the above.

Besides, the present invention can be variously modified and implemented without departing from the gist thereof.

[0094]

As described above, according to the first aspect of the invention, the first-conductivity-type source layer is formed on the surface of the second-conductivity-type base layer in the form of a plurality of islands. Since the gate electrode is also formed on the first-conductivity-type source layer, the channel is also formed on the first-conductivity-type source layer, so that the first-conductivity-type source layer and the first-conductivity-type drift layer are formed. Since the effective channel width can be widened as compared with the conventional high breakdown voltage semiconductor device in which the gate electrode is formed only between and the channel is formed, it is possible to provide a high breakdown voltage semiconductor device that can obtain low on-resistance. .

According to the second aspect of the invention, when the first-conductivity-type source layer is formed in a plurality of islands, the drain layer is formed in a substantially stripe shape as in the conventional case, and is substantially parallel to the stripe direction. Since the first-conductivity-type source layer is formed in an array, the high breakdown voltage semiconductor device can be provided in addition to the effect of the first aspect, which can be formed without significantly changing the conventional design.

Further, according to the invention of claim 3, the high resistance semiconductor layer is formed on the insulating film formed on the substrate,
By applying the so-called SOI structure, in addition to the effect of the first aspect, it is possible to provide a high breakdown voltage semiconductor device that facilitates isolation between elements and has very effective resistance to noise.

According to the fourth aspect of the invention, the length in the arrangement direction of the first conductivity type source layer is defined as x, and the length in the arrangement direction of the first conductivity type source layer is defined as x. y
Then, the relationship of 4.5 μm ≦ x + y ≦ 100 μm is satisfied, and in addition to the effect of any one of claims 1 to 3, a high breakdown voltage semiconductor device that reduces the on-resistance without increasing the contact resistance is provided. it can.

Further, according to the invention of claim 5, when the length in the arrangement direction of the gate electrodes formed between the adjacent first conductivity type source layers is x, 1.5 μm ≦ x ≦ 4 μm
Since the above relationship is satisfied, in addition to the effect of any one of claims 1 to 3, it is possible to provide a high breakdown voltage semiconductor device that reduces the on-resistance without increasing the contact resistance.

Further, according to the invention of claim 6, since the drain layer is of the first conductivity type, in addition to the effect of any one of claims 1 to 3, a high breakdown voltage semiconductor device as a high breakdown voltage MOSFET is provided. Can be provided.

Further, according to the invention of claim 7, since the drain layer is of the second conductivity type, in addition to the effect of any one of claims 1 to 3, a high breakdown voltage semiconductor device as a high breakdown voltage IGBT is provided. Can be provided.

According to the invention of claim 8, the through hole between the lower layer source wiring and the upper layer source wiring and the contact hole between the lower layer source wiring and the first conductivity type source layer are not overlapped, Moreover, by realizing a cross wiring structure in which the through hole between the lower layer drain wiring and the upper layer drain wiring and the contact hole between the lower layer drain wiring and the first conductivity type drain layer are not overlapped, the contact hole area is reduced. Since the through-hole area can be increased without decreasing, in addition to the effect of any one of claims 1 to 3, even if the orthogonal wiring structure is formed, the wiring resistance is not increased and the on-resistance can be further reduced. A high breakdown voltage semiconductor device suitable for miniaturization and integration can be provided.

[Brief description of the drawings]

FIG. 1 is a high breakdown voltage MOS according to a first embodiment of the present invention.
Plan view showing the element structure of the FET

FIG. 2 is a IIA-IIA line of FIG. 1 in the same embodiment;
IIB-IIB line sectional view

FIG. 3 is a vertical MO for explaining the effect of the embodiment.
Schematic diagram showing the problems of SFET

FIG. 4 is a high breakdown voltage MOS according to a second embodiment of the present invention.
Plan view showing the element structure of the FET

FIG. 5 is a sectional view taken along the line VA-VA and line VB-VB of FIG. 4 in the same embodiment.

FIG. 6 is a high breakdown voltage MOS according to a third embodiment of the present invention.
Plan view showing the element structure of the FET

FIG. 7 is a sectional view taken along line VIIA-VIIA and line VIIB-VIIB of FIG. 6 in the same embodiment.

FIG. 8 is a diagram showing an experimental result comparing the ON resistance of the high breakdown voltage MOSFET in the same embodiment with the ON resistance of the conventional high breakdown voltage MOSFET.

FIG. 9 is a high breakdown voltage MOS according to a fourth embodiment of the present invention.
Sectional view showing the element structure of the FET

FIG. 10 is a high breakdown voltage MO according to a fifth embodiment of the present invention.
The top view which shows the element structure of SFET.

FIG. 11 is a high breakdown voltage MO according to a sixth embodiment of the present invention.
The top view which shows the element structure of SFET.

FIG. 12 is a sectional view taken along line XII-XII of FIG. 11 in the same embodiment.

FIG. 13 is a high breakdown voltage MO according to a seventh embodiment of the present invention.
Plan view showing the structure of the SFET

FIG. 14 is a sectional view taken along the line XIV-XIV of FIG. 13 in the same embodiment.

FIG. 15 is a sectional view taken along the line XV-XV of FIG. 13 in the same embodiment.

FIG. 16 is a cross-sectional view showing a modified configuration of the same embodiment.

FIG. 17 is a sectional view showing a modified configuration of the same embodiment.

FIG. 18 is a cross-sectional view showing a modified configuration of the same embodiment.

FIG. 19 is a high breakdown voltage MO according to an eighth embodiment of the present invention.
Plan view showing the structure of the SFET

FIG. 20 is a cross-sectional view taken along the line XX-XX of FIG. 19 in the embodiment.

FIG. 21 is a plan view showing an element structure of a conventional high breakdown voltage MOSFET.

22 is a sectional view taken along the line XXII-XXII in FIG. 21 of the related art.

FIG. 23 is a plan view showing a structure in which orthogonal wiring is applied to a conventional high breakdown voltage MOSFET.

FIG. 24 is a sectional view taken along the line IV-IV of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... p-type semiconductor layer 2 ... p-type base layer 3,3 '... n-type source layer 4 ... n-type drain layer 5 ... n-type drift layer 5a ... immediately below 6 ... gate oxide film 7 ... field oxide film 8,8 ′ ... Gate electrode 9 ... Source electrode 10 ... Drain electrode 11 ... P-type contact layer 12 ... P-type Si substrate 13 ... Oxide film 14, 15 ... Insulating film 16 ... Interlayer insulating film x, y, z ... Length S1 ... Lower layer Source wiring S2 ... Upper layer source wiring D1 ... Lower layer drain wiring D2 ... Upper layer drain wiring

Claims (8)

[Claims] 1. A high resistance semiconductor layer, a first conductivity type drift layer selectively formed on a surface of the high resistance semiconductor layer, a drain layer formed on a surface of the first conductivity type drift layer, A second conductivity type base layer selectively formed on the surface of the high resistance semiconductor layer; and a first conductivity type source layer formed in a plurality of islands on the surface of the second conductivity type base layer, A gate electrode formed on the second conductive type base layer between the first conductive type source layer and the first conductive type drift layer and between the adjacent first conductive type source layers via a gate insulating film; A high breakdown voltage semiconductor device comprising: a drain electrode that contacts the drain layer; and a source electrode that contacts both the first conductive type source layer and the second conductive type base layer. 2. A high resistance semiconductor layer, a first conductivity type drift layer selectively formed on the surface of the high resistance semiconductor layer, and a substantially stripe shape formed on the surface of the first conductivity type drift layer. Drain layer, a second conductivity type base layer selectively formed on the surface of the high resistance semiconductor layer, and a plurality of second conductivity type base layers formed on the surface of the second conductivity type base layer and substantially parallel to the stripe direction of the drain layer. A first conductive type source layer arranged in the form of an island, and the second conductive layer between the first conductive type source layer and the first conductive type drift layer and between the adjacent first conductive type source layers. A gate electrode formed on the conductive type base layer via a gate insulating film, a drain electrode contacting the drain layer, and a source contacting both the first conductive type source layer and the second conductive type base layer. Equipped with electrodes A high breakdown voltage semiconductor device characterized by the above. 3. A substrate, an insulating film formed on the substrate, a high resistance semiconductor layer formed on the insulating film, and a first conductive film selectively formed on a surface of the high resistance semiconductor layer. Type drift layer, a drain layer formed in a substantially stripe shape on the surface of the first conductivity type drift layer, a second conductivity type base layer selectively formed on the surface of the high resistance semiconductor layer, A first-conductivity-type source layer formed on the surface of the second-conductivity-type base layer and arranged in a plurality of islands substantially parallel to the stripe direction of the drain layer; A gate electrode formed on the second conductive type base layer between the first conductive type drift layer and the adjacent first conductive type source layer via a gate insulating film; and a drain electrode contacting the drain layer. , The first conductivity type source And the high-voltage semiconductor device being characterized in that a source electrode that contacts both of the second conductivity type base layer. 4. The high breakdown voltage semiconductor device according to claim 1, wherein a plurality of the first conductivity type source layers are adjacent to each other when they are formed along a predetermined arrangement direction. When the length of the gate electrodes formed on the first conductive type source layer in the arrangement direction is x, and the length of the first conductive type source layers in the arrangement direction is y, 4.5 μm ≦ x + y A high breakdown voltage semiconductor device having a relationship of ≦ 100 μm. 5. The high breakdown voltage semiconductor device according to claim 1, wherein a plurality of the first conductivity type source layers are adjacent to each other when they are formed along a predetermined array direction. A high withstand voltage semiconductor device satisfying a relationship of 1.5 μm ≦ x ≦ 4 μm, where x is a length of the gate electrodes formed on the first conductive type source layers that are aligned with each other in the arrangement direction. . 6. The high breakdown voltage semiconductor device according to claim 1, wherein the first conductivity type drift layer is in contact with the gate insulating film, and the second conductivity type base layer is in contact therewith. A high breakdown voltage semiconductor device characterized in that it is also formed. 7. The high breakdown voltage semiconductor device according to claim 1, wherein the drain layer is of a first conductivity type. 8. The high breakdown voltage semiconductor device according to claim 1, wherein the drain electrode is formed in a plurality of islands in an array, and the drain electrode is in contact with the gate electrode. Without a lower layer source wiring that electrically connects adjacent source electrodes via the gate electrode above, and a longitudinal direction in a direction orthogonal to the lower layer source wiring, and the lower layer source above the gate electrode. The upper layer source wiring that contacts the upper portion of the wiring, the lower layer drain wiring that electrically connects adjacent drain electrodes through the upper portion of the drain layer without making contact with the drain layer, and the lower layer drain wiring are orthogonal to each other. An upper layer drain wiring which is in contact with the upper portion of the lower layer drain wiring above the drain layer. High voltage semiconductor device.