JP2016058541A - Lateral semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that it is necessary to manufacture a gate insulation film and a drift region covering film separately in the case of a lateral semiconductor device in which a source region and a drain region are formed at positions facing a surface of a semiconductor substrate and resistance between a source and drain is changed by a voltage of a gate electrode.SOLUTION: In a lateral semiconductor device, one sheet of STI insulation film 13 which extends from a position in contact with a source region 8 through a body region 4 and a drift region 18 to reach a position in a drain region 16 is used. The STI film 13 can double as the gate insulation film and the drift region covering film and it is not necessary to manufacture the gate insulation film and the drift region covering film separately. It is preferable to prepare a resurf layer 4a. It is preferable to form a gate electrode 12 by p-type polysilicon in the case of an n-channel.SELECTED DRAWING: Figure 2

Description

  In this specification, the source region and the drain region are formed so as to face the surface of the semiconductor substrate, and the resistance between the source region and the drain region varies depending on the voltage of the gate electrode formed on the surface of the semiconductor substrate. A lateral semiconductor device is disclosed. Also disclosed is a lateral semiconductor device in which an emitter region is used instead of a source region and a collector region is used instead of a drain region.

  An example of a horizontal semiconductor device is disclosed in Patent Document 1. As shown in FIG. 6, the semiconductor device is formed at a position facing a part of the surface of the semiconductor substrate 2 and a position facing the other part of the surface of the semiconductor substrate 2. The drain region 16 is provided. A body region (a part of a well region in terms of the shape of the region) 4 is formed at a position where the source region 8 and the drain region 16 are separated, and the gate insulating film 10 is formed in a range where the body region 4 faces the surface. Through which the gate electrode 12 faces. The source region 8 and the drain region 16 are n-type, and the body region 4 is p-type. When a voltage is applied to the gate electrode 12, the buddy region 4 in the range facing the gate electrode 12 through the gate insulating film 10 is inverted to n-type, and the resistance between the source region 8 and the drain region 16 decreases.

Reference number 18 is a drift region interposed between the body region 4 and the drain region 16, and is an n-type region having a lower concentration than the drain region 16. The drift region 18 becomes a current path when the semiconductor device is on, and holds (withstand voltage) a reverse bias voltage when the semiconductor device is off. Reference numeral 6 denotes a contact region, which is formed of a p-type region having a concentration higher than that of the body region 4, and makes an ohmic contact with a source electrode (not shown) to make the potential of the body region 4 coincide with the potential of the source electrode. Stabilize the operation of the semiconductor device.
In FIG. 6, illustration of a source electrode, a drain electrode, a protective film, and the like formed on the surface of the semiconductor substrate 2 is omitted. Further, the structure deeper than the drift region 18 can be designed in various ways. An actual semiconductor device may have a bilaterally symmetric structure with the AA line as the axis of symmetry.

  In order to stabilize the operation of the semiconductor device, an insulating film 14 that covers the surface of the drift region 18 interposed between the body region 4 and the drain region 16 is formed. It is preferable to make the electric field distribution in the drift region 18 uniform by using the potential difference between the source and the drain when it is turned off so that it flows inside the semiconductor substrate located underneath or when a reverse bias voltage is applied. When the electric field distribution becomes uniform, the semiconductor device has a high breakdown voltage. In order to increase the breakdown voltage, the insulating film 14 formed on the drift region 18 is preferably formed thick. The insulating film 14 is formed by a LOCOS (local oxidation of silicon) method.

  FIG. 7 shows an example in which the surface of the drift region 18 interposed between the body region 4 and the drain region 16 is covered with an insulating film 14a formed by an STI (shallow trench isolation) method instead of the LOCOS method. Yes. The insulating film 14a is formed by forming a shallow trench on the surface of the semiconductor substrate 2, filling the trench with an oxide, and then performing a planarization process.

Japanese Patent Laid-Open No. 9-205201

In the prior art, the gate insulating film 10 that insulates between the gate electrode 12 and the body region 4, and the insulating film that covers the surface of the drift region 18 interposed between the body region 4 and the drain region 16 (the drift region coating). 14 and 14a are required.
In this specification, it is not necessary to prepare the gate insulating film 10 and the drift region coating films 14 and 14a separately, and a technique of sharing a single common insulating film is provided.

  The lateral semiconductor device disclosed in this specification includes a well region on the first conductive side formed at a position facing a part of the surface of the semiconductor substrate, and a position facing a part of the surface of the semiconductor substrate in the well region. A source region on the second conductive side formed, a drain region on the second conductive side formed at a position facing a part of the surface of the semiconductor substrate outside the well region, and interposed between the well region and the drain region The second conductivity type drift region, the insulating film, and the gate electrode are provided. The insulating film extends along the surface of the semiconductor substrate from a position in contact with the source region to a position in contact with the drain region through the well region and the drift region. The gate electrode is stacked on the insulating film in the existence range of the well region that separates the source region and the drift region. In the lateral semiconductor device disclosed in this specification, one insulating film continuously extends from a position in contact with the source region to a position in contact with the drain region through the well region and the drift region.

As a result of various studies, the maximum thickness allowed for the gate insulating film, which is required to be thin to form the inversion layer, depends on the magnitude of the gate voltage applied to the gate electrode, and stabilizes the electric field distribution in the drift region. It has been found that there is a case where the relationship is thicker than the minimum thickness allowed for the drift region coating film that is required to be thick. That is, the allowable maximum thickness of the gate insulating film> the allowable minimum thickness of the drift region covering film, and the insulating film having a thickness within the range of the allowable maximum thickness of the gate insulating film to the allowable minimum thickness of the drift region covering film It has been found that there is a case where it can be used as a gate insulating film or a drift region coating film.
When the above condition is satisfied, it is only necessary that a single insulating film continuously extends with a uniform thickness from a position in contact with the source region to a position in contact with the drain region, and the gate insulating film and the drift region coating film are separately provided. There is no need to manufacture.
As will be described later, it is possible to form a single insulating film whose thickness varies depending on the location. According to the insulating film forming method, the optimum thickness of the gate insulating film and the optimum thickness of the drift region covering film are Even if they are different, a single insulating film continuously extending from a position in contact with the source region to a position in contact with the drain region can be used as the gate insulating film and the drift region coating film. One insulating film continuously extending from a position in contact with the source region to a position in contact with the drain region has both a portion functioning as a gate insulating film and a portion functioning as a drift region covering film, It is not necessary to prepare a drift region coating film separately.

When an insulating film formed by the STI method is used, the thickness of the insulating film can be accurately controlled, and an insulating film having both a portion functioning as a gate insulating film and a portion functioning as a drift region covering film is obtained. Cheap. For example, when the maximum thickness allowed for the gate insulating film> the minimum thickness allowed for the drift region covering film, the maximum thickness allowed for the gate insulating film> the thickness of the STI insulating film> the drift region covering It is easy to manage the relationship between the minimum thickness allowed for the film. When the STI method is used, the gate electrode and the well region, etc. are insulated from each other, and when a voltage is applied to the gate electrode, the thickness required for the gate insulating film, which requires the characteristics of forming an inversion layer in the well region, is reversed. The thickness required for the drift region coating film, which is required to make the electric field distribution between the source and the drain uniform during biasing, can be satisfied at the same time. When an insulating film formed by the STI method is used, the gate insulating film and the drift region coating film can be easily used together.
The depth of the trench used for the STI method does not necessarily have to be uniform. For example, the depth at the position facing the well region and the depth at the position covering the drift region may be changed. In the above semiconductor device, one insulating film continuously extends from a position in contact with the source region to a position in contact with the drain region. The insulating film has both a portion functioning as a gate insulating film and a portion functioning as a drift region coating film, and can be adjusted to an optimum thickness for each portion. There is no need to prepare a gate insulating film and a drift region coating film separately.

  When the well region (that is, the region providing the channel region) is p-type, the source region / drift region / drain region is n-type, and the gate insulating film thickness is constant, the gate electrode is made of p-type polysilicon. When formed, the threshold voltage can be increased as compared with the case where the gate electrode is formed of n-type polysilicon. In other words, the increase in threshold voltage can be compensated by lowering the channel concentration, which is advantageous in reducing variations in channel impurities. Conversely, when the well region is n-type and the source region / drift region / drain region is p-type, the same effect can be obtained by forming the gate electrode from n-type polysilicon. Further, when the impurity concentration in the well region is constant, the gate insulating film can be thinned, so that the gate insulating film and the drift region covering film can be easily used in common.

  It is preferable to form a RESURF layer extending from the well region to the drain region at a depth away from the surface of the semiconductor substrate. Accordingly, the drift layer is easily depleted in a state where no voltage is applied to the gate electrode, and the breakdown voltage is improved. When it is not necessary to improve the breakdown voltage, the impurity concentration of the drift layer can be increased and the on-resistance can be lowered. Alternatively, the semiconductor device can be miniaturized by reducing the length of the drift region.

Sectional drawing of the semiconductor device of 1st Example. Sectional drawing of the semiconductor device of 2nd Example. Sectional drawing of the semiconductor device of 3rd Example. Sectional drawing of the semiconductor device of 4th Example. Sectional drawing of the semiconductor device of 5th Example. Sectional drawing of the conventional semiconductor device. Sectional drawing of the other conventional semiconductor device.

The features of the technology disclosed in this specification will be summarized below. The items described below have technical usefulness independently.
(First Feature) The gate insulating film and the drift region coating film are used together by the STI insulating film.
(Second feature) The thickness of the STI insulating film (the depth of the trench) is uniform.
(Third feature) The thickness of the STI insulating film (the depth of the trench) varies depending on the location.
(Fourth feature) By using p-type polysilicon for the gate electrode for the n-type inversion channel, an inversion layer is provided in the range facing the gate electrode while ensuring the necessary thickness for the drift region coating film. Form.
(Fifth feature) By using n-type polysilicon for a gate electrode for a channel that is inverted to p-type, an inversion layer is provided in a range facing the gate electrode while ensuring a necessary thickness for the drift region coating film. Form.
(Sixth feature) A contact region and a source region (or an emitter region) are formed in a part of the well region, and a well region in which the contact region and the source region are not formed is called a body region. The body region may be referred to as a base region.

(Example 1)
FIG. 1 shows a cross-sectional structure of a lateral semiconductor device according to the first embodiment, more specifically, a lateral LDMOSFET (laterally diffused metal oxide semiconductor field-effect transistor).
Reference numeral 2 is a semiconductor substrate, 4 is a body region (a part of the well region), 6 is a body contact region (a part of the well region), 8 is a source region (formed in a part of the well region), 12 Denotes a gate electrode, 16 denotes a drain region, and 18 denotes a drift region. The body region 4 is formed in a range facing a part of the surface of the semiconductor substrate 2 and may be a part of the well region. The drift region 18 may be formed of the semiconductor substrate 2 itself as illustrated in FIGS. 6 and 7. However, in the embodiment of FIG. 1, the n-type region formed in a part of the semiconductor substrate 2. It consists of 6 and 7, an n-type semiconductor substrate 2 is used, and in the embodiment shown in FIG. 1, a p-type semiconductor substrate is used. In the case of FIG. 1, the semiconductor substrate 2 itself is p-type, the source region 8, the drift region 18 and the drain region 16 are n-type, and the body region 4 and the body contact region 6 are p-type. The source region 8 and the body contact region 6 have an impurity concentration that makes ohmic contact with a source electrode (not shown). The drain region 16 has an impurity concentration that makes ohmic contact with a drain electrode (not shown). The impurity concentration of the body region 4 is lower than the impurity concentration of the body contact region 6. The impurity concentration of the drift region 18 is lower than the impurity concentration of the drain region 16. The body contact region 6 can be understood as a part of the well regions 4 and 6.

Reference numeral 13 is an insulating film formed by the STI method. The STI insulating film 13 is manufactured as follows.
(1) A shallow trench is etched in a part of the surface of the semiconductor substrate 2. In the etching, a nitride film is formed on a part of the surface of the semiconductor substrate 2, and the semiconductor substrate 2 is anisotropically plasma etched using the nitride film as a mask to form a trench. By forming an opening having a shape corresponding to the formation range of the insulating film 13 in the nitride film used as a mask, a trench is formed in the formation range of the insulating film 13.
(2) A thin thermal oxide film is formed on the inner surface of the trench.
(3) The trench is filled with SiO ₂ . A CVD method is used for the filling process, and SiO ₂ is deposited until it exceeds the surface of the semiconductor substrate before the trench formation.
(4) Thereafter the SiO ₂ etching, to match the SiO ₂ surface after etching the surface of the semiconductor substrate before the trench formation. Further, the nitride film formed in (1) is removed by etching.
Reference numeral 12 denotes a gate electrode, which is made of p-type polysilicon.

The horizontal semiconductor device according to the first embodiment shown in FIG. 1 has the following features.
(1) The well regions 4 and 6 are formed at positions facing a part of the surface of the semiconductor substrate 2.
(2) The source region 8 is formed at a position facing a part of the surface of the semiconductor substrate 2 in the well regions 4 and 6.
(3) The drain region 16 is formed in a range facing a part of the surface of the semiconductor substrate 2 outside the well regions 4 and 6.
(4) The drift region 18 is interposed between the well regions 4 and 6 and the drain region 16.
(5) From a position where one insulating film 13 is in contact with the source region 8 along the surface of the semiconductor substrate 2 to a position where it is in contact with the drain region 16 through the body region 4 and the drift region 18 which are part of the well region. , Extending continuously.
(6) The gate electrode 12 is stacked on the insulating film 13 in the existence range of the well region (body region 4) in the range separating the source region 8 and the drift region 18. (7) The insulating film 13 is the source It extends uniformly from a position in contact with the region 8 to a position in contact with the drain region 16 through the well region 4 and the drift region 18. That is, the insulating film 13 is formed with a uniform thickness and is formed with a homogeneous component.
(8) The source region 8, the drift region 18 and the drain region 16 are n-type, and the body region 4 and the body contact region 6 are p-type. The conductivity type can be reversed. That is, the source region 8, the drift region 18, and the drain region 16 may be p-type, and the body region 4 and the body contact region 6 may be n-type. In short, the body region 4 and the body contact region 6 have the same conductivity type (referred to as the first conductivity type in this specification), and the source region 8, the drift region 18 and the drain region 16 also have the same conductivity type. If the conductivity type is different from the conductivity type of the body contact region 6 (referred to as the second conductivity type in this specification), a semiconductor device that operates as intended can be obtained.

  In this semiconductor device, if the STI insulating film 13 functions as a gate insulating film, it also functions as a drift region coating film that stabilizes the electric field distribution in the drift region 18. That is, when a predetermined potential is applied to the gate electrode 12, the body region 4 at a position facing the gate electrode 12 through the STI insulating film 13 is inverted to n-type, and the resistance between the source region 8 and the drain region 16 is reduced. descend. Even if the semiconductor device is actually used and a protective film (not shown) covering the surface of the semiconductor substrate 2 is charged by the surrounding environment, the drift region 18 is covered with the STI insulating film 13, and the drift region 18 The electric field distribution at 18 does not change. In the semiconductor device of FIG. 1, the gate insulating film that insulates between the gate electrode 12 and the body region 4 and the like and the insulating film that covers the surface of the drift region 18 are shared, and it is not necessary to prepare them separately.

  When a thermal oxide film is used for the drift region coating film, the bird's peak of the LOCOS oxide film extends to the vicinity of the source region 8. For this reason, the source contact area varies, the stress field accompanying the change in the thickness of the LOCOS film overlaps with the source region (impurity high concentration diffusion region), crystal defects are likely to occur, and the leakage current tends to increase.

When p-type polysilicon is used for the gate electrode that is inverted to n-type to lower the resistance, the work function of the gate electrode material influences, and an inversion layer is formed even if the gate insulating film is thinned. The inversion layer is also easily formed by lowering the impurity concentration of the body layer (channel) that forms the inversion layer. When the impurity concentration of the body layer is lowered, the variation in threshold voltage can be reduced.
The combination of the technology for selecting the material of the gate electrode, the technology for reducing the impurity concentration in the body region, and the STI insulating film alleviates the conditions for sharing the gate insulating film and the drift region covering film. .
If n-type polysilicon is used for the gate electrode that is inverted to p-type to lower the resistance, the impurity concentration of the channel can be lowered by the increase of the threshold voltage. In the case of a p-channel semiconductor device, a combination of n-type polysilicon and an STI insulating film is preferable.

  When the concentration of the body layer is lowered, there is a concern that it becomes weak against DIBL (Drain-induced barrier lowering). When such a problem occurs, a countermeasure can be taken by setting the channel length long or by forming a region (barrier layer) having a high impurity concentration at a deep position immediately below the channel region.

(Second embodiment)
As shown in FIG. 2, in the semiconductor device of the second embodiment, a RESURF layer 4 a extending from a body region (well region) 4 to a deep region of the semiconductor substrate 2 toward the drain region 16 is formed. The RESURF layer 4a is deeper than the STI insulating film 13, and the drift region 18 is secured at a depth between the STI insulating film 13 and the RESURF layer 4a.
When the RESURF layer 4a is formed, the electric field distribution in the drift region 18 is easily uniformized. By adding the RESURF layer 4a, the breakdown voltage of the semiconductor device is improved. If the necessary breakdown voltage is obtained and the same breakdown voltage can be maintained, the impurity concentration of the drift region 18 can be increased by adding the RESURF layer 4a. When the impurity concentration of the drift region 18 increases, the resistance of the drift region 18 decreases and the on-resistance of the semiconductor device decreases. Alternatively, even if the length of the drift region 18 is shortened, a necessary breakdown voltage is secured, which is advantageous for downsizing of the semiconductor device.
The thickness of the STI insulating film 13 is not necessarily uniform and can be changed depending on the location. By changing the depth of the trench depending on the location, the thickness of the STI insulating film 13 can be changed depending on the location. In the case of FIG. 2, the portion that functions as the gate insulating film is thinned, and the portion that functions as the drift region coating film is thickened.

(Third embodiment)
As shown in FIG. 3, a concentration profile may be formed in the RESURF layer 4a. When the impurity concentration gradually decreases in the regions 4b, 4c, and 4d in order, the electric field distribution in the drift region 18 is homogenized, and local electric field concentration can be prevented.
Further, it is preferable to dispose a drain plate 28 having the same potential as the drain region 16 on the STI insulating film 13. When the drain plate 28 is disposed, the electric field relaxation effect on the drain side is enhanced, and a stable breakdown voltage can be obtained. The drain plate 28 is preferably set to the same potential as the drain electrode 32.
The drain electrode 32 may be in contact with not only the drain region 16 but also the p ⁺ -type region 30. A structure in which the drain region 16 and the p ⁺ -type region 30 are in contact with the drain electrode 32 is known as a universal contact. When the universal contact is employed, holes can be extracted from the drain side during dynamic avalanche, and element destruction can be prevented.
As shown in FIG. 3, the semiconductor substrate 2 may be an SOI substrate in which an active layer 20, an intermediate insulating layer 22, and a base layer 24 are stacked. In that case, the semiconductor structure of the present embodiment is realized in the active layer 20.
Further, as shown in FIG. 3, the insulating film 26 may be exposed on the side surface when the semiconductor device is formed into a chip. The chip of the semiconductor device in FIG. 3 has a symmetrical structure with respect to the line AA.
The shape of the trench for the STI insulating film 13 can be various. FIG. 3 shows a trench shape in which an inclined surface appears near the boundary between the wall surface and the bottom surface. By improving the trench shape, it is possible to alleviate electric field concentration.

(Fourth embodiment)
As shown in FIG. 4, a p ⁺ -type collector region 35 may be used instead of the drain region 16. In this case, the source region 8 becomes the emitter region 8a. In FIG. 4, reference numeral 8a is assigned to indicate the emitter region. According to the structure of FIG. 4, an IGBT is obtained. Also in the case of the IGBT, when the STI insulating film 13 is used, the gate insulating film and the drift region coating film can be used together. In the case of an IGBT, an n ⁺ type region 34 may be disposed around the p ⁺ type collector region 35. By arranging the n ⁺ -type region 34, the breakdown voltage of the IGBT can be increased.

(5th Example)
FIG. 5 shows a sectional structure of the fifth embodiment. Parts that have already been described are given the same reference numerals, and redundant description is omitted. Reference numeral 42 indicates an n ⁺ layer, 44 indicates an insulating layer, 36 indicates a source metal plate, 40 indicates a drain metal plate, and 38 indicates an insulating layer. Also in this embodiment, the STI insulating film 13 continuously extends from a position in contact with the source region 8 to a position in contact with the drain region 16. Although the film thickness of the STI insulating film 13 may vary depending on the location, the STI insulating film 13 extends with a uniform thickness in this embodiment. When a necessary function can be ensured with a uniform thickness, the trench formation process is simplified.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

2: Semiconductor substrate 4: Body region (part of well region)
4a: RESURF layer 4b, 4C, 4D: RESURF layer with concentration distribution 6: body contact region (part of well region)
4 + 6: well region 8: source region 8a: emitter region 10: gate insulating film 12: gate electrode 13: STI insulating film 14: LOCOS oxide film 14a: STI insulating film 16: drain region 18: drift region 20: active layer 22: Intermediate insulating layer 24: base layer 26: side insulating layer 28: drain plate 30: P ⁺ region 32: drain electrode 34: buffer region 35: collector region 36: source metal plate 38: insulating layer 40: drain metal plate 42: n layer 44: Insulating layer

Claims (5)

A well region on the first conductive side formed at a position facing a part of the surface of the semiconductor substrate;
A source region on the second conductive side formed at a position facing a part of the surface of the semiconductor substrate in the well region;
A drain region on the second conductive side formed at a position facing a part of the surface of the semiconductor substrate outside the well region;
A drift region of a second conductivity type interposed between the well region and the drain region;
An insulating film extending along a surface of the semiconductor substrate from a position in contact with the source region to a position in contact with the drain region through the well region and the drift region;
A gate electrode stacked on the insulating film in a range of the well region in a range separating the source region and the drift region;
The lateral semiconductor device, wherein the one insulating film continuously extends from a position in contact with the source region to a position in contact with the drain region.   2. The lateral semiconductor device according to claim 1, wherein the insulating film is an insulating film formed by an STI method. The first conductivity type is p-type, the second conductivity type is n-type,
The lateral semiconductor device according to claim 2, wherein the gate electrode is p-type polysilicon.   The semiconductor device according to claim 3, wherein a RESURF layer is formed extending from the well region toward the drain region at a depth away from the surface of the semiconductor substrate. A well region on the first conductive side formed at a position facing a part of the surface of the semiconductor substrate;
A second conductive side emitter region formed at a position facing a part of the surface of the semiconductor substrate in the well region;
A collector region on the first conductive side formed at a position facing a part of the surface of the semiconductor substrate outside the well region;
A second conductivity type drift region interposed between the well region and the collector region;
An insulating film extending along the surface of the semiconductor substrate from a position in contact with the emitter region to a position in contact with the collector region through the well region and the drift region;
A gate electrode laminated on the insulating film in the existence range of the well region in a range separating the emitter region and the drift region;
The lateral semiconductor device, wherein the one insulating film continuously extends from a position in contact with the emitter region to a position in contact with the collector region.

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