JP2010258355A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a LDMOS transistor which has the breakdown voltage lowered to be less than those in conventional configurations, while maintaining low on-resistance, and to provide a manufacturing method for the LDMOS transistor. <P>SOLUTION: The LDMOS transistor includes: an N-type well 2, formed on a P-type substrate 1; a P-type body region 6 formed in the well 2; a P-type embedded diffusion region 4, formed in a location deeper than the body region 6 in the well 2; an N-type source region 9, formed in the body region 6; an N-type drift region 7 formed isolated from the body region 6 via an element isolation region in the well 2; an N-type drain region 10 formed in the drift region 7; and a gate electrode 7, formed extending to at least over part of the body region 9 and over the part of the well region 2 sandwiched between the body region 9 and the drain region 10 via a gate insulating film. The drift region 7 and the drain region 10 are so formed into a ring shape as to encircle the body region 6. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to an LDMOS transistor (lateral double diffusion MOS transistor) and a manufacturing method thereof.

  LDMOS transistors have features such as a high switching speed and are easy to use because of voltage drive systems. They are used in switching regulators, various drivers, DC-DC converters, etc., and are key devices in the field of power and high withstand voltage. Yes.

  In general, the performance of an LDMOS transistor is indicated by its breakdown voltage (breakdown breakdown voltage) and on-resistance when it is off. However, these are usually in a trade-off relationship, and it is difficult to achieve both high breakdown voltage and low on-resistance. For this reason, development has been conducted for many years in terms of how to achieve this balance.

  Hereinafter, the structure of a conventional N-channel LDMOS transistor described in Patent Document 1 will be described with reference to FIGS. FIG. 12 is a schematic plan view of this transistor, and FIG. 13 is a schematic cross-sectional view taken along line L1-L2 in FIG.

  As shown in FIG. 13, the conventional LDMOS transistor has a P-type epitaxial layer 101 formed on a P-type semiconductor substrate 100. In the epi layer 101, an N-type buried diffusion region 102 and an N-type well 2 are formed above the buried diffusion region 102.

  A P-type body region 6 and an N-type drain region 10 are formed in the N-type well 2 so as to be separated from each other in the L direction (direction parallel to the L1-L2 line) via the element isolation region 21.

  A high concentration N type source region 8 is formed in the P type body region 6, and a high concentration P type body contact region 9 is further formed in the source region 8. A source electrode 16 is formed on the source region 8 and the body contact region 9 via a contact electrode, and the source region 16 and the body region 6 are set to the same potential.

  A gate electrode 11 is formed through a gate insulating film over a part of the P-type body region 6 and a part of the N-type well 2 located outside the P-type body region 6.

  A drain electrode 15 is formed on the N-type drain region 10 via a contact electrode. Reference numeral 22 in FIG. 13 denotes an interlayer insulating film.

  In general, in an N-channel LDMOS transistor, when a reverse bias is applied between the drain and source, the source electrode 16 and the gate electrode 11 are set to the GND potential, and a positive voltage is applied to the drain electrode 15. To do. In this way, when a reverse bias is applied between the drain and the source, the electric field in the depletion layer reaches a critical electric field at a certain voltage, avalanche breakdown occurs, and current begins to flow rapidly between the drain and the source. The voltage applied to the drain electrode at this time is the off-breakdown voltage value of the transistor.

  When a reverse bias is applied between the drain and source, the electric field in the L direction is concentrated on the gate edge (region A in FIG. 13) on the drain side, which causes a decrease in breakdown voltage.

  Therefore, in order to increase the breakdown voltage, it is important to relax the electric field at the gate edge. As countermeasures, there are methods of adjusting the concentration of the N-type well 2 and adjusting the drift length (region B in FIG. 13).

  By the way, in the conventional N-channel LDMOS transistor shown in FIGS. 12 and 13, since the P-type body region 6 is formed in the N-type well 2, the P-type body region 6 is electrically connected to the P-type semiconductor substrate 100. It is characterized by being electrically insulated.

  When general N-channel LDMOS transistors are arranged in series in a plurality of stages between the power supply and GND, the potential of the source region of the N-channel LDMOS transistor arranged on the power supply side is almost fixed to the power supply voltage when turned on. In the source region, a withstand voltage corresponding to the power supply voltage is required for the P-type semiconductor substrate (usually GND potential).

  On the other hand, when the P-type body region 6 is formed in the N-type well 2 as in the N-channel LDMOS transistor having the above structure, the P-type body region 6 is electrically insulated from the P-type semiconductor substrate 100. Therefore, the potential of the P-type body region 6, that is, the potential of the N-type source region 8 can be used without being fixed to the GND potential, and there is an advantage that the circuit is highly versatile.

  However, in the N-channel LDMOS transistor shown in FIGS. 12 and 13, although the P-type body region 6 is formed in the N-type well 2, as shown below, depending on the use conditions, the source It is possible that the potential of the region 8 is fixed to the GND potential, and the versatility on the circuit is lost.

  Such a problem occurs when the low potential metal wiring 31 is formed so as to extend over the N-type well 2 at the outer position of the gate electrode 11 in the configuration of FIG. FIG. 15 is a schematic sectional view taken along line W1-W2 in FIG.

  Here, it is assumed that the N-channel LDMOS transistor operates in the saturation region (pentode region). More specifically, in FIG. 15, it is assumed that the N-type well 2 is at a high potential (several tens of volts), the gate-source voltage is about 5 V, and the source potential is an intermediate potential between the high potential and the GND potential.

  At this time, an inversion layer (hole) is formed by the gate electrode 11 immediately below the gate insulating film and immediately below the element isolation region 21 in the region C in FIG. Further, an inversion layer (hole) is formed by the metal wiring 31 immediately below the element isolation region 21 in the region D in FIG. Thereby, P type epitaxial layer 101 and P type body region 6 are electrically connected. As a result, when the P-type body region 6 is at an intermediate potential, a leak path is formed from the body region 6 to the P-type epitaxial layer 101 and the P-type semiconductor substrate 100. Can't get the result. That is, according to the configuration shown in FIG. 12 (FIG. 14), the above-described problem occurs depending on the formation position of the metal wiring 31, and thus versatility on the circuit is lost.

  For such a problem, a countermeasure as shown in FIG. 16 is usually implemented (for example, see Patent Document 2 below). FIG. 17 is a schematic sectional view taken along line W1-W2 in FIG.

  In this prior art, as shown in FIG. 16, the N-type drain region 10 is formed in a ring shape so as to surround the P-type body region 6. Accordingly, unlike FIG. 15, FIG. 16 also shows the N-type drain region 10 in the cross-sectional view taken along the line W1-W2.

  When the N-channel LDMOS transistor configured as described above operates in the saturation region (pentode region), more specifically, as before, the N-type well 2 has a high potential (several tens of volts), a gate -Assume that the source-to-source voltage is about 5 V and the source potential is an intermediate potential between the High potential and the GND potential.

  At this time, as in the case of FIG. 15, an inversion layer (hole) is formed by the gate electrode 11 immediately below the gate insulating film and immediately below the element isolation region 21 in the region C. However, the inversion layer is not formed immediately below the element isolation region 21 in the region D due to the presence of the high concentration N-type drain region 10. As a result, the insulation between the P-type body region 6 and the P-type epitaxial layer 101 is maintained, and the P-type body region 6 can be fixed at an intermediate potential. That is, the versatility of the circuit is enhanced as compared with the configuration of FIG.

US Pat. No. 5,719,421 Japanese Patent No. 3897801

  However, when a reverse bias is applied between the drain region 10 and the source region 8 for the N-channel LDMOS transistor having the configuration of FIGS. 16 and 17, the following problem occurs. FIG. 18 is a drawing in which the potential distribution when the reverse bias is applied is added to FIG.

  When a reverse bias is applied between the drain region 10 and the source region 8, the depletion layer extends from the junction interface between the P-type body region 6 and the N-type well 2, but due to the presence of the metal wiring 31 having a lower potential than the gate electrode 11, This depletion layer (hole) moves to the metal wiring 31 formation side (that is, the right side in FIG. 18) (field plate effect). Since the high-concentration N-type drain region 10 is formed on the right side of the drawing with respect to the gate electrode 11, as a result, a high electric field is concentrated in the vicinity of this edge (region E in FIG. 18). There arises a problem that the breakdown voltage is lowered.

  In general, in the case of an N-channel LDMOS transistor having a breakdown voltage of 50 V or higher, it is necessary to set the concentration of the N-type well 2 low in order to increase the off breakdown voltage value. This means that when a reverse bias is applied between the drain region 10 and the source region 8, the depletion layer becomes easier to extend toward the edge E side of the drain region 10. That is, a decrease in breakdown voltage in the W direction becomes significant.

  As a result, the breakdown voltage in the W direction (the direction parallel to the W1-W2 line) is lower than the breakdown voltage determined from the cross-sectional structure in the L direction (the direction parallel to the L1-L2 line). There is a problem that the breakdown voltage of the channel LDMOS transistor is lowered.

  In view of the above problems, an object of the present invention is to provide an LDMOS transistor that maintains a low on-resistance and further suppresses a decrease in breakdown voltage as compared with a conventional configuration, and a manufacturing method thereof.

In order to achieve the above object, a semiconductor device of the present invention includes:
A second conductivity type well different from the first conductivity type formed on the first conductivity type semiconductor substrate;
A body region of the first conductivity type formed in the well;
In the well, the buried diffusion region of the first conductivity type formed at a position deeper than the body region so as to be in contact with the bottom surface of the body region;
A source region of the second conductivity type formed in the body region and having a higher concentration than the well;
In the well, the drift region of the second conductivity type having a higher concentration than the well formed at a position separated from the body region in a direction parallel to the substrate surface of the semiconductor substrate;
In the drift region, the drain region of the second conductivity type having a concentration higher than that of the drift region, formed at a position spaced apart from the body region and the element isolation region in a direction parallel to the substrate surface of the semiconductor substrate. When,
A gate electrode formed through a gate insulating film over at least a part of the body region and over the well region at a position sandwiched between the body region and the drain region;
The drift region and the drain region are formed in a ring shape so as to surround the body region.

  Note that a semiconductor device having this feature can be manufactured by the following manufacturing method.

That is, a method of manufacturing a semiconductor device,
Implanting the second conductivity type impurity ions into the first conductivity type semiconductor substrate to form the well region;
Forming the element isolation region;
Implanting impurity ions of the first conductivity type into the well to form the body region and the buried diffusion region;
Implanting impurity ions of the second conductivity type at a concentration higher than that of the well into the well to form the ring-shaped drift region so as to surround the body region or a region to be formed;
Impurity ions of the second conductivity type having a concentration higher than that of the drift region are implanted into the body region and the drift region, the source region is implanted into the body region, and the ring-shaped region is implanted into the drift region. Forming each drain region; and
Forming the gate electrode through the gate insulating film over a part of the body region and over the well region at a position sandwiched between the body region and the drain region. It is what.

The semiconductor device of the present invention is
A second conductivity type well different from the first conductivity type formed on the first conductivity type semiconductor substrate;
A body region of the first conductivity type formed in the well;
In the well, the buried diffusion region of the first conductivity type formed at a position deeper than the body region so as to be in contact with the bottom surface of the body region;
A source region of the second conductivity type formed in the body region and having a higher concentration than the well;
In the well, the drift region of the second conductivity type having a higher concentration than the well formed at a position separated from the body region in a direction parallel to the substrate surface of the semiconductor substrate;
In the drift region, the drain region of the second conductivity type having a concentration higher than that of the drift region, formed at a position spaced apart from the body region and the element isolation region in a direction parallel to the substrate surface of the semiconductor substrate. When,
In the drift region, a diffusion region for preventing inversion layer formation of the second conductivity type having a higher concentration than the drift region, formed at a position spaced apart from the drain region in a direction parallel to the substrate surface of the semiconductor substrate; ,
A gate electrode formed through a gate insulating film over at least a part of the body region and over the well region at a position sandwiched between the body region and the drain region;
The source region is formed by extending in a first direction parallel to the substrate surface,
The drain region is formed to be opposed to the body region in a second direction that is parallel to the substrate surface and perpendicular to the first direction, but is not opposed to the first direction.
The drift region is formed in a ring shape so as to surround the body region, and the inversion layer formation preventing diffusion region is formed in a ring shape so as to surround the body region in the drift region at a position outside the drain region. It is another feature that it is formed.

  Note that a semiconductor device having this feature can be manufactured by the following manufacturing method.

That is, a method of manufacturing a semiconductor device,
Implanting the second conductivity type impurity ions into the first conductivity type semiconductor substrate to form the well region;
Forming the element isolation region;
Implanting impurity ions of the first conductivity type into the well to form the body region and the buried diffusion region;
Implanting impurity ions of the second conductivity type at a concentration higher than that of the well into the well to form the ring-shaped drift region so as to surround the body region or a region to be formed;
Injecting impurity ions of the second conductivity type having a concentration higher than that of the drift region in the body region and the drift region to form the source region extending in the first direction in the body region, Forming the drain region extending in the first direction in the drift region and the ring-shaped inversion layer formation diffusion region spaced apart from the drain region; and
Forming the gate electrode through the gate insulating film over a part of the body region and over the well region at a position sandwiched between the body region and the drain region. It is what.

In addition to the above features, the semiconductor device of the present invention has
Another feature is that the drift region is formed so as to partially overlap the buried diffusion region in a ring shape.

In addition to the above features, the semiconductor device of the present invention has
The source region is formed by extending in a first direction parallel to the substrate surface,
Another feature of the present invention is that the distance between the drift region and the body region is wider in the first direction than in the second direction parallel to the substrate surface and perpendicular to the first direction.

In addition to the above features, the semiconductor device of the present invention has
The source region is formed by extending in a first direction parallel to the substrate surface,
With respect to the impurity concentration of the drift region, a region formed apart from the source region in the first direction is separated from a region formed parallel to the substrate surface and in a second direction perpendicular to the first direction. Another characteristic is that the concentration is high.

  In addition to the above-described feature, the semiconductor device of the present invention has another feature that the body contact region of the first conductivity type having a higher concentration than the body region is formed in the body region. .

  According to the semiconductor device of the present invention, it is possible to realize an LDMOS transistor having a further improved breakdown voltage while maintaining a low on-resistance.

1 is a schematic plan view of an LDMOS transistor according to a first embodiment of the present invention. Schematic sectional view taken along line L1-L2 in FIG. Schematic sectional view taken along line W1-W2 in FIG. Figure with added potential distribution when reverse bias is applied to Fig. 4. In FIG. 1, a graph showing the relationship between the implantation dose in the N-type drift region and the breakdown voltage in the W direction. In FIG. 1, a graph showing the relationship between the implantation dose in the N-type drift region and the breakdown voltage in the L direction. Another schematic plan view of the LDMOS transistor of the first embodiment of the present invention FIG. 1 is a graph comparing the breakdown voltage in the W direction with respect to the interval between the N-type drift region and the P-type body region in FIG. 1 when the interval in the W direction is wider than that in the L direction. Process sectional drawing which shows roughly the manufacturing process of the LDMOS transistor of 1st Embodiment of this invention Schematic plan view of the LDMOS transistor of the second embodiment of the present invention Comparison of plan views of the first and second embodiments Schematic plan view of an LDMOS transistor in the prior art Schematic sectional view taken along line L1-L2 in FIG. Schematic plan view when metal wiring is formed in an LDMOS transistor in the prior art Schematic sectional view taken along line W1-W2 in FIG. Schematic plan view of another conventional LDMOS transistor Schematic sectional view taken along line W1-W2 of FIG. Fig. 17 shows the addition of potential distribution when reverse bias is applied.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol is attached | subjected about the same component as FIGS. 12-18. Moreover, each plan view and cross-sectional view are schematically illustrated to the last, and the actual dimensional ratio and the dimensional ratio on the drawing do not necessarily match.

[First Embodiment]
FIG. 1 is a schematic plan view of the N-channel LDMOS transistor of the first embodiment. Moreover, the schematic sectional drawing in the L1-L2 line of FIG. 1 is shown in FIG. 2, and the schematic sectional drawing in the W1-W2 line is shown in FIG.

  The N-channel LDMOS transistor of this embodiment is largely different from the case of FIG. 16 in that an N-type drift region 7 is formed so as to surround the P-type body region 6. Note that the N-type drain region 10 is formed in the N-type drift region 7. The N-type drain region 10 is formed so as to surround the P-type body region 6 as in the case of FIG.

  In the configuration of this embodiment, the N-type well 2 is formed on the P-type semiconductor substrate 1, and the P-type buried diffusion region 4 is formed in the well 2. The interface between the P-type body region 6 and the P-type buried diffusion region 4 is in contact. Due to the presence of the P-type buried diffusion region 4, the depletion layer extends in the L direction along the interface between the buried diffusion region 4 and the N-type well 2 when a reverse bias is applied, so that the gate edge (region A in FIG. 2). It plays the role of preventing the electric field from concentrating on. In other words, it is provided for the purpose of improving the breakdown voltage in the L direction.

  That is, in order to enhance the effect of improving the breakdown voltage in the L direction, the P-type buried diffusion region 4 is formed to extend from the lower layer of the body region 6 to the outside of the drain side end of the gate electrode 11. It is preferable. FIG. 2 shows an example in which the N-type drain region 10 is formed so as to extend to a position below the N-type drain region 10.

  In FIG. 2, the equipotential surface of the potential is drawn together with the schematic cross-sectional view. According to this, the electric field concentration in the L direction is caused by the presence of the P-type buried diffusion region 4 extending in the L direction. As a result, it can be seen that the electric field concentration on the gate edge portion A is prevented.

  Further, according to the cross-sectional view taken along the line W1-W2 shown in FIG. 3, the high-concentration N-type drain region 10 is formed below the metal wiring 31 as in the case of FIG. Therefore, when the LDMOS transistor operates in the saturation region due to the presence of the drain region 10, more specifically, the N-type well 2 has a high potential (several tens of volts), and the gate-source voltage is about 5V. When the source potential is an intermediate potential between the High potential and the GND potential, since the inversion layer (hole) is not formed immediately below the element isolation region 21 in the region D, the P-type body region 6 and the P-type semiconductor substrate 1 are electrically connected. There is no such thing. This is common with FIG. 17 in that the versatility of the circuit is enhanced compared to the configuration of FIG.

  However, in the case of the configuration of FIG. 17, the electric field concentrates on the drain edge E of the N-type drain 10 at a position facing the source region 9 (body region 6) in the W direction. (See FIG. 18). According to the configuration of this embodiment, this problem is solved by forming the N-type drift region 7 in a loop shape.

  FIG. 4 is obtained by adding an equipotential surface of the potential in FIG. 3, which corresponds to FIG. 18 in the conventional configuration. Due to the presence of the N-type drift region 7, the equipotential surface of the potential is pushed back toward the P-type body region, thereby reducing the concentration of the electric field on the edge portion (E in the figure) of the N-type drain region 10. Yes.

  In order to make such an effect more remarkable, as shown in FIG. 4 (FIG. 3), the inner edge of the ring-shaped N-type drift region 7 is located on the inner side (P-type body) than the outer edge of the P-type buried diffusion region 4. It is preferable to form it so as to be located on the region 6 side). As a result, the depletion layer formed when the reverse bias is applied is pushed back in the direction away from the P-type body region 6 side, that is, the N-type drain region 10, and as a result, the function of reducing the concentration of the electric field on the drain edge E is achieved. Can be increased.

  5 and 6 are graphs showing the effect of introducing the N-type drift region 7. That is, it is a graph showing the relationship between the dose (horizontal axis) implanted as the N-type drift region 7 and the breakdown voltage (vertical axis). FIG. 5 is a graph showing a change in breakdown voltage in the W direction (direction parallel to the W1-W2 line), and FIG. 6 is a graph showing a change in breakdown voltage in the L direction (direction parallel to the L1-L2 line).

  5 and 6, the case where the implantation dose amount of the N-type drift region 7 is 0 corresponds to the case where the N-type drift region 7 is not formed in the configuration of FIG. 1.

  As can be seen from FIG. 5, the breakdown voltage in the W direction increases as the implantation dose into the N-type drift region 7 increases (the impurity concentration in the N-type drift region 7 increases).

  With respect to the breakdown voltage in the W direction, as described with reference to FIG. 18, when the implantation dose amount of the N-type drift region 7 is 0, the depletion layer becomes the P-type body region 6 due to the field plate effect of the metal wiring 31. As a result, the electric field concentrates on the drain edge E, and the breakdown voltage decreases. This is because even if the P-type buried diffusion region 4 is formed as shown in FIG. 3, the position where the depletion layer starts to extend is closer to the drain 10 side than the end on the drain side of the P-type body region 6. Can be discussed in the same way.

  On the other hand, by introducing the N-type drift region 7, it is possible to suppress the depletion layer from extending to the drain 10 side (see FIG. 4). As the dose amount to the N-type drift region 7 is increased (as the impurity concentration of the N-type drift region 7 is increased), the effect is increased. This is also evident in the rise in the breakdown voltage.

  Next, regarding the breakdown voltage in the L direction, as described above, the configuration of the present embodiment includes the P-type buried diffusion region 4 to disperse the electric field in the L direction, thereby the gate edge portion A on the drain side. Electric field concentration on the surface can be reduced (RESURF effect, see FIG. 2). Therefore, the presence of the P-type buried diffusion region 4 can improve the breakdown voltage in the L direction. Therefore, when the same breakdown voltage is ensured, the on-resistance can be reduced by increasing the concentration of the N-type drift region 7. This can improve the trade-off relationship between breakdown voltage and on-resistance.

  According to FIG. 6, the withstand voltage in the L direction decreases to a certain extent as the implantation dose into the N-type drift region 7 is increased. This is because the concentration of the N-type drift region 7 is increased, so that the RESURF effect by the P-type buried diffusion region 4 is suppressed, so that the electric field concentration at the gate edge portion A on the drain side is not sufficiently relaxed. .

  However, the graph of FIG. 6 is based on the premise that the breakdown voltage in the L direction is increased by forming the P-type buried diffusion region 4 to the last. Under such a configuration, the breakdown voltage in the W direction is lower than the breakdown voltage in the L direction. As a result, the breakdown voltage in the W direction needs to be increased to the same level as the breakdown voltage in the L direction.

  That is, in FIG. 6, it seems that the breakdown voltage is lowered at first glance by introducing the N-type drift region 7, but as can be seen by comparing with FIG. 5, if the N-type drift region 7 is not introduced, the W direction is obtained. Since the breakdown voltage in the L direction is lower than that in the W direction, breakdown occurs when a reverse bias voltage exceeding the breakdown voltage in the W direction is applied. That is, by introducing the N-type drift region 7 with a dose such that the breakdown voltage in the W direction is approximately the same as the breakdown voltage in the L direction, an effect of maximizing the breakdown voltage of the entire LDMOS transistor can be exhibited. Naturally, under the condition that the breakdown voltage in the W direction is lower than the breakdown voltage in the L direction, the effect of increasing the breakdown voltage is exhibited as the dose is increased.

  For example, according to the examples of FIGS. 5 and 6, when the normalized-dose amount of the N-type drift region is set to 1.5, the breakdown voltages in the W direction and the L direction can both be set to about 120V. If the dose is smaller than this, the breakdown voltage in the W direction is lower than the breakdown voltage in the L direction, and conversely, if the dose is large, the breakdown voltage in the L direction is lower than the breakdown voltage in the W direction.

  According to the example of FIG. 5, the breakdown voltage in the W direction has about 70 V when the N-type drift region 7 is not introduced. Nevertheless, the necessity for improving the breakdown voltage in the W direction arises because the breakdown voltage in the L direction is dramatically increased by introducing the P-type buried diffusion region 4. In other words, even if it is accepted that the L direction is lowered to some extent by introducing the N type drift region 7, this has the effect of improving the breakdown voltage in the W direction lower than the breakdown voltage in the L direction. This is an advantage of introducing the drift region 7.

  5 and FIG. 6, it is preferable to increase the dose amount of the N-type drift region 7 in order to increase the breakdown voltage in the W direction, and to increase the breakdown voltage in the L direction. It is preferable not to increase the dose of 7. For this reason, it is also useful to vary the dose amount of the N-type drift region 7 between the region extending in the L direction and the region extending in the W direction.

  That is, as shown in FIG. 7, for the concentration of the N-type drift region 7, the concentration of the region 7a contributing to the breakdown voltage in the W direction is set higher than the concentration of the region 7b contributing to the breakdown voltage in the L direction. More specifically, the concentration of the region 7a facing the source region 9 in the W direction is set higher than the concentration of the region 7b facing the L direction. Thereby, the pressure | voltage resistance of a W direction can be improved, suppressing the pressure | voltage fall in the L direction.

  Note that the N-type drift region 7b formed away from the source region 9 in the L direction corresponds to a position below the region extending in the W direction in the N-type drain region 10 formed in a ring shape. . Similarly, the N-type drift region 7a formed apart from the source region 9 in the W direction corresponds to a position below the region extending in the L direction in the N-type drain region 10 formed in a ring shape. To do.

  Furthermore, in order to reduce the electric field concentration in the W direction, it is also useful to make the interval between the P-type body region 6 and the N-type drift region 7 different in the W direction and the L direction. That is, the interval Y in the W direction between the P-type body region 6 and the N-type drift region 7 is made larger than the interval X in the W direction (see FIGS. 1, 2, and 3).

  In such a structure, when a reverse bias is applied, the depletion layer extends from the P-type body region 6 toward the N-type drift region 7, but the distance between both is wider in the W direction than in the L direction. Electric field concentration in this direction is alleviated. FIG. 8 shows a case where the interval between the P-type body region 6 and the N-type drift region 7 is made equal in the W direction and the L direction (Y = X), and a case where the interval in the W direction is wider than the L direction (Y> X ), The breakdown voltage in the W direction is compared, and it can be seen that the breakdown voltage in the W direction is increased by setting Y> X.

  As described above, (1) forming the N-type drift region 7 in a ring shape so as to surround the body region 6 has the effect of increasing the breakdown voltage in the W direction, as in the configuration of the present embodiment. (2) With respect to the drift region 7, the implantation dose amount (impurity concentration) in the region facing the W direction is higher than the region facing the source region in the L direction, thereby suppressing a decrease in breakdown voltage in the L direction. The effect of increasing the breakdown voltage in the W direction can be further exhibited. Further, (3) by making the interval Y in the W direction between the P-type body region 6 and the N-type drift region 7 larger than the interval X in the L direction, the effect of further increasing the breakdown voltage in the W direction can be increased. That is, the provision of only (1) has the effect of improving the breakdown voltage in the W direction, and when the elements (2) and (3) are included in this, the effect can be further improved.

  Hereinafter, the manufacturing method of the LDMOS transistor of this embodiment will be described with reference to the process cross-sectional view of FIG. Note that a case of manufacturing an LDMOS transistor having a structure satisfying all of the above (1), (2), and (3) will be described as an example. However, a case where only (1) is satisfied or (1) and (2) ) Or a case where (1) and (3) are satisfied.

As shown in FIG. 9A, N-type impurities are implanted into the P-type semiconductor substrate 1, and the N-type well 2 is formed to a desired depth by thermal diffusion by high-temperature drive-in. As the N-type impurity, for example, phosphorus is used, the implantation energy is, for example, 2 MeV or more, and the dose is 1.0 × 10 ¹³ cm ⁻² or less. Further, the region where the impurity is implanted is defined by, for example, using a thick resist corresponding to high energy implantation and patterning the region where the implantation is performed by using a photoetching technique or the like. Further, an element isolation region 21 (LOCOS oxide film) is formed on a part of the surface of the N-type well 2.

  Next, a P-type body region 6 is formed by implanting a P-type impurity such as boron. Further, a P-type impurity, for example, boron is implanted by high energy implantation of 1 MeV or more to form the P-type buried diffusion region 4.

  Next, as shown in FIG. 9B, an N-type impurity, for example, phosphorus is implanted at a position separated from the P-type body region 6 with an implantation energy of, for example, 300 KeV or more, and the N-type drift regions 7a, 7b is formed. Here, when forming the N-type drift region 7a, a resist mask different from that of the N-type drift region 7b is used, and the interval between the P-type body region 6 and the N-type drift region 7 is set to the interval Y in the W direction. Is defined to be larger than the interval X in the L direction (Y> X), the resist mask is defined. Further, at this time, the implantation dose of the N-type drift region 7a is set higher than the implantation dose of the N-type drift region 7b.

  Next, a gate insulating film is formed in the surface region of the N-type well 2, and the gate electrode 11 is formed from a part of the P-type body region 6 to a part of the element isolation region 21. In forming the gate electrode 11, for example, a polysilicon film doped with phosphorus is formed by a CVD method, a resist is patterned thereon by a photoetching technique, and then the polysilicon film is processed by a dry etching technique or the like. It is formed by doing.

  Next, as shown in FIG. 9C, an N-type source region 8 and an N-type drain region 10 are formed by, for example, implantation of phosphorus or arsenic, and further, for example, a P-type body contact region 9 is implanted by implantation of boron or the like. Form.

  Next, as shown in FIG. 9D, an interlayer insulating film 22 is formed on the surface by, for example, atmospheric pressure CVD, and reflowed to reduce the surface step. Thereafter, contact etching is performed on the oxide film above the gate electrode 11, the N-type drain region 10, the N-type source region 8, and the P-type body contact region 9 to form contact holes. Thereafter, for example, after an aluminum film is grown by sputtering, the aluminum film is patterned by photo etching and dry etching to form the source electrode 16, the drain electrode 15, and the metal wiring 31. The metal wiring 31 may be formed at the same time as the source electrode 16 and the drain electrode 15 or may be formed after the source electrode 16 and the drain electrode 15 are formed.

[Second Embodiment]
In the first embodiment, similarly to FIG. 16 of the conventional configuration, the N-type drain region 10 is formed so as to surround the P-type body region 6, whereby an inversion layer is formed when a reverse bias is applied, and the P-type body region 6. And the P-type semiconductor substrate 1 are prevented from conducting. That is, by forming the N-type drain region 10 in a ring shape, it has a function as a normal drain and a function of suppressing the formation of an inversion layer in the W direction.

  On the other hand, the configuration (schematic plan view) of this embodiment shown in FIG. 10 divides a functional region as a drain and a suppression functional region for forming an inversion layer in the W direction. That is, the N-type drain 10 has a shape extending in the W direction as shown in FIG. 12 (a shape facing the source region 9 in the L direction) and is not formed in a ring shape. On the other hand, on the outside of the drain 10, a high-concentration N-type region 27 (inversion layer formation preventing diffusion region) similar to the N-type drain 10 is formed in a ring shape so as to surround the body region 6. The N-type region 27 is formed in the N-type drift region 7 like the N-type drain region 10, and is separated from the N-type drain region 10 via the element isolation region in the L direction.

  Even in such a configuration, the high-concentration N-type region 27 is formed at a position spaced apart from the P-type body region 6 in the W direction. No inversion layer is formed below, so that no leak path is formed between the P-type body region 6 and the P-type semiconductor substrate 1 when a reverse bias is applied.

  As in the first embodiment, since the N-type region 27 is formed in the N-type drift region 7 formed in a ring shape, an electric field is concentrated near the edge of the high-concentration N-type region 27. Can also be avoided. The reason for this can be described with reference to FIG. 4 as in the first embodiment, and therefore the description thereof is omitted here.

  Furthermore, according to the configuration of the present embodiment, there is an effect that the tolerance at the time of applying overvoltage such as surge or overcurrent is higher than that of the first embodiment. This point will be described with reference to FIG.

  FIG. 11 shows the configuration (a) of the first embodiment and the configuration (b) of the present embodiment side by side.

  In the case of the configuration of the first embodiment shown in FIG. 11A, since the N-type drain region 10 is formed in a ring shape, when a potential difference is applied between the source region 9 and the drain region 10, the L direction is changed. In addition to the normal drain current flowing between the source region 9 and the drain region 10 facing each other, a sneak current having a direction component in the W direction is generated.

  In general, when an overvoltage or overcurrent such as a surge is applied to the drain region of an LDMOS transistor, first, an avalanche breakdown occurs near the drain region due to an increase in the electric field due to the overvoltage, and the generated hole is a P-type body. A parasitic bipolar transistor including an N-type drain region, a P-type body region, and an N-type source region is turned on by a potential difference when flowing in the region. As a result, a large current flows from the drain region to the source region, eventually leading to thermal destruction.

  When an overvoltage or overcurrent such as a surge is applied to the drain region, the electric field is most concentrated at the corners of the P-type body 6 region (F1 in FIG. 11A, F2 in FIG. 11B). is there. Therefore, when a sneak current as shown in FIG. 11A occurs in the F1 portion, there is a possibility of promoting an increase in the avalanche current when an overvoltage or overcurrent such as a surge is applied.

  On the other hand, in the configuration of the present embodiment, a ring-shaped N-type region 27 is provided separately from the N-type drain region 10, and the N-type drain region 10 faces the N-type source region 9 only in the L direction. It is the structure to do. Since the N-type region 27 is formed outside the N-type drain region 10, the distance between the N-type region 27 and the source region 9 is larger than the distance between the drain region 10 and the source region 9. As a result, when a potential difference is applied between the source and the drain, a normal drain current parallel to the L direction flows. On the other hand, a sneak current from the source region 9 to the N-type region 27 is significantly higher than in the case of (a). descend.

  That is, by adopting the configuration of the present embodiment, it is possible to increase the resistance (surge resistance) at the time of application of overvoltage and overcurrent, compared to the configuration of the first embodiment. However, on the other hand, since the N-type region 27 different from the drain region 10 needs to be formed in a ring shape outside the drain region 10, the occupied area is increased as compared with the first embodiment. For this reason, it is effective to use the configuration as in this embodiment particularly when transistors are arrayed in a large area. In that case, the high-concentration N-type region 27 formed for preventing channel inversion should be formed only on the outermost periphery of the transistors arrayed in a large area. With this configuration, it is possible to reduce the ratio of the additional area by providing the N-type region 27 when the original occupied area is used as a reference, and it is possible to minimize the influence of the area increase.

  Needless to say, the elements (2) and (3) described in the first embodiment can be applied to the structure of the present embodiment.

[Another embodiment]
Another embodiment will be described below.

  <1> In the structure of the present invention described above, the gate electrode 11 is illustrated as having a polygonal shape composed of a component parallel to the L direction and a component parallel to the W direction. It is not something. For example, a track shape (oval shape) as shown in FIG. 12 may be used.

  <2> In the structure of the present invention, the N-type well 2 is formed deeper than in the case of FIG. 13, thereby omitting the formation of the N-type buried diffusion region 102 of FIG. It is also possible to form the buried diffusion region 102. However, since it is actually difficult to form the N-type buried diffusion region 102 by ion implantation, it is difficult to form such a structure. Usually, a forming process is used. Since the epi formation process is an expensive process, the configuration of the above-described embodiment that does not require an epi formation process in manufacturing is more useful in that the manufacturing cost can be reduced.

  In the N-type buried diffusion region 102 in FIG. 13, when the LDMOS transistor is used on the high voltage side, the P-type body region 6 is fixed at a high potential when the transistor is turned on. It is provided for the purpose of suppressing the influence of the vertical parasitic bipolar transistor composed of the N-type well 2 and the P-type semiconductor substrate 100. In particular, when the hFE of the parasitic transistor is high, power consumption due to a current flowing from the P-type body region 6 toward the P-type semiconductor substrate 100 increases. Therefore, for the purpose of reducing the hFE, the N-type buried diffusion region is used. 102 is formed.

  In other words, when the vertical parasitic current based on hFE of the vertical parasitic PNP transistor does not become a big problem in the first place, such an N-type buried diffusion region 102 is unnecessary. Furthermore, by forming the N-type well 2 as a region deeper than the configuration of FIG. 13 as shown in FIG. 2, the same effect (decrease in hFE) as when the N-type buried diffusion region 102 is provided can be exhibited. .

  <3> In each of the above-described embodiments, an N-channel LDMOS transistor having a P-type body region and N-type source / drain regions on a P-type semiconductor substrate has been described. By inversion, it is possible to realize a P-channel type LDMOS transistor exhibiting the same effect.

  <4> In each of the above-described embodiments, the source electrode 16 is formed so as to be in contact with both the source region 8 and the body contact region 9. It is good also as a structure provided.

1: P-type semiconductor substrate 2: N-type well 4: Buried diffusion region 6: P-type body region 7: N-type drift region 8: N-type source region 9: P-type body contact region 10: N-type drain region 11: Gate Electrode 15: Drain electrode 16: Source electrode 21: Element isolation region 22: Interlayer insulating film 27: High concentration N-type region (diffusion region for preventing inversion layer formation)
31: Metal wiring 100: P-type semiconductor substrate 101: P-type epitaxial layer 102: N-type buried diffusion region

Claims (8)

A second conductivity type well different from the first conductivity type formed on the first conductivity type semiconductor substrate;
A body region of the first conductivity type formed in the well;
In the well, the buried diffusion region of the first conductivity type formed at a position deeper than the body region so as to be in contact with the bottom surface of the body region;
A source region of the second conductivity type formed in the body region and having a higher concentration than the well;
In the well, the drift region of the second conductivity type having a higher concentration than the well formed at a position separated from the body region in a direction parallel to the substrate surface of the semiconductor substrate;
In the drift region, the drain region of the second conductivity type having a concentration higher than that of the drift region, formed at a position spaced apart from the body region and the element isolation region in a direction parallel to the substrate surface of the semiconductor substrate. When,
A gate electrode formed through a gate insulating film over at least a part of the body region and over the well region at a position sandwiched between the body region and the drain region;
The semiconductor device, wherein the drift region and the drain region are formed in a ring shape so as to surround the body region. A second conductivity type well different from the first conductivity type formed on the first conductivity type semiconductor substrate;
A body region of the first conductivity type formed in the well;
In the well, the buried diffusion region of the first conductivity type formed at a position deeper than the body region so as to be in contact with the bottom surface of the body region;
A source region of the second conductivity type formed in the body region and having a higher concentration than the well;
In the well, the drift region of the second conductivity type having a higher concentration than the well formed at a position separated from the body region in a direction parallel to the substrate surface of the semiconductor substrate;
In the drift region, the drain region of the second conductivity type having a concentration higher than that of the drift region, formed at a position spaced apart from the body region and the element isolation region in a direction parallel to the substrate surface of the semiconductor substrate. When,
In the drift region, a diffusion region for preventing inversion layer formation of the second conductivity type having a higher concentration than the drift region, formed at a position spaced apart from the drain region in a direction parallel to the substrate surface of the semiconductor substrate; ,
A gate electrode formed through a gate insulating film over at least a part of the body region and over the well region at a position sandwiched between the body region and the drain region;
The source region is formed by extending in a first direction parallel to the substrate surface,
The drain region is formed to be opposed to the body region in a second direction that is parallel to the substrate surface and perpendicular to the first direction, but is not opposed to the first direction.
The drift region is formed in a ring shape so as to surround the body region, and the inversion layer formation preventing diffusion region is formed in a ring shape so as to surround the body region in the drift region at a position outside the drain region. A semiconductor device characterized in that the semiconductor device is formed.   3. The semiconductor device according to claim 1, wherein a part of the drift region overlaps with the buried diffusion region in a ring shape. 4. The source region is formed by extending in a first direction parallel to the substrate surface,
The interval between the drift region and the body region is wider in the first direction than in a second direction that is parallel to the substrate surface and orthogonal to the first direction. 2. The semiconductor device according to claim 1. The source region is formed by extending in a first direction parallel to the substrate surface,
With respect to the impurity concentration of the drift region, a region formed apart from the source region in the first direction is separated from a region formed parallel to the substrate surface and in a second direction perpendicular to the first direction. The semiconductor device according to claim 1, wherein the concentration of the semiconductor device is high.   6. The semiconductor device according to claim 1, wherein the body contact region of the first conductivity type having a higher concentration than the body region is formed in the body region. A method of manufacturing a semiconductor device according to claim 1,
Implanting the second conductivity type impurity ions into the first conductivity type semiconductor substrate to form the well region;
Forming the element isolation region;
Implanting impurity ions of the first conductivity type into the well to form the body region and the buried diffusion region;
Implanting impurity ions of the second conductivity type at a concentration higher than that of the well into the well to form the ring-shaped drift region so as to surround the body region or a region to be formed;
Impurity ions of the second conductivity type having a concentration higher than that of the drift region are implanted into the body region and the drift region, the source region is implanted into the body region, and the ring-shaped region is implanted into the drift region. Forming each drain region; and
Forming the gate electrode through the gate insulating film over a part of the body region and over the well region at a position sandwiched between the body region and the drain region. A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 2,
Implanting the second conductivity type impurity ions into the first conductivity type semiconductor substrate to form the well region;
Forming the element isolation region;
Implanting impurity ions of the first conductivity type into the well to form the body region and the buried diffusion region;
Implanting impurity ions of the second conductivity type at a concentration higher than that of the well into the well to form the ring-shaped drift region so as to surround the body region or a region to be formed;
Injecting impurity ions of the second conductivity type having a concentration higher than that of the drift region in the body region and the drift region to form the source region extending in the first direction in the body region, Forming the drain region extending in the first direction in the drift region and the ring-shaped inversion layer formation diffusion region spaced apart from the drain region; and
Forming the gate electrode through the gate insulating film over a part of the body region and over the well region at a position sandwiched between the body region and the drain region. A method for manufacturing a semiconductor device.

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