WO2012107998A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2012107998A1
WO2012107998A1 PCT/JP2011/052635 JP2011052635W WO2012107998A1 WO 2012107998 A1 WO2012107998 A1 WO 2012107998A1 JP 2011052635 W JP2011052635 W JP 2011052635W WO 2012107998 A1 WO2012107998 A1 WO 2012107998A1
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WO
WIPO (PCT)
Prior art keywords
inner peripheral
element isolation
isolation structure
region
axis direction
Prior art date
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PCT/JP2011/052635
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French (fr)
Japanese (ja)
Inventor
寺田　隆司
Original Assignee
ルネサスエレクトロニクス株式会社
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Application filed by ルネサスエレクトロニクス株式会社 filed Critical ルネサスエレクトロニクス株式会社
Priority to PCT/JP2011/052635 priority Critical patent/WO2012107998A1/en
Priority to TW100142388A priority patent/TW201234595A/en
Publication of WO2012107998A1 publication Critical patent/WO2012107998A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0882—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/086—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a semiconductor device having a lateral structure transistor.
  • a so-called lateral structure MIS (Metal Insulator Semiconductor) transistor in which a current flows in a lateral direction has a structure in which a source region is surrounded by a drain region on the main surface of a semiconductor substrate.
  • MIS Metal Insulator Semiconductor
  • Such a structure is disclosed in, for example, Japanese Patent Application Laid-Open No. 10-50985 (Patent Document 1), Japanese Patent Application Laid-Open No. 2007-96143 (Patent Document 2), Japanese Patent Application Laid-Open No. 2008-4600 (Patent Document 3), and the like. Yes.
  • Patent Document 4 describes a technique in which a metal wiring connected to a drain region is overlapped with an isolation region at a drain end, and the electric field concentration at the drain end is reduced by the electric field of the metal wiring. (RESURF (REduced SURface Field) effect) is described to improve the off breakdown voltage.
  • the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of improving the breakdown voltage.
  • a semiconductor device includes a semiconductor substrate, a first conductivity type source region, a second conductivity type body region, an element isolation structure, a first conductivity type drift region, and a gate electrode layer. And.
  • the semiconductor substrate has a main surface.
  • the source region is disposed on the main surface thereof.
  • the body region is arranged in the semiconductor substrate so as to surround the periphery of the source region in plan view.
  • the element isolation structure is disposed so as to surround the body region with a space from the body region in plan view.
  • the drift region is disposed in the semiconductor substrate so as to surround the body region with a space from the body region in plan view and to contact the lower surface of the element isolation structure.
  • the gate electrode layer surrounds the periphery of the source region in plan view, and is disposed on the body region and the element isolation structure.
  • Each of the inner peripheral side edge of the drift region and the inner peripheral side edge of the element isolation structure is a plane extending in the major axis direction longer than the minor axis direction in the major axis direction and the minor axis direction orthogonal to each other in plan view. It has a shape.
  • the inner peripheral edge of the drift region is positioned at the outer peripheral side of the inner peripheral edge of the element isolation structure at least at a part of both ends in the long axis direction, and the long axis is sandwiched between the both ends Is located on the inner peripheral side with respect to the inner peripheral side edge of the element isolation structure.
  • the inner peripheral side edge of the drift region in the plan view is at the outer peripheral side of the inner peripheral side edge of the element isolation structure in at least a part of both ends in the major axis direction Is located. For this reason, the breakdown voltage can be improved at least at a part of both ends.
  • the inner peripheral side edge of the drift region in a plan view is larger than the inner peripheral side edge of the element isolation structure at the central portion in the major axis direction sandwiched between both end portions. Located on the inner circumference. For this reason, the on-resistance can be reduced at the center.
  • FIG. 1 is a plan view schematically showing the configuration of the semiconductor device according to the first embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional view taken along the line II-II in FIG. It is a schematic plan view for demonstrating an edge part. It is an expanded sectional view which abbreviate
  • FIG. 3 is an enlarged cross-sectional view in which a part of a region R2 in FIG. 2 is omitted. Impurity concentration distribution along the line A1-A1 in FIG. 4 and impurity concentration along the line A2-A2 in FIG.
  • (A) is a plan view schematically showing a configuration of a semiconductor device in a comparative example
  • (B) is a schematic cross-sectional view taken along line XB-XB in FIG. 10 (A).
  • FIG. 11 is a schematic sectional view taken along line XI-XI in FIG.
  • FIG. 16 is a schematic cross-sectional view taken along line XVI-XVI in FIG. (A) is a plan view schematically showing the configuration of the semiconductor device according to the third embodiment of the present invention, and (B) is a schematic cross-sectional view taken along line XVIIB-XVIIB in FIG. 17 (A).
  • FIG. 18 is a schematic sectional view taken along the line XVIII-XVIII in FIG.
  • Embodiment 1 First, the structure of Embodiment 1 of the present invention will be described with reference to FIGS. 1A, 1B, and 2.
  • FIG. 1A, 1B, and 2 Second, the structure of Embodiment 1 of the present invention will be described with reference to FIGS. 1A, 1B, and 2.
  • the semiconductor device of the present embodiment has a high breakdown voltage MIS transistor TR.
  • the MIS transistor TR has a so-called lateral structure and is formed on the main surface of the semiconductor substrate SUB.
  • a p ⁇ region PR is formed inside the semiconductor substrate SUB.
  • the MIS transistor TR is formed in the n-type well region NWR.
  • the MIS transistor TR includes a plurality of n + source regions NSR (FIG. 1B), a plurality of p + body contact regions PBC (FIG. 2), an n ⁇ region NLD, a p-type body region BR, n A drain region NDR, an n-type drift region DRI, a low-concentration n-type region LNW, a gate insulating layer GI, and a gate electrode layer GE are mainly included.
  • a plurality of n + source regions NSR and a plurality of p + body contact regions PBC are formed on the main surface of the semiconductor substrate SUB.
  • n + source regions NSR and p + body contact regions PBC are arranged alternately.
  • N + source region NSR is formed shallower than the main surface of semiconductor substrate SUB than p + body contact region PBC.
  • n ⁇ region NLD is formed on the main surface of the semiconductor substrate SUB.
  • N ⁇ region NLD surrounds the main surface of semiconductor substrate SUB around the arrangement region of a plurality of n + source regions NSR and a plurality of p + body contact regions PBC arranged alternately.
  • the lateral side and lower side of n + source region NSR and the lateral side of p + body contact region PBC are covered with n ⁇ region NLD.
  • the lower side of p + body contact region PBC is formed deeper than n ⁇ region NLD and is in contact with p type body region BR.
  • the p-type body region BR is formed on the main surface of the semiconductor substrate SUB.
  • the p-type body region BR surrounds the plurality of n + source regions NSR, the plurality of p + body contact regions PBC and the n ⁇ region NLD on the main surface of the semiconductor substrate SUB, and the n-type well regions NWR and pn It constitutes a joint.
  • N + drain region NDR is formed on the main surface of semiconductor substrate SUB at a distance from p-type body region BR.
  • Element isolation structures IS1 and IS2 are formed on the main surface of the semiconductor substrate SUB, and the n + drain region NDR is formed so as to be sandwiched between the element isolation structures IS1 and IS2 on the main surface of the semiconductor substrate SUB. ing.
  • Each of the element isolation structures IS1 and IS2 includes, for example, STI (Shallow Trench Isolation), LOCOS (LOCal Oxidation of Silicon), and the like.
  • STI Shallow Trench Isolation
  • LOCOS LOCOS
  • each of the element isolation structures IS1 and IS2 includes a trench TRE formed in the main surface of the semiconductor substrate SUB, and an insulating layer IL filling the trench TRE. have.
  • N ⁇ region NLD is formed in contact with the lower side of n + drain region NDR.
  • the low concentration n-type region LNW is formed in the semiconductor substrate SUB so as to be in contact with the lower surface of the n ⁇ region NLD under the n + drain region NDR and the lower surfaces of the element isolation structures IS1 and IS2.
  • the n-type drift region DRI is formed in the semiconductor substrate SUB so as to contact the lower surfaces of the low-concentration n-type region LNW and the element isolation structures IS1 and IS2.
  • An n-type well region NWR is located on the main surface of the semiconductor substrate SUB between the n-type drift region DRI and the p-type body region BR.
  • N-type drift region DRI has an n-type impurity concentration lower than that of n + drain region NDR and an n-type impurity concentration higher than that of n-type well region NWR.
  • the low concentration n-type region LNW has a higher n-type impurity concentration than the n-type drift region DRI.
  • the n ⁇ region NLD has a higher n-type impurity concentration than the low-concentration n-type region LNW and a lower n-type impurity concentration than the n + drain region NDR.
  • the gate electrode layer GE is formed on the p-type body region BR, the n-type drift region DRI, and the n-type well region NWR with a gate insulating layer GI interposed therebetween.
  • the outer peripheral edge GEO of the gate electrode layer GE rides on the element isolation structure IS1, so that the gate electrode layer GE faces the n-type drift region DRI across the element isolation structure IS1.
  • Sidewall insulating layer SW is formed so as to cover the side surface of gate electrode layer GE.
  • the n ⁇ region NLD described above is located on the main surface of the semiconductor substrate SUB under the side wall insulating layer SW in contact with the inner peripheral edge GEI of the gate electrode layer GE and the n + drain region NDR.
  • Silicide layer SC is formed on the surfaces of n + drain region NDR, n + source region NSR, p + body contact region PBC, and gate electrode layer GE.
  • Wiring layer ICL is electrically connected to n + drain region NDR with conductive plug layer PL interposed.
  • Wiring layer ICL is electrically connected to each of a plurality of n + source regions NSR and each of a plurality of p + body contact regions PBC with conductive plug layer PL interposed therebetween.
  • a wiring layer (not shown) is also electrically connected to the gate electrode layer GE via a conductive plug layer PL.
  • a p-type well region PWR is formed in the semiconductor substrate SUB so as to be in contact with the side portions of the n-type drift region DRI and the n-type well region NWR and in contact with the lower surface of the element isolation structure IS2.
  • a p + contact region PSDR is formed on the main surface of the semiconductor substrate SUB in the p-type well region PWR.
  • n + source regions NSR and p + body contact regions PBC are alternately arranged along the major axis direction (vertical direction in the drawing) in plan view.
  • p type body region BR surrounds a plurality of n + source regions NSR and a plurality of p + body contact regions PBC with n ⁇ region NLD interposed therebetween.
  • the element isolation structure IS1 surrounds the outer peripheral side edge BRO of the p-type body region BR with a space therebetween.
  • n type drift region DRI surrounds outer peripheral side edge BRO of p type body region BR with n type well region NWR interposed.
  • n + drain region NDR surrounds the periphery of a plurality of n + source regions NSR with p-type body region BR, element isolation structure IS1 and the like interposed therebetween.
  • element isolation structure IS2 surrounds the outer periphery of n + drain region NDR.
  • Each of the inner circumferential edge GEI and the outer circumferential edge GEO is longer in the major axis direction than the minor axis direction in the major axis direction and the minor axis direction (left and right direction in the figure) orthogonal to each other in plan view. It has a planar shape that extends.
  • Each of the side edges IS2I has a rectangular planar shape that is long in the long axis direction and short in the short axis direction.
  • Each of the outer peripheral side edge BRO of the p-type body region BR, the inner peripheral side edge IS1I of the element isolation structure IS1, and the outer peripheral side edge GEO of the gate electrode layer GE has a central portion and central portions of both end portions. It has a substantially track-shaped planar shape that is formed in a straight line shape and that has an intermediate portion (corner portion) at both ends in a round shape.
  • the round shape in the intermediate portion is an arc (quarter circle) centering on the corner of the rectangular planar shape of the gate electrode layer GE.
  • the substantially track shape is a shape in which a portion to be a rectangular corner is a round shape (arc).
  • the both ends have a central portion serving as an end in the major axis direction and an intermediate portion (corner portion) positioned between the central portion and the intermediate portion.
  • the inner peripheral edge DRII of the n-type drift region DRI is at least a part (intermediate portion (corner portion)) of both ends in the major axis direction and is more outer than the inner peripheral edge IS1I of the element isolation structure IS1. Located on the side. Further, the inner peripheral edge DRII of the n-type drift region DRI in plan view is more than the inner peripheral edge IS1I of the element isolation structure IS1 at the central portion in the major axis direction sandwiched between both ends and the central portion of both ends. Located on the inner circumference.
  • the rectangular planar corner portion of the inner peripheral edge DRII of the n-type drift region DRI is on the outer peripheral side than a part of the intermediate portion of the round shape (arc) of the inner peripheral edge IS1I of the element isolation structure IS1. Is located.
  • the distance between the outer peripheral side edge BRO of the p-type body region BR in the central part and the inner peripheral side edge DRII of the n-type drift region DRI is larger than that of the p-type body region BR in the intermediate part (corner part).
  • the distance L2 between the outer peripheral edge BRO and the inner peripheral edge DRII of the n-type drift region DRI is larger.
  • the distance L3 between the outer peripheral edge BRO of the p-type body region BR and the inner peripheral edge DRII of the n-type drift region DRI at the center of both ends is substantially the same as the distance L1.
  • the n-type drift region DRI covers the inner peripheral edge IS1I of the element isolation structure IS1.
  • the n-type drift region DRI does not cover the inner peripheral edge IS1I of the element isolation structure IS1, and the inner peripheral edge of the element isolation structure IS1.
  • IS1I is in contact with the n-type well region NWR.
  • the width in plan view between the inner peripheral edge IS1I and the outer peripheral edge IS1O of the element isolation structure IS1 is larger than the width W1 of the element isolation structure IS1 in the center.
  • the width W2 of the element isolation structure IS1 is larger in at least a part (intermediate portion (corner portion)) of both end portions in the long axis direction.
  • the length G1 of the gate electrode layer GE riding on the element isolation structure IS1 in the center in the width in a plan view in the direction from the inner peripheral edge GEI to the outer peripheral edge GEO of the gate electrode layer GE is a long axis.
  • the length G2 is substantially the same as the length G2 over which the gate electrode layer GE rides on the element isolation structure IS1 in at least a part of both ends in the direction.
  • plan view in this specification means a state seen in a plan view in FIG. 1A and the like, and means a state seen from a direction perpendicular to the main surface of the semiconductor substrate SUB.
  • planar shape in this specification means a shape seen in a plan view in FIG. 1A and the like, and means a shape seen from a direction perpendicular to the main surface of the semiconductor substrate SUB.
  • the length G2 of the intermediate part (corner part) in the above is defined as follows. Referring to FIG. 3, inner edge IS1I of element isolation structure IS1 along a perpendicular line (E1-E1 line) with respect to arc tangent D1-D1 in the middle of inner edge IS1I of element isolation structure IS1. And the distance between the outer peripheral edge GEO of the gate electrode layer GE is the length G2. The width W2 and the distance L2 are defined similarly to the length G2.
  • FIG. 4 is an enlarged view of the region R1 in FIG. 1B.
  • the impurity concentration distribution at the position of the A1-A1 line immediately below the main surface of the semiconductor substrate SUB in FIG. 4 is indicated by the A1-A1 line in FIG.
  • the impurity concentration distribution at the position of the B1-B1 line immediately below the isolation structure IS1 is shown by the B1-B1 line in FIG.
  • the impurity concentration distribution at the position of the line A2-A2 immediately below the main surface of the semiconductor substrate SUB in FIG. 5 showing the region R2 in FIG. 2 in an enlarged manner is indicated by the line A2-A2 in FIG.
  • the impurity concentration distribution at the position of the B2-B2 line immediately under IS1 is shown by the B2-B2 line in FIG.
  • the portion of the n-type impurity along the line A1-A1 Concentration (for example, phosphorus concentration) is 6 times or more higher than the concentration of the lowest concentration portion in the highest concentration portion under the gate electrode layer GE. That is, the n-type impurity concentration changes by 6 times or more under the gate electrode layer GE.
  • the n-type drift region DRI does not cover the inner peripheral side edge IS1I of the element isolation structure IS1, as is apparent from FIG.
  • the change in the n-type impurity concentration (for example, phosphorus concentration) is about twice as high, and the n-type impurity concentration hardly changes under the gate electrode layer GE.
  • n-type impurity concentration for example, phosphorus concentration
  • n-type impurity concentration for example, phosphorus concentration
  • FIGS. 6 and 7 show impurity concentration distributions in the case where the n-type drift region DRI is formed by ion implantation of phosphorus (P) under the condition of a dose amount of 4 ⁇ 10 12 cm ⁇ 2 .
  • FIGS. 8 and 9 show impurity concentration distributions in the case where the n-type drift region DRI is formed by ion implantation of phosphorus (P) under the condition of a dose amount of 8 ⁇ 10 12 cm ⁇ 2 . It can be seen that the change in impurity concentration in FIGS. 8 and 9 shows almost the same tendency as the change in impurity concentration shown in FIGS.
  • the n-type impurity concentration (for example, phosphorus concentration) along the A1-A1 line Changes by one digit or more (10 times or more) under the gate electrode layer GE.
  • the n-type impurity concentration (for example, phosphorus concentration) along the B1-B1 line is also observed. ) Is changed by one digit or more (10 times or more) under the gate electrode layer GE.
  • the n-type drift region DRI shown in FIG. 4 is, for example, 0.1 ⁇ m closer to the n + source region NSR side (left side in the drawing) than the inner peripheral side edge IS1I of the element isolation structure IS1. This is a result when ion implantation is performed in a state where the resist pattern is formed so that the opening end of the register pattern is located at a distant position.
  • the n-type drift region DRI shown in FIG. 5 is, for example, 0.3 ⁇ m closer to the n + drain region NDR side (right side in the figure) than the inner peripheral side edge IS1I of the element isolation structure IS1. This is a result when ion implantation is performed in a state where the resist pattern is formed so that the opening end of the register pattern is located at a distant position.
  • a method for manufacturing the semiconductor device of the present embodiment will be described.
  • a p-type semiconductor substrate SUB is formed with a high breakdown voltage n-type well region NWR and a high breakdown voltage p-type well region PWR having a low impurity concentration.
  • An n-type drift region DRI is formed on the main surface of the semiconductor substrate SUB in the n-type well region NWR, and then element isolation structures IS1 and IS2 are formed on the main surface of the semiconductor substrate SUB.
  • the n-type drift region DRI is formed such that each of the inner peripheral edge DRII and the outer peripheral edge DRIO has a rectangular planar shape, for example.
  • the element isolation structure IS1 is formed such that each of the inner peripheral edge IS1I and the outer peripheral edge IS1O has, for example, the above-described substantially track-shaped planar shape.
  • the element isolation structure IS2 is formed such that the inner peripheral edge IS2I has, for example, a rectangular planar shape.
  • the n-type drift region DRI has an inner peripheral edge DRII located at the outer peripheral side of the inner peripheral edge IS1I of the element isolation structure IS1 in at least a part of both ends in plan view, and the element isolation structure in the center. It is formed so as to be located on the inner peripheral side from the inner peripheral side edge IS1I of IS1.
  • a p-type body region BR serving as a channel is formed, and then a gate insulating layer GI and a gate electrode layer GE are formed.
  • the p-type body region BR is formed on the inner periphery from the inner peripheral edge DRII of the n-type drift region DRI in plan view.
  • the gate electrode layer GE is formed so that the inner peripheral edge GEI has, for example, a rectangular planar shape, and the outer peripheral edge GEO has, for example, the above-described substantially track-shaped planar shape.
  • n-type impurities are ion-implanted into the main surface of the semiconductor substrate SUB to form an n ⁇ region NLD. Thereafter, sidewall insulating layer SW is formed so as to cover the sidewall of gate electrode layer GE.
  • n + drain region NDR and a plurality of n + source regions NSR are formed by ion-implanting n-type impurities into the main surface of the semiconductor substrate SUB using the gate electrode layer GE, the sidewall insulating layer SW, and the like as a mask.
  • the plurality of n + source regions NSR are formed on the inner periphery with respect to the inner peripheral edge GEI of the gate electrode layer GE in plan view.
  • the n + drain region NDR is formed between the element isolation structures IS1 and IS2, and is formed so as to surround the outer periphery of the plurality of n + source regions NSR in plan view.
  • a plurality of p + body contact regions PBC, p + contact regions PSDR, and the like are formed by ion implantation of p-type impurities into the main surface of the semiconductor substrate SUB.
  • the plurality of p + body contact regions PBC are formed on the inner periphery of the inner periphery side edge GEI of the gate electrode layer GE in plan view.
  • Each of the plurality of p + body contact regions PBC is alternately arranged with each of the plurality of n + source regions NSR.
  • nMIS transistor TR is formed on the main surface of the semiconductor substrate SUB.
  • An interlayer insulating layer (not shown) is formed on the main surface of semiconductor substrate SUB so as to cover nMIS transistor TR and the like.
  • Contact holes reaching n + drain region NDR, n + source region NSR, p + body contact region PBC, and gate electrode layer GE are formed in the interlayer insulating layer.
  • Plug layer PL is formed so as to fill the contact hole.
  • a wiring layer ICL is formed on the interlayer insulating layer so as to be in contact with plug layer PL. As described above, the semiconductor device according to the present embodiment is manufactured.
  • the configuration of the comparative example shown in FIGS. 10A, 10B, and 11 is the inner peripheral side edge DRII of the n-type drift region DRI, the element isolation structure IS1.
  • Each of the outer peripheral side edge IS1O and the inner peripheral side edge IS2I of the element isolation structure IS2 has a substantially track shape in which the planar shape is not rectangular, but the middle part (corner part) of both ends is round (arc). Is different in that it has
  • the inner peripheral side edge DRII of the n-type drift region DRI of the comparative example is always located on the inner peripheral side with respect to the inner peripheral side edge IS1I of the element isolation structure IS1.
  • the distance L1 between the outer peripheral side edge BRO of the p-type body region BR in the central part and the inner peripheral side edge DRII of the n-type drift region DRI is equal to the outer peripheral side edge BRO of the p-type body region BR in the intermediate part. It is approximately the same size as the distance L2 from the inner peripheral edge DRII of the type drift region DRI.
  • the distance L3 between the outer peripheral edge BRO of the p-type body region BR and the inner peripheral edge DRII of the n-type drift region DRI at the center of both ends is substantially the same as the distance L1.
  • the width W1 of the element isolation structure IS1 in the central portion is at least a part of both ends in the major axis direction. Is substantially the same as the width W2 of the element isolation structure IS1.
  • the inner peripheral side edge DRII of the n-type drift region DRI in a plan view is more intermediate than the inner peripheral side edge IS1I of the element isolation structure IS1 at the middle part (corner part) of both ends. Is also located on the outer peripheral side.
  • the distance L2 is larger than the distance L1.
  • the depletion layer when a positive voltage is applied to the n + drain region NDR and the depletion layer extends from the pn junction between the central p-type body region BR and the n-type well region NWR to the n-type drift region DRI.
  • the depletion layer In the middle part (corner part), the depletion layer can be extended more widely than the central part.
  • the concentration of the electric field in the depletion layer at the intermediate portion (corner portion) can be suppressed (relieved), and the off breakdown voltage can be improved as compared with the comparative example.
  • the inner peripheral edge DRII of the n-type drift region DRI is located on the inner peripheral side with respect to the inner peripheral edge IS1I of the element isolation structure IS1.
  • the gate insulating layer GI is in contact with the gate insulating layer GI.
  • the inner peripheral edge DRII of the n-type drift region DRI is more outer than the inner peripheral edge IS1I of the element isolation structure IS1. Located on the side. For this reason, the electric field concentration at the inner peripheral side edge IS1I of the element isolation structure IS1 immediately below the gate electrode layer GE in the intermediate portion (corner portion) can be reduced, and the off breakdown voltage can be further improved.
  • the width W2 of the element isolation structure IS1 in the middle part (corner portion) at both ends is larger than the width W1 of the element isolation structure IS1 in the center. For this reason, the electric field due to the drain voltage is sufficiently relaxed in the intermediate portion (corner portion), and the off breakdown voltage is further improved.
  • the inner peripheral edge DRII of the n-type drift region DRI is located on the inner peripheral side with respect to the inner peripheral edge IS1I of the element isolation structure IS1 in the central portion.
  • the distance L1 is smaller than the distance L2. For this reason, the on-resistance can be reduced in the central portion.
  • the comparative example A is an intermediate portion (corner portion) of the inner peripheral side edge DRII of the n-type drift region DRI in the configuration of the present embodiment shown in FIG. 1 (A), FIG. 1 (B) and FIG.
  • it has the structure which became a round shape like the comparative example shown to FIG. 10 (A), FIG. 10 (B), and FIG. Since the structure of the comparative example A other than that is substantially the same as the structure of this Embodiment, the description is not repeated.
  • the n-type well region NWR was formed with a dose of 1.5 ⁇ 10 12 cm ⁇ 2 .
  • the n-type drift region DRI was formed with a dose of 7 ⁇ 10 12 cm ⁇ 2 .
  • the inventor changes the position of the inner peripheral edge DRII of the n-type drift region DRI with respect to the position of the inner peripheral edge IS1I of the element isolation structure IS1 in the configuration as shown in FIG. The off breakdown voltage was measured.
  • FIG. 13 used for the measurement corresponds to the configuration near the region R1 in FIG. Note n in FIG. 13 - region NLD n in FIG. 1 (B) - a region NLD substantially the same region, p + body contact region PBC substantially the p + body contact region PBC in Figure 2 in FIG. 13 In the same area.
  • the n-type well region NWR was formed with a dose of 1.5 ⁇ 10 12 cm ⁇ 2 .
  • the n-type drift region DRI was formed with a dose of 7 ⁇ 10 12 cm ⁇ 2 .
  • the result of measurement using this configuration is shown in FIG.
  • the off breakdown voltage increases as the position of the inner peripheral edge DRII of the n-type drift region DRI is located closer to the n + drain region NDR than the position of the inner peripheral edge IS1I of the element isolation structure IS1. It turns out that it improves. Further, it was found that the off breakdown voltage is improved as the concentrations of both the n-type drift region DRI and the n-type well region NWR are lower.
  • Embodiment 2 Referring to FIGS. 15A, 15B, and 16, the configuration of the present embodiment is compared with the configuration of Embodiment 1 in the plan view in the outer peripheral side edge of gate electrode layer GE. The difference is that the GEO has a rectangular shape.
  • the gate electrode layer GE is formed on the element isolation structure IS1 in the center in the width in a plan view in the direction from the inner peripheral edge GEI to the outer peripheral edge GEO of the gate electrode layer GE with the above configuration.
  • the length G2 over which the gate electrode layer GE rides on the element isolation structure IS1 is larger at least at a part (intermediate portion (corner portion)) of both end portions in the major axis direction than the length G1 that rides on the element isolation structure IS1.
  • the gate electrode layer GE is placed on the element isolation structure IS1 in the middle portion (corner portion) at both ends rather than the length G1 where the gate electrode layer GE rides on the element isolation structure IS1 in the center.
  • the ride length G2 is larger. For this reason, the depletion layer due to the gate electric field is easily extended by the RESURF effect in the intermediate portion (corner portion). Therefore, by optimizing this length G2, the off breakdown voltage can be further improved as compared with the first embodiment.
  • the configuration of the present embodiment is the inner peripheral side of n-type drift region DRI in plan view as compared with the configuration of the first embodiment. The difference is that the end edge DRII is located at the outer peripheral side of the inner peripheral side edge IS1I of the element isolation structure IS1 at the center of both ends.
  • the distance L3 between the outer peripheral side edge BRO of the p-type body region BR and the inner peripheral side edge DRII of the n-type drift region DRI at the central part of both ends is set to be p at the central part. It is larger than the distance L1 between the outer peripheral side edge BRO of the type body region BR and the inner peripheral side edge DRII of the n-type drift region DRI.
  • the inner peripheral side edge IS1I of the element isolation structure IS1 is also covered with the n-type drift region DRI in the central portion of both end portions as in the intermediate portion (corner portion) shown in FIG. First, it is in contact with the n-type well region NWR.
  • the inner peripheral edge DRII of the n-type drift region DRI is not only the intermediate portion (corner portion) at both ends but also the central portion (straight portion), and the inner peripheral end of the element isolation structure IS1. It is located on the outer peripheral side with respect to the edge IS1I. For this reason, it is possible to suppress a decrease in off breakdown voltage due to electric field concentration even at the central portion.
  • the planar shape of the inner peripheral edge IS1I of the element isolation structure IS1 is a substantially track in which the central portion and the central portion of both end portions are linear, and the intermediate portion is round.
  • the case of the shape has been described.
  • the planar shape of the inner peripheral edge IS1I of the element isolation structure IS1 may have a planar shape that extends longer in the major axis direction than in the minor axis direction in the major axis direction and the minor axis direction orthogonal to each other in plan view. That's fine.
  • the planar shape of the inner peripheral side edge IS1I of the element isolation structure IS1 may be, for example, a track shape in which the central portion has a linear shape and both end portions have semicircular shapes, Moreover, an elliptical shape may be sufficient. In the case of an ellipse, the center between the two focal points of the ellipse corresponds to the central part, and the outer side in the major axis direction corresponds to the end part.
  • outer peripheral edge BRO of the p-type body region BR of the first to third embodiments, the outer peripheral edge GEO of the gate electrode layer GE of the first embodiment, and the outer peripheral edge of the element isolation structure IS1 of the second embodiment are not limited to the substantially round shape described above.
  • Each of the outer peripheral side edges BRO, GEO, IS1O and the inner peripheral side edge IS2I has a planar shape extending longer in the major axis direction than in the minor axis direction in the major axis direction and the minor axis direction orthogonal to each other in plan view. For example, a track shape, an ellipse shape, etc. may be sufficient.
  • the planar shape of the inner peripheral edge DRII of the n-type drift region DRI is rectangular.
  • the planar shape of the inner peripheral edge DRII of the n-type drift region DRI is located on the outer peripheral side with respect to the inner peripheral edge IS1I of the element isolation structure IS1 in at least a part of both ends in the major axis direction. Any shape may be employed as long as the shape is located on the inner peripheral side with respect to the inner peripheral side edge IS1I of the element isolation structure IS1 in the central portion in the major axis direction sandwiched between both ends.
  • the rectangular shape includes those in which the corners of the rectangle are rounded when viewed microscopically.
  • silicide may not be formed on the surfaces of n + drain region NDR, n + source region NSR, p + body contact region PBC, and gate electrode layer GE. Further, the n + source region NSR and the n ⁇ region NLD beside the body contact region PBC may be omitted.
  • the transistor may be a MOS transistor in which the gate insulating layer GI is made of a silicon oxide film.
  • the present invention can be applied particularly advantageously to a semiconductor device having a lateral structure transistor.
  • BR p-type body region BRO, DRIO, GEO, IS1O outer peripheral side edge, DRI n-type drift region, DRII, GEI, IS1I, IS2I inner peripheral side edge, GE gate electrode layer, GI gate insulating layer, ICL wiring layer , IL insulating layer, IS1, IS2 element isolation structure, LNW n-type region, NDR n + drain region, NLD n ⁇ region, PR p ⁇ region, NSR n + source region, NWR n-type well region, PBC body contact region, PL plug layer, PSDR contact region, PWR p-type well region, SC silicide layer, SUB semiconductor substrate, SW sidewall insulating layer, TR MIS transistor, TRE trench.

Abstract

On a main surface of a semiconductor substrate (SUB), an n+ drain region (NDR) surrounds an n+ source region (NSR). An inner circumferential side end edge (DRII) of an n-type drift region (DRI) and an inner circumferential side end edge (IS1I) of an element isolation structure (IS1) each have a flat plane shape which is extended in a long axis direction as compared to a short axis direction, the long axis direction and the short axis direction being perpendicular to each other in a plan view. In the plan view, the inner circumferential side end edge (DRII) of the n-type drift region (DRI) is disposed on an outer circumferential side from the inner circumferential side end edge (IS1I) of the element isolation structure (IS1) in at least a part of both end portions in the long axis direction and is disposed on an inner circumferential side from the inner circumferential side end edge (IS1I) of the element isolation structure (IS1) in a center portion in the long axis direction which is sandwiched between the both end portions. With this structure, it is possible to improve an off-state breakdown voltage while reducing an on resistance.

Description

半導体装置Semiconductor device
　本発明は、半導体装置に関し、特に、ラテラル構造のトランジスタを有する半導体装置に関するものである。 The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a lateral structure transistor.
　横方向に電流を流す、いわゆるラテラル構造のＭＩＳ（Metal　Insulator　Semiconductor）トランジスタには、半導体基板の主表面においてソース領域をドレイン領域により取り囲む構造がある。このような構造は、たとえば特開平１０－５０９８５号公報（特許文献１）、特開２００７－９６１４３号公報（特許文献２）、特開２００８－４６００号公報（特許文献３）などに開示されている。 A so-called lateral structure MIS (Metal Insulator Semiconductor) transistor in which a current flows in a lateral direction has a structure in which a source region is surrounded by a drain region on the main surface of a semiconductor substrate. Such a structure is disclosed in, for example, Japanese Patent Application Laid-Open No. 10-50985 (Patent Document 1), Japanese Patent Application Laid-Open No. 2007-96143 (Patent Document 2), Japanese Patent Application Laid-Open No. 2008-4600 (Patent Document 3), and the like. Yes.
　また特開２０１０－２０６１６３号公報（特許文献４）には、ドレイン領域に接続される金属配線をドレイン端の分離オフセット領域上にオーバーラップさせ、この金属配線の電界でドレイン端の電界集中を緩和（ＲＥＳＵＲＦ（REduced　SURface　Field）効果）してオフ耐圧を向上させることが記載されている。 Japanese Patent Laid-Open No. 2010-206163 (Patent Document 4) describes a technique in which a metal wiring connected to a drain region is overlapped with an isolation region at a drain end, and the electric field concentration at the drain end is reduced by the electric field of the metal wiring. (RESURF (REduced SURface Field) effect) is described to improve the off breakdown voltage.
特開平１０－５０９８５号公報Japanese Patent Laid-Open No. 10-50985 特開２００７－９６１４３号公報JP 2007-96143 A 特開２００８－４６００号公報Japanese Patent Laid-Open No. 2008-4600 特開２０１０－２０６１６３号公報JP 2010-206163 A
　上記の特開平１０－５０９８５号公報、特開２００７－９６１４３号公報、特開２００８－４６００号公報に記載されたトランジスタ構造では、平面視におけるソース領域のコーナー部（エッジ部）で電界集中が生じやすく、耐圧が低下するという問題がある。 In the transistor structures described in JP-A-10-50985, JP-A-2007-96143, and JP-A-2008-4600, electric field concentration occurs at the corner (edge) of the source region in plan view. There is a problem that the breakdown voltage is easily reduced.
　本発明は、上記の課題を鑑みてなされたものであり、その目的は、耐圧を向上できる半導体装置を提供することである。 The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of improving the breakdown voltage.
　本発明の一実施例の半導体装置は、半導体基板と、第１導電型のソース領域と、第２導電型のボディ領域と、素子分離構造と、第１導電型のドリフト領域と、ゲート電極層とを備えている。半導体基板は主表面を有している。ソース領域は、その主表面に配置されている。ボディ領域は、平面視においてソース領域の周囲を取り囲むように半導体基板内に配置されている。素子分離構造は、平面視においてボディ領域と間隔をあけてボディ領域の周囲を取り囲むように配置されている。ドリフト領域は、平面視においてボディ領域と間隔をあけてボディ領域の周囲を取り囲むように、かつ素子分離構造の下面に接するように半導体基板内に配置されている。ゲート電極層は、平面視においてソース領域の周囲を取り囲み、かつボディ領域上および素子分離構造上に配置されている。ドリフト領域の内周側端縁および素子分離構造の内周側端縁の各々は、平面視にて互いに直交する長軸方向と短軸方向とにおいて短軸方向よりも長軸方向に長く延びる平面形状を有している。平面視においてドリフト領域の内周側端縁は、長軸方向の両端部の少なくとも一部で素子分離構造の内周側端縁よりも外周側に位置し、かつ両端部に挟まれる長軸方向の中央部で素子分離構造の内周側端縁よりも内周側に位置している。 A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate, a first conductivity type source region, a second conductivity type body region, an element isolation structure, a first conductivity type drift region, and a gate electrode layer. And. The semiconductor substrate has a main surface. The source region is disposed on the main surface thereof. The body region is arranged in the semiconductor substrate so as to surround the periphery of the source region in plan view. The element isolation structure is disposed so as to surround the body region with a space from the body region in plan view. The drift region is disposed in the semiconductor substrate so as to surround the body region with a space from the body region in plan view and to contact the lower surface of the element isolation structure. The gate electrode layer surrounds the periphery of the source region in plan view, and is disposed on the body region and the element isolation structure. Each of the inner peripheral side edge of the drift region and the inner peripheral side edge of the element isolation structure is a plane extending in the major axis direction longer than the minor axis direction in the major axis direction and the minor axis direction orthogonal to each other in plan view. It has a shape. In plan view, the inner peripheral edge of the drift region is positioned at the outer peripheral side of the inner peripheral edge of the element isolation structure at least at a part of both ends in the long axis direction, and the long axis is sandwiched between the both ends Is located on the inner peripheral side with respect to the inner peripheral side edge of the element isolation structure.
　本発明の一実施例の半導体装置によれば、平面視においてドリフト領域の内周側端縁は、長軸方向の両端部の少なくとも一部で素子分離構造の内周側端縁よりも外周側に位置している。このため、両端部の少なくとも一部で耐圧を向上することができる。また本発明の一実施例の半導体装置によれば、平面視においてドリフト領域の内周側端縁が、両端部に挟まれる長軸方向の中央部で素子分離構造の内周側端縁よりも内周側に位置している。このため、中央部にてオン抵抗を低減することができる。 According to the semiconductor device of one embodiment of the present invention, the inner peripheral side edge of the drift region in the plan view is at the outer peripheral side of the inner peripheral side edge of the element isolation structure in at least a part of both ends in the major axis direction Is located. For this reason, the breakdown voltage can be improved at least at a part of both ends. Further, according to the semiconductor device of one embodiment of the present invention, the inner peripheral side edge of the drift region in a plan view is larger than the inner peripheral side edge of the element isolation structure at the central portion in the major axis direction sandwiched between both end portions. Located on the inner circumference. For this reason, the on-resistance can be reduced at the center.
（Ａ）は本発明の実施の形態１における半導体装置の構成を概略的に示す平面図であり、（Ｂ）は図１（Ａ）のＩＢ－ＩＢ線に沿う概略断面図である。(A) is a plan view schematically showing the configuration of the semiconductor device according to the first embodiment of the present invention, and (B) is a schematic cross-sectional view taken along line IB-IB in FIG. 1 (A). 図１（Ａ）のＩＩ－ＩＩ線に沿う概略断面図である。FIG. 2 is a schematic cross-sectional view taken along the line II-II in FIG. エッジ部の説明をするための概略平面図である。It is a schematic plan view for demonstrating an edge part. 図１（Ｂ）の領域Ｒ１の一部を省略して示す拡大断面図である。It is an expanded sectional view which abbreviate | omits and shows a part of area | region R1 of FIG. 1 (B). 図２の領域Ｒ２の一部を省略して示す拡大断面図である。FIG. 3 is an enlarged cross-sectional view in which a part of a region R2 in FIG. 2 is omitted. ドリフト領域の燐イオン注入条件をドーズ量４×１０12ｃｍ-2としたときの、図４のＡ１－Ａ１線に沿う部分の不純物濃度分布および図５のＡ２－Ａ２線に沿う部分の不純物濃度分布を示す図である。Impurity concentration distribution along the line A1-A1 in FIG. 4 and impurity concentration along the line A2-A2 in FIG. 5 when the phosphorus ion implantation condition in the drift region is a dose of 4 × 10 12 cm −2 . It is a figure which shows distribution. ドリフト領域の燐イオン注入条件をドーズ量４×１０12ｃｍ-2としたときの、図４のＢ１－Ｂ１線に沿う部分の不純物濃度分布および図５のＢ２－Ｂ２線に沿う部分の不純物濃度分布を示す図である。Impurity concentration distribution along the line B1-B1 in FIG. 4 and impurity concentration along the line B2-B2 in FIG. 5 when the phosphorus ion implantation condition in the drift region is a dose of 4 × 10 12 cm −2 . It is a figure which shows distribution. ドリフト領域の燐イオン注入条件をドーズ量８×１０12ｃｍ-2としたときの、図４のＡ１－Ａ１線に沿う部分の不純物濃度分布および図５のＡ２－Ａ２線に沿う部分の不純物濃度分布を示す図である。Impurity concentration distribution along the line A1-A1 in FIG. 4 and impurity concentration along the line A2-A2 in FIG. 5 when the phosphorus ion implantation condition in the drift region is a dose of 8 × 10 12 cm −2 . It is a figure which shows distribution. ドリフト領域の燐イオン注入条件をドーズ量８×１０12ｃｍ-2としたときの、図４のＢ１－Ｂ１線に沿う部分の不純物濃度分布および図５のＢ２－Ｂ２線に沿う部分の不純物濃度分布を示す図である。Impurity concentration distribution along the line B1-B1 in FIG. 4 and impurity concentration along the line B2-B2 in FIG. 5 when the phosphorus ion implantation condition in the drift region is a dose of 8 × 10 12 cm −2 . It is a figure which shows distribution. （Ａ）は比較例における半導体装置の構成を概略的に示す平面図であり、（Ｂ）は図１０（Ａ）のＸＢ－ＸＢ線に沿う概略断面図である。(A) is a plan view schematically showing a configuration of a semiconductor device in a comparative example, and (B) is a schematic cross-sectional view taken along line XB-XB in FIG. 10 (A). 図１０（Ａ）のＸＩ－ＸＩ線に沿う概略断面図である。FIG. 11 is a schematic sectional view taken along line XI-XI in FIG. 本発明の実施の形態１の構成と比較例Ａの構成との双方でウエルおよびドリフト領域の注入条件を変えたときのオフ耐圧の関係を示す図である。It is a figure which shows the relationship of an off-breakdown voltage when the injection conditions of a well and a drift area | region are changed with both the structure of Embodiment 1 of this invention, and the structure of the comparative example A. ドリフト領域のソース側端縁の位置に対して素子分離構造の内周側端縁の位置を内周側または外周側に変える様子を説明するための概略断面図である。It is a schematic sectional drawing for demonstrating a mode that the position of the inner peripheral side edge of an element isolation structure is changed to an inner peripheral side or an outer peripheral side with respect to the position of the source side edge of a drift region. ドリフト領域のソース側端縁の位置に対する素子分離構造の内周側端縁の位置と、オフ耐圧の関係を示す図である。It is a figure which shows the relationship of the position of the inner peripheral side edge of an element isolation structure with respect to the position of the source side edge of a drift region, and an off-breakdown pressure | voltage. （Ａ）は本発明の実施の形態２における半導体装置の構成を概略的に示す平面図であり、（Ｂ）は図１５（Ａ）のＸＶＢ－ＸＶＢ線に沿う概略断面図である。(A) is a plan view schematically showing the configuration of the semiconductor device according to the second embodiment of the present invention, and (B) is a schematic cross-sectional view taken along line XVB-XVB in FIG. 15 (A). 図１５（Ａ）のＸＶＩ－ＸＶＩ線に沿う概略断面図である。FIG. 16 is a schematic cross-sectional view taken along line XVI-XVI in FIG. （Ａ）は本発明の実施の形態３における半導体装置の構成を概略的に示す平面図であり、（Ｂ）は図１７（Ａ）のＸＶＩＩＢ－ＸＶＩＩＢ線に沿う概略断面図である。(A) is a plan view schematically showing the configuration of the semiconductor device according to the third embodiment of the present invention, and (B) is a schematic cross-sectional view taken along line XVIIB-XVIIB in FIG. 17 (A). 図１７（Ａ）のＸＶＩＩＩ－ＸＶＩＩＩ線に沿う概略断面図である。FIG. 18 is a schematic sectional view taken along the line XVIII-XVIII in FIG.
　以下、本発明の実施の形態について図に基づいて説明する。
　（実施の形態１）
　まず本発明の実施の形態１の構成について図１（Ａ）、図１（Ｂ）および図２を用いて説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
First, the structure of Embodiment 1 of the present invention will be described with reference to FIGS. 1A, 1B, and 2. FIG.
　図１（Ａ）、図１（Ｂ）および図２を参照して、本実施の形態の半導体装置は、高耐圧のＭＩＳトランジスタＴＲを有している。このＭＩＳトランジスタＴＲは、いわゆるラテラル構造を有しており、半導体基板ＳＵＢの主表面に形成されている。 Referring to FIG. 1A, FIG. 1B, and FIG. 2, the semiconductor device of the present embodiment has a high breakdown voltage MIS transistor TR. The MIS transistor TR has a so-called lateral structure and is formed on the main surface of the semiconductor substrate SUB.
　半導体基板ＳＵＢの内部にはｐ-領域ＰＲが形成されている。このｐ-領域ＰＲよりも半導体基板ＳＵＢの主表面側には、ｎ型ウエル領域ＮＷＲとｐ型ウエル領域ＰＷＲとの各々がｐ-領域ＰＲと接するように形成されている。このｎ型ウエル領域ＮＷＲには上記のＭＩＳトランジスタＴＲが形成されている。 A p − region PR is formed inside the semiconductor substrate SUB. The p - on the main surface of the semiconductor substrate SUB than the region PR, each of the n-type well region NWR and p-type well region PWR is the p - formed in contact with the region PR. In the n-type well region NWR, the MIS transistor TR is formed.
　このＭＩＳトランジスタＴＲは、複数のｎ+ソース領域ＮＳＲ（図１（Ｂ））と、複数のｐ+ボディコンタクト領域ＰＢＣ（図２）と、ｎ-領域ＮＬＤと、ｐ型ボディ領域ＢＲと、ｎ+ドレイン領域ＮＤＲと、ｎ型ドリフト領域ＤＲＩと、低濃度ｎ型領域ＬＮＷと、ゲート絶縁層ＧＩと、ゲート電極層ＧＥとを主に有している。 The MIS transistor TR includes a plurality of n + source regions NSR (FIG. 1B), a plurality of p + body contact regions PBC (FIG. 2), an n − region NLD, a p-type body region BR, n A drain region NDR, an n-type drift region DRI, a low-concentration n-type region LNW, a gate insulating layer GI, and a gate electrode layer GE are mainly included.
　半導体基板ＳＵＢの主表面には、複数のｎ+ソース領域ＮＳＲと複数のｐ+ボディコンタクト領域ＰＢＣとが形成されている。半導体基板ＳＵＢの主表面において、ｎ+ソース領域ＮＳＲとｐ+ボディコンタクト領域ＰＢＣとが交互に並ぶように配置されている。ｎ+ソース領域ＮＳＲはｐ+ボディコンタクト領域ＰＢＣよりも半導体基板ＳＵＢの主表面から浅く形成されている。 A plurality of n + source regions NSR and a plurality of p + body contact regions PBC are formed on the main surface of the semiconductor substrate SUB. On the main surface of semiconductor substrate SUB, n + source regions NSR and p + body contact regions PBC are arranged alternately. N + source region NSR is formed shallower than the main surface of semiconductor substrate SUB than p + body contact region PBC.
　ｎ-領域ＮＬＤは半導体基板ＳＵＢの主表面に形成されている。ｎ-領域ＮＬＤは、互いに交互に配置された複数のｎ+ソース領域ＮＳＲと複数のｐ+ボディコンタクト領域ＰＢＣとの配置領域の周囲を半導体基板ＳＵＢの主表面において取り囲んでいる。ｎ+ソース領域ＮＳＲの横側および下側とｐ+ボディコンタクト領域ＰＢＣの横側とはｎ-領域ＮＬＤにより覆われている。ｐ+ボディコンタクト領域ＰＢＣの下側はｎ-領域ＮＬＤよりも深く形成されてｐ型ボディ領域ＢＲに接している。 The n − region NLD is formed on the main surface of the semiconductor substrate SUB. N − region NLD surrounds the main surface of semiconductor substrate SUB around the arrangement region of a plurality of n + source regions NSR and a plurality of p + body contact regions PBC arranged alternately. The lateral side and lower side of n + source region NSR and the lateral side of p + body contact region PBC are covered with n − region NLD. The lower side of p + body contact region PBC is formed deeper than n − region NLD and is in contact with p type body region BR.
　ｐ型ボディ領域ＢＲは半導体基板ＳＵＢの主表面に形成されている。ｐ型ボディ領域ＢＲは、半導体基板ＳＵＢの主表面において複数のｎ+ソース領域ＮＳＲ、複数のｐ+ボディコンタクト領域ＰＢＣおよびｎ-領域ＮＬＤの周囲を取り囲んでおり、かつｎ型ウエル領域ＮＷＲとｐｎ接合を構成している。 The p-type body region BR is formed on the main surface of the semiconductor substrate SUB. The p-type body region BR surrounds the plurality of n + source regions NSR, the plurality of p + body contact regions PBC and the n − region NLD on the main surface of the semiconductor substrate SUB, and the n-type well regions NWR and pn It constitutes a joint.
　ｎ+ドレイン領域ＮＤＲは、ｐ型ボディ領域ＢＲと間隔をあけて半導体基板ＳＵＢの主表面に形成されている。なお半導体基板ＳＵＢの主表面には素子分離構造ＩＳ１、ＩＳ２が形成されており、ｎ+ドレイン領域ＮＤＲは半導体基板ＳＵＢの主表面において素子分離構造ＩＳ１とＩＳ２との間に挟まれるように形成されている。 N + drain region NDR is formed on the main surface of semiconductor substrate SUB at a distance from p-type body region BR. Element isolation structures IS1 and IS2 are formed on the main surface of the semiconductor substrate SUB, and the n + drain region NDR is formed so as to be sandwiched between the element isolation structures IS1 and IS2 on the main surface of the semiconductor substrate SUB. ing.
　この素子分離構造ＩＳ１、ＩＳ２の各々は、たとえばＳＴＩ（Shallow　Trench　Isolation）、ＬＯＣＯＳ（LOCal　Oxidation　of　Silicon）などよりなっている。素子分離構造ＩＳ１、ＩＳ２の各々がＳＴＩよりなる場合には、素子分離構造ＩＳ１、ＩＳ２の各々は、半導体基板ＳＵＢの主表面に形成された溝ＴＲＥと、その溝ＴＲＥ内を埋め込む絶縁層ＩＬとを有している。 Each of the element isolation structures IS1 and IS2 includes, for example, STI (Shallow Trench Isolation), LOCOS (LOCal Oxidation of Silicon), and the like. When each of the element isolation structures IS1 and IS2 is made of STI, each of the element isolation structures IS1 and IS2 includes a trench TRE formed in the main surface of the semiconductor substrate SUB, and an insulating layer IL filling the trench TRE. have.
　ｎ+ドレイン領域ＮＤＲの下側に接するようにｎ-領域ＮＬＤが形成されている。低濃度ｎ型領域ＬＮＷは、ｎ+ドレイン領域ＮＤＲ下のｎ-領域ＮＬＤの下面および素子分離構造ＩＳ１とＩＳ２のそれぞれの下面に接するように半導体基板ＳＵＢ内に形成されている。 N − region NLD is formed in contact with the lower side of n + drain region NDR. The low concentration n-type region LNW is formed in the semiconductor substrate SUB so as to be in contact with the lower surface of the n − region NLD under the n + drain region NDR and the lower surfaces of the element isolation structures IS1 and IS2.
　ｎ型ドリフト領域ＤＲＩは、低濃度ｎ型領域ＬＮＷおよび素子分離構造ＩＳ１とＩＳ２のそれぞれの下面に接するように半導体基板ＳＵＢ内に形成されている。このｎ型ドリフト領域ＤＲＩとｐ型ボディ領域ＢＲとの間の半導体基板ＳＵＢの主表面にはｎ型ウエル領域ＮＷＲが位置している。ｎ型ドリフト領域ＤＲＩは、ｎ+ドレイン領域ＮＤＲよりも低いｎ型不純物濃度を有し、かつｎ型ウエル領域ＮＷＲよりも高いｎ型不純物濃度を有している。また低濃度ｎ型領域ＬＮＷはｎ型ドリフト領域ＤＲＩよりも高いｎ型不純物濃度を有している。また、ｎ-領域ＮＬＤは、低濃度ｎ型領域ＬＮＷよりも高いｎ型不純物濃度を有し、かつｎ+ドレイン領域ＮＤＲよりも低いｎ型不純物濃度を有している。 The n-type drift region DRI is formed in the semiconductor substrate SUB so as to contact the lower surfaces of the low-concentration n-type region LNW and the element isolation structures IS1 and IS2. An n-type well region NWR is located on the main surface of the semiconductor substrate SUB between the n-type drift region DRI and the p-type body region BR. N-type drift region DRI has an n-type impurity concentration lower than that of n + drain region NDR and an n-type impurity concentration higher than that of n-type well region NWR. The low concentration n-type region LNW has a higher n-type impurity concentration than the n-type drift region DRI. The n − region NLD has a higher n-type impurity concentration than the low-concentration n-type region LNW and a lower n-type impurity concentration than the n + drain region NDR.
　ゲート電極層ＧＥは、ｐ型ボディ領域ＢＲ、ｎ型ドリフト領域ＤＲＩおよびｎ型ウエル領域ＮＷＲの上にゲート絶縁層ＧＩを介在して形成されている。このゲート電極層ＧＥの外周側端縁ＧＥＯは素子分離構造ＩＳ１上に乗り上げており、これによりゲート電極層ＧＥは素子分離構造ＩＳ１を挟んでｎ型ドリフト領域ＤＲＩと対向している。 The gate electrode layer GE is formed on the p-type body region BR, the n-type drift region DRI, and the n-type well region NWR with a gate insulating layer GI interposed therebetween. The outer peripheral edge GEO of the gate electrode layer GE rides on the element isolation structure IS1, so that the gate electrode layer GE faces the n-type drift region DRI across the element isolation structure IS1.
　ゲート電極層ＧＥの側面を覆うように側壁絶縁層ＳＷが形成されている。ゲート電極層ＧＥの内周側端縁ＧＥＩに接する側壁絶縁層ＳＷの下の半導体基板ＳＵＢの主表面およびｎ+ドレイン領域ＮＤＲ部には、上述したｎ-領域ＮＬＤが位置している。 Sidewall insulating layer SW is formed so as to cover the side surface of gate electrode layer GE. The n − region NLD described above is located on the main surface of the semiconductor substrate SUB under the side wall insulating layer SW in contact with the inner peripheral edge GEI of the gate electrode layer GE and the n + drain region NDR.
　シリサイド層ＳＣは、ｎ+ドレイン領域ＮＤＲ、ｎ+ソース領域ＮＳＲ、ｐ+ボディコンタクト領域ＰＢＣおよびゲート電極層ＧＥの各々の表面上に形成されている。 Silicide layer SC is formed on the surfaces of n + drain region NDR, n + source region NSR, p + body contact region PBC, and gate electrode layer GE.
　ｎ+ドレイン領域ＮＤＲには、導電性のプラグ層ＰＬを介在して配線層ＩＣＬが電気的に接続されている。複数のｎ+ソース領域ＮＳＲの各々、および複数のｐ+ボディコンタクト領域ＰＢＣの各々にも、導電性のプラグ層ＰＬを介在して配線層ＩＣＬが電気的に接続されている。またゲート電極層ＧＥにも、導電性のプラグ層ＰＬを介在して配線層（図示せず）が電気的に接続されている。 Wiring layer ICL is electrically connected to n + drain region NDR with conductive plug layer PL interposed. Wiring layer ICL is electrically connected to each of a plurality of n + source regions NSR and each of a plurality of p + body contact regions PBC with conductive plug layer PL interposed therebetween. A wiring layer (not shown) is also electrically connected to the gate electrode layer GE via a conductive plug layer PL.
　ｎ型ドリフト領域ＤＲＩおよびｎ型ウエル領域ＮＷＲの側部と接するように、かつ素子分離構造ＩＳ２の下面に接するように半導体基板ＳＵＢ内にはｐ型ウエル領域ＰＷＲが形成されている。このｐ型ウエル領域ＰＷＲ内の半導体基板ＳＵＢの主表面には、ｐ+コンタクト領域ＰＳＤＲが形成されている。 A p-type well region PWR is formed in the semiconductor substrate SUB so as to be in contact with the side portions of the n-type drift region DRI and the n-type well region NWR and in contact with the lower surface of the element isolation structure IS2. A p + contact region PSDR is formed on the main surface of the semiconductor substrate SUB in the p-type well region PWR.
　主に図１（Ａ）を参照して、平面視において長軸方向（図中上下方向）に沿ってｎ+ソース領域ＮＳＲとｐ+ボディコンタクト領域ＰＢＣとが交互に並ぶように配置されている。平面視においてｐ型ボディ領域ＢＲは、複数のｎ+ソース領域ＮＳＲおよび複数のｐ+ボディコンタクト領域ＰＢＣの周囲をｎ-領域ＮＬＤを介在して取り囲んでいる。 Referring mainly to FIG. 1A, n + source regions NSR and p + body contact regions PBC are alternately arranged along the major axis direction (vertical direction in the drawing) in plan view. . In plan view, p type body region BR surrounds a plurality of n + source regions NSR and a plurality of p + body contact regions PBC with n − region NLD interposed therebetween.
　平面視において素子分離構造ＩＳ１は、ｐ型ボディ領域ＢＲの外周側端縁ＢＲＯと間隔をあけて取り囲んでいる。また平面視においてｎ型ドリフト領域ＤＲＩは、ｐ型ボディ領域ＢＲの外周側端縁ＢＲＯをｎ型ウエル領域ＮＷＲを介在して取り囲んでいる。また平面視においてｎ+ドレイン領域ＮＤＲは、複数のｎ+ソース領域ＮＳＲの外周をｐ型ボディ領域ＢＲ、素子分離構造ＩＳ１などを介在して取り囲んでいる。また平面視において素子分離構造ＩＳ２は、ｎ+ドレイン領域ＮＤＲの外周を取り囲んでいる。 In a plan view, the element isolation structure IS1 surrounds the outer peripheral side edge BRO of the p-type body region BR with a space therebetween. In plan view, n type drift region DRI surrounds outer peripheral side edge BRO of p type body region BR with n type well region NWR interposed. In plan view, n + drain region NDR surrounds the periphery of a plurality of n + source regions NSR with p-type body region BR, element isolation structure IS1 and the like interposed therebetween. In plan view, element isolation structure IS2 surrounds the outer periphery of n + drain region NDR.
　ｐ型ボディ領域ＢＲの外周側端縁ＢＲＯと、ｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩと、素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉおよび外周側端縁ＩＳ１Ｏと、ゲート電極層ＧＥの内周側端縁ＧＥＩおよび外周側端縁ＧＥＯとの各々は、平面視にて互いに直交する長軸方向と短軸方向（図中左右方向）とにおいて短軸方向よりも長軸方向に長く延びる平面形状を有している。 The outer peripheral edge BRO of the p-type body region BR, the inner peripheral edge DRII of the n-type drift region DRI, the inner peripheral edge IS1I and the outer peripheral edge IS1O of the element isolation structure IS1, and the gate electrode layer GE Each of the inner circumferential edge GEI and the outer circumferential edge GEO is longer in the major axis direction than the minor axis direction in the major axis direction and the minor axis direction (left and right direction in the figure) orthogonal to each other in plan view. It has a planar shape that extends.
　ゲート電極層ＧＥの内周側端縁ＧＥＩ、ｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩ、外周側端縁ＤＲＩＯ、素子分離構造ＩＳ１の外周側端縁ＩＳ１Ｏ、および素子分離構造ＩＳ２の内周側端縁ＩＳ２Ｉの各々は、長軸方向に長く、短軸方向の短い長方形状の平面形状を有している。 The inner peripheral edge GEI of the gate electrode layer GE, the inner peripheral edge DRII of the n-type drift region DRI, the outer peripheral edge DRIO, the outer peripheral edge IS1O of the element isolation structure IS1, and the inner periphery of the element isolation structure IS2 Each of the side edges IS2I has a rectangular planar shape that is long in the long axis direction and short in the short axis direction.
　ｐ型ボディ領域ＢＲの外周側端縁ＢＲＯ、素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉおよびゲート電極層ＧＥの外周側端縁ＧＥＯの各々は、中央部と両端部の中央箇所との各々が直線形状よりなり、かつ両端部の中間部分（コーナー部）がラウンド形状よりなる略トラック形状の平面形状を有している。この中間部分におけるラウンド形状は、ゲート電極層ＧＥの長方形の平面形状の角部を中心とする円弧（４分の１円）をなしている。この略トラック形状とは、言い換えると、長方形の角部となるべき部分がラウンド形状（円弧）となった形状である。まお両端部は長軸方向の端となる中央箇所と、その中央箇所および中間部の間に位置する中間部分（コーナー部）とを有している。 Each of the outer peripheral side edge BRO of the p-type body region BR, the inner peripheral side edge IS1I of the element isolation structure IS1, and the outer peripheral side edge GEO of the gate electrode layer GE has a central portion and central portions of both end portions. It has a substantially track-shaped planar shape that is formed in a straight line shape and that has an intermediate portion (corner portion) at both ends in a round shape. The round shape in the intermediate portion is an arc (quarter circle) centering on the corner of the rectangular planar shape of the gate electrode layer GE. In other words, the substantially track shape is a shape in which a portion to be a rectangular corner is a round shape (arc). The both ends have a central portion serving as an end in the major axis direction and an intermediate portion (corner portion) positioned between the central portion and the intermediate portion.
　平面視においてｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩは、長軸方向の両端部の少なくとも一部（中間部分（コーナー部））で素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉよりも外周側に位置している。また平面視においてｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩは、両端部に挟まれる長軸方向の中央部と両端部の中央箇所とにおいて素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉよりも内周側に位置している。つまり、ｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩの長方形の平面形状の角部が、素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉのラウンド形状（円弧）の中間部分の一部より外周側に位置している。 In plan view, the inner peripheral edge DRII of the n-type drift region DRI is at least a part (intermediate portion (corner portion)) of both ends in the major axis direction and is more outer than the inner peripheral edge IS1I of the element isolation structure IS1. Located on the side. Further, the inner peripheral edge DRII of the n-type drift region DRI in plan view is more than the inner peripheral edge IS1I of the element isolation structure IS1 at the central portion in the major axis direction sandwiched between both ends and the central portion of both ends. Located on the inner circumference. That is, the rectangular planar corner portion of the inner peripheral edge DRII of the n-type drift region DRI is on the outer peripheral side than a part of the intermediate portion of the round shape (arc) of the inner peripheral edge IS1I of the element isolation structure IS1. Is located.
　これにより、中央部におけるｐ型ボディ領域ＢＲの外周側端縁ＢＲＯとｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩとの距離Ｌ１よりも、中間部分（コーナー部）におけるｐ型ボディ領域ＢＲの外周側端縁ＢＲＯとｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩとの距離Ｌ２の方が大きくなる。また両端部の中央箇所におけるｐ型ボディ領域ＢＲの外周側端縁ＢＲＯとｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩとの距離Ｌ３は、上記の距離Ｌ１とほぼ同じ大きさである。 As a result, the distance between the outer peripheral side edge BRO of the p-type body region BR in the central part and the inner peripheral side edge DRII of the n-type drift region DRI is larger than that of the p-type body region BR in the intermediate part (corner part). The distance L2 between the outer peripheral edge BRO and the inner peripheral edge DRII of the n-type drift region DRI is larger. Further, the distance L3 between the outer peripheral edge BRO of the p-type body region BR and the inner peripheral edge DRII of the n-type drift region DRI at the center of both ends is substantially the same as the distance L1.
　これにより図１（Ｂ）に示す中央部の断面構造においては、ｎ型ドリフト領域ＤＲＩが素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉを覆っている。また図２に示す両端部の少なくとも一部の断面構造においては、ｎ型ドリフト領域ＤＲＩが素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉを覆っておらず、素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉはｎ型ウエル領域ＮＷＲと接している。 Thus, in the central cross-sectional structure shown in FIG. 1B, the n-type drift region DRI covers the inner peripheral edge IS1I of the element isolation structure IS1. In the cross-sectional structure of at least a part of both ends shown in FIG. 2, the n-type drift region DRI does not cover the inner peripheral edge IS1I of the element isolation structure IS1, and the inner peripheral edge of the element isolation structure IS1. IS1I is in contact with the n-type well region NWR.
　また図１（Ａ）を参照して、素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉと外周側端縁ＩＳ１Ｏとの間の平面視における幅において、中央部における素子分離構造ＩＳ１の幅Ｗ１よりも長軸方向の両端部の少なくとも一部（中間部分（コーナー部））における素子分離構造ＩＳ１の幅Ｗ２の方が大きい。 1A, the width in plan view between the inner peripheral edge IS1I and the outer peripheral edge IS1O of the element isolation structure IS1 is larger than the width W1 of the element isolation structure IS1 in the center. The width W2 of the element isolation structure IS1 is larger in at least a part (intermediate portion (corner portion)) of both end portions in the long axis direction.
　またゲート電極層ＧＥの内周側端縁ＧＥＩから外周側端縁ＧＥＯへ向かう方向の平面視における幅において、中央部においてゲート電極層ＧＥが素子分離構造ＩＳ１上に乗り上げる長さＧ１は、長軸方向の両端部の少なくとも一部においてゲート電極層ＧＥが素子分離構造ＩＳ１上に乗り上げる長さＧ２と実質的に同じである。 The length G1 of the gate electrode layer GE riding on the element isolation structure IS1 in the center in the width in a plan view in the direction from the inner peripheral edge GEI to the outer peripheral edge GEO of the gate electrode layer GE is a long axis. The length G2 is substantially the same as the length G2 over which the gate electrode layer GE rides on the element isolation structure IS1 in at least a part of both ends in the direction.
　なお本明細書における平面視とは図１（Ａ）などにおける平面図において見た様子を意味しており、半導体基板ＳＵＢの主表面に対して垂直な方向から見た様子を意味する。また本明細書における平面形状とは、図１（Ａ）などにおける平面図において見た形状を意味しており、半導体基板ＳＵＢの主表面に対して垂直な方向から見た形状を意味する。 Note that the plan view in this specification means a state seen in a plan view in FIG. 1A and the like, and means a state seen from a direction perpendicular to the main surface of the semiconductor substrate SUB. In addition, the planar shape in this specification means a shape seen in a plan view in FIG. 1A and the like, and means a shape seen from a direction perpendicular to the main surface of the semiconductor substrate SUB.
　なお、上記における中間部（コーナー部）の長さＧ２は以下のように規定される。
　図３を参照して、素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉの中間部の円弧の接線Ｄ１－Ｄ１に対する垂線（Ｅ１－Ｅ１線）に沿う、素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉとゲート電極層ＧＥの外周側端縁ＧＥＯとの間の距離が長さＧ２とされる。幅Ｗ２および距離Ｌ２も長さＧ２と同様に規定される。 The length G2 of the intermediate part (corner part) in the above is defined as follows.
Referring to FIG. 3, inner edge IS1I of element isolation structure IS1 along a perpendicular line (E1-E1 line) with respect to arc tangent D1-D1 in the middle of inner edge IS1I of element isolation structure IS1. And the distance between the outer peripheral edge GEO of the gate electrode layer GE is the length G2. The width W2 and the distance L2 are defined similarly to the length G2.
　次に、図１（Ｂ）の断面におけるｎ型ドリフト領域ＤＲＩの不純物濃度分布と図２の断面におけるｎ型ドリフト領域ＤＲＩの不純物濃度分布との相違について図４～図９を用いて説明する。 Next, the difference between the impurity concentration distribution of the n-type drift region DRI in the cross section of FIG. 1B and the impurity concentration distribution of the n-type drift region DRI in the cross section of FIG. 2 will be described with reference to FIGS.
　図１（Ｂ）の領域Ｒ１を拡大して示す図４における半導体基板ＳＵＢの主表面直下のＡ１－Ａ１線の位置における不純物濃度分布は図６のＡ１－Ａ１線で示され、図４における素子分離構造ＩＳ１直下のＢ１－Ｂ１線の位置における不純物濃度分布は図７のＢ１－Ｂ１線で示される。また図２の領域Ｒ２を拡大して示す図５における半導体基板ＳＵＢの主表面直下のＡ２－Ａ２線の位置における不純物濃度分布は図６のＡ２－Ａ２線で示され、図５における素子分離構造ＩＳ１直下のＢ２－Ｂ２線の位置における不純物濃度分布は図７のＢ２－Ｂ２線で示される。 4 is an enlarged view of the region R1 in FIG. 1B. The impurity concentration distribution at the position of the A1-A1 line immediately below the main surface of the semiconductor substrate SUB in FIG. 4 is indicated by the A1-A1 line in FIG. The impurity concentration distribution at the position of the B1-B1 line immediately below the isolation structure IS1 is shown by the B1-B1 line in FIG. Further, the impurity concentration distribution at the position of the line A2-A2 immediately below the main surface of the semiconductor substrate SUB in FIG. 5 showing the region R2 in FIG. 2 in an enlarged manner is indicated by the line A2-A2 in FIG. The impurity concentration distribution at the position of the B2-B2 line immediately under IS1 is shown by the B2-B2 line in FIG.
　図４に示すようにｎ型ドリフト領域ＤＲＩが素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉを覆っている場合には、図６から明らかなように、Ａ１－Ａ１線に沿う部分のｎ型不純物濃度（たとえば燐濃度）はゲート電極層ＧＥの下において、最も濃度の高い部分の濃度が最も濃度の低い部分の濃度の６倍以上になっている。つまりゲート電極層ＧＥの下においてｎ型不純物濃度は６倍以上変化している。これに対して図５に示すようにｎ型ドリフト領域ＤＲＩが素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉを覆っていない場合には、図６から明らかなように、Ａ２－Ａ２線に沿う部分のｎ型不純物濃度（たとえば燐濃度）の変化はせいぜい２倍程度であり、ｎ型不純物濃度はゲート電極層ＧＥの下においてほとんど変化しない。 As shown in FIG. 4, when the n-type drift region DRI covers the inner peripheral edge IS1I of the element isolation structure IS1, as is apparent from FIG. 6, the portion of the n-type impurity along the line A1-A1 Concentration (for example, phosphorus concentration) is 6 times or more higher than the concentration of the lowest concentration portion in the highest concentration portion under the gate electrode layer GE. That is, the n-type impurity concentration changes by 6 times or more under the gate electrode layer GE. On the other hand, as shown in FIG. 5, when the n-type drift region DRI does not cover the inner peripheral side edge IS1I of the element isolation structure IS1, as is apparent from FIG. The change in the n-type impurity concentration (for example, phosphorus concentration) is about twice as high, and the n-type impurity concentration hardly changes under the gate electrode layer GE.
　また図４に示すようにｎ型ドリフト領域ＤＲＩが素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉを覆っている場合には、図７から明らかなように、Ｂ１－Ｂ１線に沿う部分のｎ型不純物濃度（たとえば燐濃度）はゲート電極層ＧＥの下において大きく（６倍以上）変化している。また、素子分離構造ＩＳ１の下の内周側端縁ＩＳ１Ｉ近傍においてはＢ１－Ｂ１線に沿う部分のｎ型不純物濃度（たとえば燐濃度）は、ほとんど変化していない。これに対して図５に示すようにｎ型ドリフト領域ＤＲＩが素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉを覆っていない場合には、図６から明らかなように、Ｂ２－Ｂ２線に沿う部分のｎ型不純物濃度（たとえば燐濃度）の変化はゲート電極層ＧＥの下において２倍程度であり、ｎ型不純物濃度はゲート電極層ＧＥの下においてほとんど変化していない。むしろＢ２－Ｂ２線に沿う部分のｎ型不純物濃度（たとえば燐濃度）は、素子分離構造ＩＳ１の下の内周側端縁ＩＳ１Ｉ近傍において大きく変化している。 Further, as shown in FIG. 4, when the n-type drift region DRI covers the inner peripheral side edge IS1I of the element isolation structure IS1, the n-type portion along the line B1-B1 is clearly seen from FIG. The impurity concentration (for example, phosphorus concentration) changes greatly (six times or more) under the gate electrode layer GE. In the vicinity of the inner peripheral edge IS1I below the element isolation structure IS1, the n-type impurity concentration (for example, phosphorus concentration) in the portion along the B1-B1 line is hardly changed. On the other hand, as shown in FIG. 5, when the n-type drift region DRI does not cover the inner peripheral side edge IS1I of the element isolation structure IS1, as is apparent from FIG. The change in n-type impurity concentration (for example, phosphorus concentration) is about twice under the gate electrode layer GE, and the n-type impurity concentration hardly changes under the gate electrode layer GE. Rather, the n-type impurity concentration (for example, phosphorus concentration) along the B2-B2 line changes greatly in the vicinity of the inner peripheral edge IS1I below the element isolation structure IS1.
　図６および図７は、ドーズ量が４×１０12ｃｍ-2の条件で燐（Ｐ）をイオン注入してｎ型ドリフト領域ＤＲＩを形成した場合の不純物濃度分布を示している。またドーズ量が８×１０12ｃｍ-2の条件で燐（Ｐ）をイオン注入してｎ型ドリフト領域ＤＲＩを形成した場合の不純物濃度分布を図８および図９に示す。図８および図９の不純物濃度の変化は、図６および図７に示す不純物濃度の変化とほぼ同じ傾向を示すことがわかる。 6 and 7 show impurity concentration distributions in the case where the n-type drift region DRI is formed by ion implantation of phosphorus (P) under the condition of a dose amount of 4 × 10 12 cm −2 . Further, FIGS. 8 and 9 show impurity concentration distributions in the case where the n-type drift region DRI is formed by ion implantation of phosphorus (P) under the condition of a dose amount of 8 × 10 12 cm −2 . It can be seen that the change in impurity concentration in FIGS. 8 and 9 shows almost the same tendency as the change in impurity concentration shown in FIGS.
　図８から明らかなように、ｎ型ドリフト領域ＤＲＩが素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉを覆っている場合には、Ａ１－Ａ１線に沿う部分のｎ型不純物濃度（たとえば燐濃度）はゲート電極層ＧＥの下において１桁以上（１０倍以上）変化している。また図９から明らかなように、ｎ型ドリフト領域ＤＲＩが素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉを覆っている場合にも、Ｂ１－Ｂ１線に沿う部分のｎ型不純物濃度（たとえば燐濃度）はゲート電極層ＧＥの下において１桁以上（１０倍以上）変化している。 As is apparent from FIG. 8, when the n-type drift region DRI covers the inner peripheral edge IS1I of the element isolation structure IS1, the n-type impurity concentration (for example, phosphorus concentration) along the A1-A1 line. Changes by one digit or more (10 times or more) under the gate electrode layer GE. As is apparent from FIG. 9, even when the n-type drift region DRI covers the inner peripheral side edge IS1I of the element isolation structure IS1, the n-type impurity concentration (for example, phosphorus concentration) along the B1-B1 line is also observed. ) Is changed by one digit or more (10 times or more) under the gate electrode layer GE.
　なお図６～図９の結果は、図４に示すｎ型ドリフト領域ＤＲＩを、素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉよりもｎ+ソース領域ＮＳＲ側（図中左側）にたとえば０．１μｍ離れた位置にレジスタパターンの開口端が位置するようにレジストパターンを形成した状態でイオン注入を行って形成した場合の結果である。また図６～図９の結果は、図５に示すｎ型ドリフト領域ＤＲＩを、素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉよりもｎ+ドレイン領域ＮＤＲ側（図中右側）にたとえば０．３μｍ離れた位置にレジスタパターンの開口端が位置するようにレジストパターンを形成した状態でイオン注入を行って形成した場合の結果である。 6 to 9, the n-type drift region DRI shown in FIG. 4 is, for example, 0.1 μm closer to the n + source region NSR side (left side in the drawing) than the inner peripheral side edge IS1I of the element isolation structure IS1. This is a result when ion implantation is performed in a state where the resist pattern is formed so that the opening end of the register pattern is located at a distant position. 6 to 9, the n-type drift region DRI shown in FIG. 5 is, for example, 0.3 μm closer to the n + drain region NDR side (right side in the figure) than the inner peripheral side edge IS1I of the element isolation structure IS1. This is a result when ion implantation is performed in a state where the resist pattern is formed so that the opening end of the register pattern is located at a distant position.
　次に、本実施の形態の半導体装置の製造方法について説明する。
　図１（Ｂ）および図２を参照して、ｐ型の半導体基板ＳＵＢに不純物濃度の低い高耐圧ｎ型ウエル領域ＮＷＲと高耐圧ｐ型ウエル領域ＰＷＲとが形成される。このｎ型ウエル領域ＮＷＲ内の半導体基板ＳＵＢの主表面にｎ型ドリフト領域ＤＲＩが形成され、次いで半導体基板ＳＵＢの主表面に素子分離構造ＩＳ１、ＩＳ２が形成される。 Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
Referring to FIGS. 1B and 2, a p-type semiconductor substrate SUB is formed with a high breakdown voltage n-type well region NWR and a high breakdown voltage p-type well region PWR having a low impurity concentration. An n-type drift region DRI is formed on the main surface of the semiconductor substrate SUB in the n-type well region NWR, and then element isolation structures IS1 and IS2 are formed on the main surface of the semiconductor substrate SUB.
　ｎ型ドリフト領域ＤＲＩは、内周側端縁ＤＲＩＩおよび外周側端縁ＤＲＩＯの各々がたとえば長方形の平面形状となるように形成される。また素子分離構造ＩＳ１は、内周側端縁ＩＳ１Ｉおよび外周側端縁ＩＳ１Ｏの各々がたとえば上記の略トラック形状の平面形状となるように形成される。また素子分離構造ＩＳ２は、内周側端縁ＩＳ２Ｉがたとえば長方形の平面形状となるように形成される。 The n-type drift region DRI is formed such that each of the inner peripheral edge DRII and the outer peripheral edge DRIO has a rectangular planar shape, for example. The element isolation structure IS1 is formed such that each of the inner peripheral edge IS1I and the outer peripheral edge IS1O has, for example, the above-described substantially track-shaped planar shape. The element isolation structure IS2 is formed such that the inner peripheral edge IS2I has, for example, a rectangular planar shape.
　またｎ型ドリフト領域ＤＲＩは、平面視において内周側端縁ＤＲＩＩが両端部の少なくとも一部で素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉよりも外周側に位置し、中央部で素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉよりも内周側に位置するように形成される。 In addition, the n-type drift region DRI has an inner peripheral edge DRII located at the outer peripheral side of the inner peripheral edge IS1I of the element isolation structure IS1 in at least a part of both ends in plan view, and the element isolation structure in the center. It is formed so as to be located on the inner peripheral side from the inner peripheral side edge IS1I of IS1.
　その後、チャネルとなるｐ型ボディ領域ＢＲが形成され、次いでゲート絶縁層ＧＩとゲート電極層ＧＥとが形成される。ｐ型ボディ領域ＢＲは、平面視においてｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩよりも内周に形成される。ゲート電極層ＧＥは、内周側端縁ＧＥＩがたとえば長方形の平面形状となるように、かつ外周側端縁ＧＥＯがたとえば上記の略トラック形状の平面形状となるように形成される。 Thereafter, a p-type body region BR serving as a channel is formed, and then a gate insulating layer GI and a gate electrode layer GE are formed. The p-type body region BR is formed on the inner periphery from the inner peripheral edge DRII of the n-type drift region DRI in plan view. The gate electrode layer GE is formed so that the inner peripheral edge GEI has, for example, a rectangular planar shape, and the outer peripheral edge GEO has, for example, the above-described substantially track-shaped planar shape.
　このゲート電極層ＧＥなどをマスクとして半導体基板ＳＵＢの主表面にｎ型不純物をイオン注入などをすることにより、ｎ-領域ＮＬＤが形成される。この後、ゲート電極層ＧＥの側壁を覆うように側壁絶縁層ＳＷが形成される。 By using this gate electrode layer GE or the like as a mask, n-type impurities are ion-implanted into the main surface of the semiconductor substrate SUB to form an n − region NLD. Thereafter, sidewall insulating layer SW is formed so as to cover the sidewall of gate electrode layer GE.
　このゲート電極層ＧＥ、側壁絶縁層ＳＷなどをマスクとして半導体基板ＳＵＢの主表面にｎ型不純物をイオン注入などすることにより、ｎ+ドレイン領域ＮＤＲ、複数のｎ+ソース領域ＮＳＲが形成される。複数のｎ+ソース領域ＮＳＲは、平面視においてゲート電極層ＧＥの内周側端縁ＧＥＩよりも内周に形成される。ｎ+ドレイン領域ＮＤＲは、素子分離構造ＩＳ１とＩＳ２との間に形成され、かつ平面視において複数のｎ+ソース領域ＮＳＲの外周を取り囲むように形成される。 An n + drain region NDR and a plurality of n + source regions NSR are formed by ion-implanting n-type impurities into the main surface of the semiconductor substrate SUB using the gate electrode layer GE, the sidewall insulating layer SW, and the like as a mask. The plurality of n + source regions NSR are formed on the inner periphery with respect to the inner peripheral edge GEI of the gate electrode layer GE in plan view. The n + drain region NDR is formed between the element isolation structures IS1 and IS2, and is formed so as to surround the outer periphery of the plurality of n + source regions NSR in plan view.
　また半導体基板ＳＵＢの主表面にｐ型不純物をイオン注入などすることにより、複数のｐ+ボディコンタクト領域ＰＢＣ、ｐ+コンタクト領域ＰＳＤＲなどが形成される。複数のｐ+ボディコンタクト領域ＰＢＣは、平面視においてゲート電極層ＧＥの内周側端縁ＧＥＩよりも内周に形成される。複数のｐ+ボディコンタクト領域ＰＢＣの各々は、複数のｎ+ソース領域ＮＳＲの各々と交互に配置される。 A plurality of p + body contact regions PBC, p + contact regions PSDR, and the like are formed by ion implantation of p-type impurities into the main surface of the semiconductor substrate SUB. The plurality of p + body contact regions PBC are formed on the inner periphery of the inner periphery side edge GEI of the gate electrode layer GE in plan view. Each of the plurality of p + body contact regions PBC is alternately arranged with each of the plurality of n + source regions NSR.
　このようにして半導体基板ＳＵＢの主表面にラテラル構造の高耐圧ｎＭＩＳトランジスタＴＲが形成される。このｎＭＩＳトランジスタＴＲなどを覆うように半導体基板ＳＵＢの主表面上に層間絶縁層（図示せず）が形成される。この層間絶縁層に、ｎ+ドレイン領域ＮＤＲ、ｎ+ソース領域ＮＳＲ、ｐ+ボディコンタクト領域ＰＢＣ、ゲート電極層ＧＥの各々に達するコンタクトホールが形成される。このコンタクトホール内を埋め込むようにプラグ層ＰＬが形成される。このプラグ層ＰＬに接するように層間絶縁層上に配線層ＩＣＬが形成される。上記のようにして本実施の形態の半導体装置が製造される。 In this manner, a lateral structure high breakdown voltage nMIS transistor TR is formed on the main surface of the semiconductor substrate SUB. An interlayer insulating layer (not shown) is formed on the main surface of semiconductor substrate SUB so as to cover nMIS transistor TR and the like. Contact holes reaching n + drain region NDR, n + source region NSR, p + body contact region PBC, and gate electrode layer GE are formed in the interlayer insulating layer. Plug layer PL is formed so as to fill the contact hole. A wiring layer ICL is formed on the interlayer insulating layer so as to be in contact with plug layer PL. As described above, the semiconductor device according to the present embodiment is manufactured.
　次に、本実施の形態の半導体装置の作用効果について比較例と対比して説明する。
　図１０（Ａ）、図１０（Ｂ）および図１１に示す比較例の構成は、本実施の形態の構成と比較して、ｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩ、素子分離構造ＩＳ１の外周側端縁ＩＳ１Ｏおよび素子分離構造ＩＳ２の内周側端縁ＩＳ２Ｉの各々の平面形状が長方形状ではなく、両端部の中間部分（コーナー部）がラウンド形状（円弧）となった略トラック形状を有する点において異なっている。 Next, the effect of the semiconductor device of this embodiment will be described in comparison with a comparative example.
Compared with the configuration of the present embodiment, the configuration of the comparative example shown in FIGS. 10A, 10B, and 11 is the inner peripheral side edge DRII of the n-type drift region DRI, the element isolation structure IS1. Each of the outer peripheral side edge IS1O and the inner peripheral side edge IS2I of the element isolation structure IS2 has a substantially track shape in which the planar shape is not rectangular, but the middle part (corner part) of both ends is round (arc). Is different in that it has
　このため、平面視において比較例のｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩは素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉよりも常に内周側に位置している。そして中央部におけるｐ型ボディ領域ＢＲの外周側端縁ＢＲＯとｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩとの距離Ｌ１は、中間部分におけるｐ型ボディ領域ＢＲの外周側端縁ＢＲＯとｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩとの距離Ｌ２とほぼ同じ大きさである。また両端部の中央箇所におけるｐ型ボディ領域ＢＲの外周側端縁ＢＲＯとｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩとの距離Ｌ３は、上記の距離Ｌ１とほぼ同じ大きさである。 Therefore, in plan view, the inner peripheral side edge DRII of the n-type drift region DRI of the comparative example is always located on the inner peripheral side with respect to the inner peripheral side edge IS1I of the element isolation structure IS1. The distance L1 between the outer peripheral side edge BRO of the p-type body region BR in the central part and the inner peripheral side edge DRII of the n-type drift region DRI is equal to the outer peripheral side edge BRO of the p-type body region BR in the intermediate part. It is approximately the same size as the distance L2 from the inner peripheral edge DRII of the type drift region DRI. Further, the distance L3 between the outer peripheral edge BRO of the p-type body region BR and the inner peripheral edge DRII of the n-type drift region DRI at the center of both ends is substantially the same as the distance L1.
　また素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉと外周側端縁ＩＳ１Ｏとの間の平面視における幅において、中央部における素子分離構造ＩＳ１の幅Ｗ１は、長軸方向の両端部の少なくとも一部における素子分離構造ＩＳ１の幅Ｗ２とほぼ同じ大きさである。 Further, in the width in plan view between the inner peripheral edge IS1I and the outer peripheral edge IS1O of the element isolation structure IS1, the width W1 of the element isolation structure IS1 in the central portion is at least a part of both ends in the major axis direction. Is substantially the same as the width W2 of the element isolation structure IS1.
　なお比較例の上記以外の構成は本実施の形態の構成とほぼ同じであるため、同一の要素については同一の符号を付し、その説明を繰り返さない。 Since the configuration of the comparative example other than the above is substantially the same as the configuration of the present embodiment, the same elements are denoted by the same reference numerals and description thereof is not repeated.
　この比較例において、オフ時においてｎ+ドレイン領域ＮＤＲに正の電圧が印加される場合、中央のｐ型ボディ領域ＢＲとｎ型ウエル領域ＮＷＲとのｐｎ接合部からドレイン側のｎ型ドリフト領域ＤＲＩへ空乏層が伸びていく。この際、図１０（Ａ）における両端部の中間部分（コーナー部）においては空乏層内で電界が集中し、オフ耐圧が低下する。 In this comparative example, when a positive voltage is applied to the n + drain region NDR at the off time, the drain side n-type drift region DRI from the pn junction between the central p-type body region BR and the n-type well region NWR The depletion layer grows. At this time, an electric field concentrates in the depletion layer in an intermediate portion (corner portion) at both end portions in FIG.
　これに対して本実施の形態においては、平面視においてｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩは、両端部の中間部分（コーナー部）で素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉよりも外周側に位置している。これにより、上記の距離Ｌ１よりも上記の距離Ｌ２の方が大きくなっている。 On the other hand, in the present embodiment, the inner peripheral side edge DRII of the n-type drift region DRI in a plan view is more intermediate than the inner peripheral side edge IS1I of the element isolation structure IS1 at the middle part (corner part) of both ends. Is also located on the outer peripheral side. Thus, the distance L2 is larger than the distance L1.
　このため、ｎ+ドレイン領域ＮＤＲに正の電圧が印加されて、中央のｐ型ボディ領域ＢＲとｎ型ウエル領域ＮＷＲとのｐｎ接合部からｎ型ドリフト領域ＤＲＩへ空乏層が伸びていく際に、中間部分（コーナー部）では中央部よりも空乏層を広く延ばすことができる。これにより、中間部分（コーナー部）の空乏層内で電界が集中することを抑制（緩和）でき、オフ耐圧を比較例よりも向上させることができる。 Therefore, when a positive voltage is applied to the n + drain region NDR and the depletion layer extends from the pn junction between the central p-type body region BR and the n-type well region NWR to the n-type drift region DRI. In the middle part (corner part), the depletion layer can be extended more widely than the central part. As a result, the concentration of the electric field in the depletion layer at the intermediate portion (corner portion) can be suppressed (relieved), and the off breakdown voltage can be improved as compared with the comparative example.
　また本実施の形態の図１（Ｂ）に示す中央部ではｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩが素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉよりも内周側に位置しており、ゲート絶縁層ＧＩと接する構造になっている。これに対して本実施の形態の図２に示す両端部の中間部分（コーナー部）ではｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩが素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉよりも外周側に位置している。このため、中間部分（コーナー部）においてゲート電極層ＧＥの直下における素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉでの電界集中も緩和でき、さらにオフ耐圧を向上させることができる。 Further, in the central portion shown in FIG. 1B of the present embodiment, the inner peripheral edge DRII of the n-type drift region DRI is located on the inner peripheral side with respect to the inner peripheral edge IS1I of the element isolation structure IS1. The gate insulating layer GI is in contact with the gate insulating layer GI. On the other hand, in the intermediate part (corner part) of both ends shown in FIG. 2 of the present embodiment, the inner peripheral edge DRII of the n-type drift region DRI is more outer than the inner peripheral edge IS1I of the element isolation structure IS1. Located on the side. For this reason, the electric field concentration at the inner peripheral side edge IS1I of the element isolation structure IS1 immediately below the gate electrode layer GE in the intermediate portion (corner portion) can be reduced, and the off breakdown voltage can be further improved.
　また本実施の形態では、中央部における素子分離構造ＩＳ１の幅Ｗ１よりも両端部の中間部分（コーナー部）における素子分離構造ＩＳ１の幅Ｗ２の方が大きい。このため、中間部分（コーナー部）においてドレイン電圧による電界が十分に緩和され、オフ耐圧がさらに向上する。 In the present embodiment, the width W2 of the element isolation structure IS1 in the middle part (corner portion) at both ends is larger than the width W1 of the element isolation structure IS1 in the center. For this reason, the electric field due to the drain voltage is sufficiently relaxed in the intermediate portion (corner portion), and the off breakdown voltage is further improved.
　また本実施の形態では、中央部においてはｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩが素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉよりも内周側に位置している。これにより、上記の距離Ｌ１は、上記の距離Ｌ２よりも小さくなっている。このため、中央部ではオン抵抗を低減することができる。 In the present embodiment, the inner peripheral edge DRII of the n-type drift region DRI is located on the inner peripheral side with respect to the inner peripheral edge IS1I of the element isolation structure IS1 in the central portion. Thus, the distance L1 is smaller than the distance L2. For this reason, the on-resistance can be reduced in the central portion.
　次に、本発明者が本実施の形態の構成と比較例Ａの構成との各々についてオフ耐圧を調べた結果について説明する。 Next, the results obtained by the inventor examining the off-breakdown voltage for each of the configuration of the present embodiment and the configuration of Comparative Example A will be described.
　本発明者は比較例Ａと本実施の形態とについてオフ耐圧を調べた。ここで比較例Ａは、図１（Ａ）、図１（Ｂ）および図２に示した本実施の形態の構成においてｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩの中間部分（コーナー部）が図１０（Ａ）、図１０（Ｂ）および図１１に示す比較例のようにラウンド形状となった構成を有している。それ以外の比較例Ａの構成は本実施の形態の構成とほぼ同じであるため、その説明を繰り返さない。 The inventor examined the off breakdown voltage for Comparative Example A and the present embodiment. Here, the comparative example A is an intermediate portion (corner portion) of the inner peripheral side edge DRII of the n-type drift region DRI in the configuration of the present embodiment shown in FIG. 1 (A), FIG. 1 (B) and FIG. However, it has the structure which became a round shape like the comparative example shown to FIG. 10 (A), FIG. 10 (B), and FIG. Since the structure of the comparative example A other than that is substantially the same as the structure of this Embodiment, the description is not repeated.
　また本実施の形態の構成および比較例Ａの構成の各々において、ｎ型ウエル領域ＮＷＲは１．５×１０12ｃｍ-2のドーズ量で形成した。またｎ型ドリフト領域ＤＲＩは７×１０12ｃｍ-2のドーズ量で形成した。 In each of the configuration of this embodiment and the configuration of Comparative Example A, the n-type well region NWR was formed with a dose of 1.5 × 10 12 cm −2 . The n-type drift region DRI was formed with a dose of 7 × 10 12 cm −2 .
　図１２の結果から、本実施の形態の構成では比較例Ａに比較して高いオフ耐圧が得られることが分かった。また本実施の形態の構成においては、ｎ型ドリフト領域ＤＲＩおよびｎ型ウエル領域ＮＷＲの双方の濃度が低いほどオフ耐圧が向上することが分かった。 From the results of FIG. 12, it was found that the off breakdown voltage higher than that of Comparative Example A can be obtained in the configuration of the present embodiment. In the configuration of the present embodiment, it has been found that the off breakdown voltage improves as the concentrations of both the n-type drift region DRI and the n-type well region NWR are lower.
　次に、本発明者がｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩと素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉとの位置関係を変えた場合にオフ耐圧がどのように変化するかを調べた結果について説明する。 Next, how the OFF breakdown voltage changes when the inventor changes the positional relationship between the inner peripheral edge DRII of the n-type drift region DRI and the inner peripheral edge IS1I of the element isolation structure IS1. The results of the investigation will be described.
　本発明者は、図１３に示すような構成においてｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩの位置を素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉの位置に対して変え、その各位置でのオフ耐圧を測定した。 The inventor changes the position of the inner peripheral edge DRII of the n-type drift region DRI with respect to the position of the inner peripheral edge IS1I of the element isolation structure IS1 in the configuration as shown in FIG. The off breakdown voltage was measured.
　測定に用いた図１３に示す構成は、図１（Ｂ）の領域Ｒ１付近の構成に対応している。なお図１３のｎ-領域ＮＬＤは図１（Ｂ）のｎ-領域ＮＬＤと実質的に同じ領域であり、図１３のｐ+ボディコンタクト領域ＰＢＣは図２のｐ+ボディコンタクト領域ＰＢＣと実質的に同じ領域である。 The configuration shown in FIG. 13 used for the measurement corresponds to the configuration near the region R1 in FIG. Note n in FIG. 13 - region NLD n in FIG. 1 (B) - a region NLD substantially the same region, p + body contact region PBC substantially the p + body contact region PBC in Figure 2 in FIG. 13 In the same area.
　またｎ型ウエル領域ＮＷＲは１．５×１０12ｃｍ-2のドーズ量で形成した。またｎ型ドリフト領域ＤＲＩは７×１０12ｃｍ-2のドーズ量で形成した。この構成を用いて測定した結果を図１４に示す。 The n-type well region NWR was formed with a dose of 1.5 × 10 12 cm −2 . The n-type drift region DRI was formed with a dose of 7 × 10 12 cm −2 . The result of measurement using this configuration is shown in FIG.
　なお図１４においては、ｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩの位置が、素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉの位置よりもｎ+ソース領域ＮＳＲ側にあるときは符号「＋」で表し、ｎ+ドレイン領域ＮＤＲ側にあるときは符号「－」で表している。 In FIG. 14, when the position of the inner peripheral edge DRII of the n-type drift region DRI is closer to the n + source region NSR than the position of the inner peripheral edge IS1I of the element isolation structure IS1, the sign “+ ”And“ − ”when it is on the n + drain region NDR side.
　図１４の結果から、ｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩの位置が、素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉの位置よりもｎ+ドレイン領域ＮＤＲ側に位置するほどオフ耐圧が向上することが分かった。またｎ型ドリフト領域ＤＲＩおよびｎ型ウエル領域ＮＷＲの双方の濃度が低いほどオフ耐圧が向上することが分かった。 From the result of FIG. 14, the off breakdown voltage increases as the position of the inner peripheral edge DRII of the n-type drift region DRI is located closer to the n + drain region NDR than the position of the inner peripheral edge IS1I of the element isolation structure IS1. It turns out that it improves. Further, it was found that the off breakdown voltage is improved as the concentrations of both the n-type drift region DRI and the n-type well region NWR are lower.
　（実施の形態２）
　図１５（Ａ）、図１５（Ｂ）および図１６を参照して、本実施の形態の構成は、実施の形態１の構成と比較して、平面視においてゲート電極層ＧＥの外周側端縁ＧＥＯの形状が長方形状である点において異なっている。 (Embodiment 2)
Referring to FIGS. 15A, 15B, and 16, the configuration of the present embodiment is compared with the configuration of Embodiment 1 in the plan view in the outer peripheral side edge of gate electrode layer GE. The difference is that the GEO has a rectangular shape.
　本実施の形態では、上記の構成によりゲート電極層ＧＥの内周側端縁ＧＥＩから外周側端縁ＧＥＯへ向かう方向の平面視における幅において、中央部においてゲート電極層ＧＥが素子分離構造ＩＳ１上に乗り上げる長さＧ１よりも、長軸方向の両端部の少なくとも一部（中間部分（コーナー部））においてゲート電極層ＧＥが素子分離構造ＩＳ１上に乗り上げる長さＧ２の方が大きい。 In the present embodiment, the gate electrode layer GE is formed on the element isolation structure IS1 in the center in the width in a plan view in the direction from the inner peripheral edge GEI to the outer peripheral edge GEO of the gate electrode layer GE with the above configuration. The length G2 over which the gate electrode layer GE rides on the element isolation structure IS1 is larger at least at a part (intermediate portion (corner portion)) of both end portions in the major axis direction than the length G1 that rides on the element isolation structure IS1.
　なお本実施の形態の上記以外の構成は実施の形態１の構成とほぼ同じであるため、同一の要素については同一の符号を付し、その説明を繰り返さない。 Since the configuration of the present embodiment other than the above is substantially the same as the configuration of the first embodiment, the same elements are denoted by the same reference numerals and description thereof is not repeated.
　本実施の形態によれば、中央部においてゲート電極層ＧＥが素子分離構造ＩＳ１上に乗り上げる長さＧ１よりも、両端部の中間部分（コーナー部）においてゲート電極層ＧＥが素子分離構造ＩＳ１上に乗り上げる長さＧ２の方が大きい。このため、その中間部分（コーナー部）においてＲＥＳＵＲＦ効果でゲート電界による空乏層が伸びやすくなる。よって、この長さＧ２を最適化することにより、実施の形態１よりもさらにオフ耐圧を向上させることができる。 According to the present embodiment, the gate electrode layer GE is placed on the element isolation structure IS1 in the middle portion (corner portion) at both ends rather than the length G1 where the gate electrode layer GE rides on the element isolation structure IS1 in the center. The ride length G2 is larger. For this reason, the depletion layer due to the gate electric field is easily extended by the RESURF effect in the intermediate portion (corner portion). Therefore, by optimizing this length G2, the off breakdown voltage can be further improved as compared with the first embodiment.
　（実施の形態３）
　図１７（Ａ）、図１７（Ｂ）および図１８を参照して、本実施の形態の構成は、実施の形態１の構成と比較して、平面視においてｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩが両端部の中央箇所において素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉよりも外周側に位置している点において異なっている。 (Embodiment 3)
Referring to FIGS. 17A, 17B, and 18, the configuration of the present embodiment is the inner peripheral side of n-type drift region DRI in plan view as compared with the configuration of the first embodiment. The difference is that the end edge DRII is located at the outer peripheral side of the inner peripheral side edge IS1I of the element isolation structure IS1 at the center of both ends.
　本実施の形態では、上記の構成により両端部の中央箇所におけるｐ型ボディ領域ＢＲの外周側端縁ＢＲＯとｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩとの距離Ｌ３は、中央部におけるｐ型ボディ領域ＢＲの外周側端縁ＢＲＯとｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩとの距離Ｌ１よりも大きくなっている。 In the present embodiment, the distance L3 between the outer peripheral side edge BRO of the p-type body region BR and the inner peripheral side edge DRII of the n-type drift region DRI at the central part of both ends is set to be p at the central part. It is larger than the distance L1 between the outer peripheral side edge BRO of the type body region BR and the inner peripheral side edge DRII of the n-type drift region DRI.
　また上記の構成により、両端部の中央箇所においても、図１８に示す中間部分（コーナー部）と同様に素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉは、ｎ型ドリフト領域ＤＲＩによって覆われておらず、ｎ型ウエル領域ＮＷＲと接している。 Further, with the above configuration, the inner peripheral side edge IS1I of the element isolation structure IS1 is also covered with the n-type drift region DRI in the central portion of both end portions as in the intermediate portion (corner portion) shown in FIG. First, it is in contact with the n-type well region NWR.
　なお本実施の形態の上記以外の構成は実施の形態１の構成とほぼ同じであるため、同一の要素については同一の符号を付し、その説明を繰り返さない。 Since the configuration of the present embodiment other than the above is substantially the same as the configuration of the first embodiment, the same elements are denoted by the same reference numerals and description thereof is not repeated.
　本実施の形態によれば、両端部の中間部分（コーナー部）だけでなく中央箇所（直線部）においてもｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩが素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉよりも外周側に位置している。このため、中央箇所においても電界集中によるオフ耐圧の低下を抑制することができる。 According to the present embodiment, the inner peripheral edge DRII of the n-type drift region DRI is not only the intermediate portion (corner portion) at both ends but also the central portion (straight portion), and the inner peripheral end of the element isolation structure IS1. It is located on the outer peripheral side with respect to the edge IS1I. For this reason, it is possible to suppress a decrease in off breakdown voltage due to electric field concentration even at the central portion.
　上記の実施の形態１～３においては、素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉの平面形状が、中央部および両端部の中央箇所が直線形状よりなり、中間部分がラウンド形状よりなる略トラック形状の場合について説明した。しかし素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉの平面形状は、平面視において互いに直交する長軸方向と短軸方向とにおいて短軸方向よりも長軸方向に長く延びる平面形状を有していればよい。素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉの平面形状は、上記の略トラック形状以外に、たとえば中央部が直線形状よりなり両端部の各々が半円形状よりなるトラック形状であってもよく、また楕円形状であってもよい。楕円形状の場合、楕円の２つの焦点の間が上記の中央部に該当し、その焦点よりも長軸方向外側が上記の端部に該当する。 In the above first to third embodiments, the planar shape of the inner peripheral edge IS1I of the element isolation structure IS1 is a substantially track in which the central portion and the central portion of both end portions are linear, and the intermediate portion is round. The case of the shape has been described. However, the planar shape of the inner peripheral edge IS1I of the element isolation structure IS1 may have a planar shape that extends longer in the major axis direction than in the minor axis direction in the major axis direction and the minor axis direction orthogonal to each other in plan view. That's fine. The planar shape of the inner peripheral side edge IS1I of the element isolation structure IS1 may be, for example, a track shape in which the central portion has a linear shape and both end portions have semicircular shapes, Moreover, an elliptical shape may be sufficient. In the case of an ellipse, the center between the two focal points of the ellipse corresponds to the central part, and the outer side in the major axis direction corresponds to the end part.
　また実施の形態１～３のｐ型ボディ領域ＢＲの外周側端縁ＢＲＯ、実施の形態１のゲート電極層ＧＥの外周側端縁ＧＥＯ、実施の形態２の素子分離構造ＩＳ１の外周側端縁ＩＳ１Ｏ、および素子分離構造ＩＳ２の内周側端縁ＩＳ２Ｉも、上記の略ラウンド形状に限定されるものではない。これらの外周側端縁ＢＲＯ、ＧＥＯ、ＩＳ１Ｏおよび内周側端縁ＩＳ２Ｉの各々は、平面視において互いに直交する長軸方向と短軸方向とにおいて短軸方向よりも長軸方向に長く延びる平面形状を有していればよく、たとえばトラック形状、楕円形状などであってもよい。 Further, the outer peripheral edge BRO of the p-type body region BR of the first to third embodiments, the outer peripheral edge GEO of the gate electrode layer GE of the first embodiment, and the outer peripheral edge of the element isolation structure IS1 of the second embodiment The IS1O and the inner peripheral side edge IS2I of the element isolation structure IS2 are not limited to the substantially round shape described above. Each of the outer peripheral side edges BRO, GEO, IS1O and the inner peripheral side edge IS2I has a planar shape extending longer in the major axis direction than in the minor axis direction in the major axis direction and the minor axis direction orthogonal to each other in plan view. For example, a track shape, an ellipse shape, etc. may be sufficient.
　また上記の実施の形態１～３においては、ｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩの平面形状が長方形状である場合について説明した。しかし、ｎ型ドリフト領域ＤＲＩの内周側端縁ＤＲＩＩの平面形状は、上記長軸方向の両端部の少なくとも一部で素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉよりも外周側に位置し、両端部に挟まれる長軸方向の中央部で素子分離構造ＩＳ１の内周側端縁ＩＳ１Ｉよりも内周側に位置する形状であれば如何なる形状であってもよい。また上記において長方形状とは、長方形の角部が微視的に見てラウンドしているものも含む。 In the first to third embodiments, the case where the planar shape of the inner peripheral edge DRII of the n-type drift region DRI is rectangular has been described. However, the planar shape of the inner peripheral edge DRII of the n-type drift region DRI is located on the outer peripheral side with respect to the inner peripheral edge IS1I of the element isolation structure IS1 in at least a part of both ends in the major axis direction. Any shape may be employed as long as the shape is located on the inner peripheral side with respect to the inner peripheral side edge IS1I of the element isolation structure IS1 in the central portion in the major axis direction sandwiched between both ends. In addition, in the above, the rectangular shape includes those in which the corners of the rectangle are rounded when viewed microscopically.
　また実施の形態１～３においてｎ+ドレイン領域ＮＤＲ、ｎ+ソース領域ＮＳＲ、ｐ+ボディコンタクト領域ＰＢＣおよびゲート電極層ＧＥの各々の表面上にシリサイドが形成されていなくてもよい。またｎ+ソース領域ＮＳＲやボディコンタクト領域ＰＢＣの横のｎ-領域ＮＬＤは省略されてもよい。 In the first to third embodiments, silicide may not be formed on the surfaces of n + drain region NDR, n + source region NSR, p + body contact region PBC, and gate electrode layer GE. Further, the n + source region NSR and the n − region NLD beside the body contact region PBC may be omitted.
　また実施の形態１～３においてはＭＩＳトランジスタＴＲについて説明したが、トランジスタは、ゲート絶縁層ＧＩがシリコン酸化膜よりなるＭＯＳトランジスタであってもよい。 Although the MIS transistor TR has been described in the first to third embodiments, the transistor may be a MOS transistor in which the gate insulating layer GI is made of a silicon oxide film.
　今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
　本発明は、ラテラル構造のトランジスタを有する半導体装置に特に有利に適用され得る。 The present invention can be applied particularly advantageously to a semiconductor device having a lateral structure transistor.
　ＢＲ　ｐ型ボディ領域、ＢＲＯ，ＤＲＩＯ，ＧＥＯ，ＩＳ１Ｏ　外周側端縁、ＤＲＩ　ｎ型ドリフト領域、ＤＲＩＩ，ＧＥＩ，ＩＳ１Ｉ，ＩＳ２Ｉ　内周側端縁、ＧＥ　ゲート電極層、ＧＩ　ゲート絶縁層、ＩＣＬ　配線層、ＩＬ　絶縁層、ＩＳ１，ＩＳ２　素子分離構造、ＬＮＷ　ｎ型領域、ＮＤＲ　ｎ+ドレイン領域、ＮＬＤ　ｎ-領域、ＰＲ　ｐ-領域、ＮＳＲ　ｎ+ソース領域、ＮＷＲ　ｎ型ウエル領域、ＰＢＣ　ボディコンタクト領域、ＰＬ　プラグ層、ＰＳＤＲ　コンタクト領域、ＰＷＲ　ｐ型ウエル領域、ＳＣ　シリサイド層、ＳＵＢ　半導体基板、ＳＷ　側壁絶縁層、ＴＲ　ＭＩＳトランジスタ、ＴＲＥ　溝。 BR p-type body region, BRO, DRIO, GEO, IS1O outer peripheral side edge, DRI n-type drift region, DRII, GEI, IS1I, IS2I inner peripheral side edge, GE gate electrode layer, GI gate insulating layer, ICL wiring layer , IL insulating layer, IS1, IS2 element isolation structure, LNW n-type region, NDR n + drain region, NLD n − region, PR p − region, NSR n + source region, NWR n-type well region, PBC body contact region, PL plug layer, PSDR contact region, PWR p-type well region, SC silicide layer, SUB semiconductor substrate, SW sidewall insulating layer, TR MIS transistor, TRE trench.

Claims (8)

  1. 　主表面を有する半導体基板（ＳＵＢ）と、
    　前記主表面に配置された第１導電型のソース領域（ＮＳＲ）と、
    　平面視において前記ソース領域（ＮＳＲ）の周囲を取り囲むように前記半導体基板（ＳＵＢ）内に配置された第２導電型のボディ領域（ＢＲ）と、
    　平面視において前記ボディ領域（ＢＲ）と間隔をあけて前記ボディ領域（ＢＲ）の周囲を取り囲むように配置された素子分離構造（ＩＳ１）と、
    　平面視において前記ボディ領域（ＢＲ）と間隔をあけて前記ボディ領域（ＢＲ）の周囲を取り囲むように、かつ前記素子分離構造（ＩＳ１）の下面に接するように前記半導体基板（ＳＵＢ）内に配置された第１導電型のドリフト領域（ＤＲＩ）と、
    　平面視において前記ソース領域（ＮＳＲ）の周囲を取り囲み、かつ前記ボディ領域（ＢＲ）上および前記素子分離構造（ＩＳ１）上に配置されたゲート電極層（ＧＥ）とを備え、
    　前記ドリフト領域（ＤＲＩ）の内周側端縁（ＤＲＩＩ）および前記素子分離構造（ＩＳ１）の内周側端縁（ＩＳ１Ｉ）の各々は、平面視にて互いに直交する長軸方向と短軸方向とにおいて前記短軸方向よりも前記長軸方向に長く延びる平面形状を有し、
    　平面視において前記ドリフト領域（ＤＲＩ）の前記内周側端縁（ＤＲＩＩ）は、前記長軸方向の両端部の少なくとも一部で前記素子分離構造（ＩＳ１）の前記内周側端縁（ＩＳ１Ｉ）よりも外周側に位置し、かつ前記両端部に挟まれる前記長軸方向の中央部で前記素子分離構造（ＩＳ１）の前記内周側端縁（ＩＳ１Ｉ）よりも内周側に位置している、半導体装置。     A semiconductor substrate (SUB) having a main surface;
    A source region (NSR) of a first conductivity type disposed on the main surface;
    A second conductivity type body region (BR) disposed in the semiconductor substrate (SUB) so as to surround the periphery of the source region (NSR) in plan view;
    An element isolation structure (IS1) disposed so as to surround the body region (BR) at a distance from the body region (BR) in plan view;
    Arranged in the semiconductor substrate (SUB) so as to surround the body region (BR) with a space from the body region (BR) in plan view and to contact the lower surface of the element isolation structure (IS1). A first conductivity type drift region (DRI),
    A gate electrode layer (GE) surrounding the source region (NSR) in plan view and disposed on the body region (BR) and the element isolation structure (IS1);
    Each of the inner peripheral side edge (DRII) of the drift region (DRI) and the inner peripheral side edge (IS1I) of the element isolation structure (IS1) has a major axis direction and a minor axis direction orthogonal to each other in plan view. And having a planar shape extending longer in the major axis direction than in the minor axis direction,
    In plan view, the inner peripheral edge (DRII) of the drift region (DRI) is at least a part of both ends in the major axis direction, and the inner peripheral edge (IS1I) of the element isolation structure (IS1). Is located on the outer peripheral side, and is located on the inner peripheral side with respect to the inner peripheral side edge (IS1I) of the element isolation structure (IS1) at the central portion in the major axis direction sandwiched between the both ends. , Semiconductor devices.
  2. 　前記長軸方向の両端部の少なくとも一部における前記ドリフト領域（ＤＲＩ）の前記内周側端縁（ＤＲＩＩ）と前記ボディ領域（ＢＲ）の外周側端縁（ＢＲＯ）との間の距離（Ｌ２）は、前記中央部における前記ドリフト領域（ＤＲＩ）の前記内周側端縁（ＤＲＩＩ）と前記ボディ領域（ＢＲ）の前記外周側端縁（ＢＲＯ）との間の距離（Ｌ１）よりも大きい、請求項１に記載の半導体装置。 The distance (L2) between the inner peripheral edge (DRII) of the drift region (DRI) and the outer peripheral edge (BRO) of the body region (BR) in at least a part of both ends in the long axis direction ) Is larger than the distance (L1) between the inner peripheral edge (DRII) of the drift region (DRI) and the outer peripheral edge (BRO) of the body region (BR) in the central portion. The semiconductor device according to claim 1.
  3. 　前記素子分離構造（ＩＳ１）の前記内周側端縁（ＩＳ１Ｉ）と前記外周側端縁（ＩＳ１Ｏ）との間の平面視における幅において、前記中央部における前記素子分離構造（ＩＳ１）の幅（Ｗ１）よりも前記長軸方向の両端部の少なくとも一部における前記素子分離構造（ＩＳ１）の幅（Ｗ２）の方が大きい、請求項１に記載の半導体装置。 In the width in plan view between the inner peripheral edge (IS1I) and the outer peripheral edge (IS1O) of the element isolation structure (IS1), the width of the element isolation structure (IS1) in the central portion ( The semiconductor device according to claim 1, wherein a width (W2) of the element isolation structure (IS1) at least at a part of both ends in the major axis direction is larger than W1).
  4. 　前記長軸方向の前記両端部は、前記長軸方向の端となる中央箇所と、前記中央箇所および前記中央部の間に位置する中間部分とを含み、
    　前記長軸方向の前記中央箇所においては前記ドリフト領域（ＤＲＩ）の前記内周側端縁（ＤＲＩＩ）は前記素子分離構造（ＩＳ１）の内周側端縁（ＩＳ１Ｉ）よりも内周側に位置し、前記中間部分においては前記ドリフト領域（ＤＲＩ）の前記内周側端縁（ＤＲＩＩ）は前記素子分離構造（ＩＳ１）の内周側端縁（ＩＳ１Ｉ）よりも外周側に位置する部分を有している、請求項１に記載の半導体装置。     The both end portions in the major axis direction include a central portion serving as an end in the major axis direction, and an intermediate portion located between the central portion and the central portion,
    In the central portion in the long axis direction, the inner peripheral edge (DRII) of the drift region (DRI) is located on the inner peripheral side of the inner peripheral edge (IS1I) of the element isolation structure (IS1). In the intermediate portion, the inner peripheral edge (DRII) of the drift region (DRI) has a portion located on the outer peripheral side with respect to the inner peripheral edge (IS1I) of the element isolation structure (IS1). The semiconductor device according to claim 1.
  5. 　前記長軸方向の前記両端部は、前記長軸方向の端となる中央箇所と、前記中央箇所および前記中央部の間に位置する中間部分とを含み、
    　前記長軸方向の前記中央箇所および前記中間部分の双方において前記ドリフト領域（ＤＲＩ）の前記内周側端縁（ＤＲＩＩ）は前記素子分離構造（ＩＳ１）の内周側端縁（ＩＳ１Ｉ）よりも外周側に位置している、請求項１に記載の半導体装置。     The both end portions in the major axis direction include a central portion serving as an end in the major axis direction, and an intermediate portion located between the central portion and the central portion,
    The inner peripheral side edge (DRII) of the drift region (DRI) is more than the inner peripheral side edge (IS1I) of the element isolation structure (IS1) at both the central portion and the intermediate portion in the long axis direction. The semiconductor device according to claim 1, which is located on an outer peripheral side.
  6. 　前記ゲート電極層（ＧＥ）の内周側端縁（ＧＥＩ）から外周側端縁（ＧＥＯ）へ向かう方向の平面視における幅において、前記中央部において前記ゲート電極層（ＧＥ）が前記素子分離構造（ＩＳ１）上に乗り上げる長さ（Ｇ１）よりも、前記長軸方向の両端部の少なくとも一部において前記ゲート電極層（ＧＥ）が前記素子分離構造（ＩＳ１）上に乗り上げる長さ（Ｇ２）の方が大きい、請求項１に記載の半導体装置。 The gate electrode layer (GE) has the element isolation structure in the central portion in a width in a plan view in a direction from the inner peripheral edge (GEI) to the outer peripheral edge (GEO) of the gate electrode layer (GE). The length (G2) that the gate electrode layer (GE) rides on the element isolation structure (IS1) in at least a part of both ends in the major axis direction, rather than the length (G1) that rides on (IS1). The semiconductor device according to claim 1, wherein the semiconductor device is larger.
  7. 　前記ドリフト領域（ＤＲＩ）の内周側端縁（ＤＲＩＩ）は、長方形の平面形状を有し、
    　前記素子分離構造（ＩＳ１）の前記内周側端縁（ＩＳ１Ｉ）は、長方形の角部となるべき部分がラウンド形状となった平面形状を有する、請求項１に記載の半導体装置。     The inner peripheral edge (DRII) of the drift region (DRI) has a rectangular planar shape,
    The semiconductor device according to claim 1, wherein the inner peripheral edge (IS1I) of the element isolation structure (IS1) has a planar shape in which a portion that should become a rectangular corner is round.
  8. 　前記ドリフト領域（ＤＲＩ）と接するように前記半導体基板（ＳＵＢ）内の前記主表面に配置され、かつ前記ドリフト領域（ＤＲＩ）よりも高い第１導電型の不純物濃度を有する第１導電型のドレイン領域（ＮＤＲ）をさらに備えた、請求項１に記載の半導体装置。 A first conductivity type drain disposed on the main surface in the semiconductor substrate (SUB) so as to be in contact with the drift region (DRI) and having a first conductivity type impurity concentration higher than that of the drift region (DRI). The semiconductor device according to claim 1, further comprising a region (NDR).
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